JP2926657B2 - Digital envelope generator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital envelope generator for generating an envelope of a modulated wave by digital processing. INDUSTRIAL APPLICABILITY The present invention is suitable for use as an apparatus for generating an envelope of a modulated wave for bias control of a power amplifier.

The present invention is to generate an envelope having relatively high accuracy with a small amount of memory by generating outputs having different accuracy depending on the amplitude of the envelope.

[Conventional technology]

As a device for transmitting a linear modulation wave with high power efficiency, a drain voltage control type linear transmission device is known. The drain voltage control type linear transmitter controls a drain bias voltage by an envelope signal of a modulated wave, thereby operating a power amplifier in a saturated state to obtain high power efficiency.

The present inventors have proposed such a linear transmission device,
We have invented a technique for obtaining the envelope of a modulated wave used for drain control by digital processing, and have already filed a patent application (Japanese Patent Application No. 1-168723, hereinafter referred to as "prior application"). In this device, the envelope of the modulated wave is obtained from the in-phase envelope component and the orthogonal envelope component of the modulated wave by digital arithmetic processing in a baseband.

The in-phase and quadrature envelope components are represented by I
(T) and Q (t), the envelope signal R (t) of the modulated wave orthogonally modulated by I (t) and Q (t) is R (t) = [I (t) ² + Q (T) ² ] ^1/2 ... (1) To perform this calculation, there are a method using a numerical calculation processor and a method using a memory table using a read-only memory or the like. FIG. 14 shows an example of an envelope generating apparatus using a read-only memory.

When a read-only memory is used as the envelope generator, I (t) and Q (t), each of which is quantized by N bits, are input to the address input. At this time, for example, I (t) is input to addresses A _{0 to} A _N−1 and
(T) is input to the address A _N ~A _2N-1. The value of R (t) calculated based on equation (1) is written in the read-only memory, and when I (t) and Q (t) are input, they are written to the corresponding addresses. R
Output the value of (t). Thus, I (t), Q
From (t), an envelope signal R (t) of the modulated wave can be generated.

[Problems to be solved by the invention]

However, when a read-only memory is used as the envelope generating device, there is a problem that the amount of memory increases in order to generate an envelope with high accuracy.

That is, when the number of bits of I (t) and Q (t) is N and the number of bits of the envelope is M, the address value of the read-only memory is 2 ^N × 2 ^N , and each address has M bits. Memory is required, and the total memory is 2 ^N ×
2 ^N × M bits are required.

If N = 8 and M = 10, the total memory required is
Although it is 640 k bits, if the precision of I (t) and Q (t) is increased by 2 bits each and N = 10, then 2 ² × 2 ² = 16
Twice the amount of memory is required, for a total memory of 10 Mbits. Such a large capacity memory is currently one chip LS
It is difficult to implement I, and it must be configured with multiple LSI memories. For this reason, the cost becomes extremely high,
This hindered miniaturization.

An object of the present invention is to solve such a problem and to provide a digital envelope generation device capable of generating an envelope of a modulated wave with high accuracy and a small memory amount.

[Means for solving the problem]

The digital envelope generating apparatus according to the present invention includes means for obtaining two envelopes having different precisions from the same envelope component, and the amplitude of an envelope output for the two input envelope components is predetermined. And a selecting means for selecting one of two envelopes having different precisions based on the judgment output of the amplitude judging means.

The means for obtaining the two envelopes includes first circuit means for obtaining the envelope using the respective upper K + n bits when the two input envelope components are each represented by a positive integer N bits, Second circuit means for determining the envelope using the lower [NK] bits.
Here, K and n are positive integers, respectively, 1 ≦ K <N,
K + n ≦ N. It is desirable that the first circuit means be configured to obtain an envelope from all bits of two envelope components, that is, K + n = N.

The first circuit means includes a square calculating means for obtaining respective square values for the two envelope components, an adding means for adding the two square values output from the square calculating means, and an output of the adding means. Means for calculating the square root of the sum of squared values to be calculated.The square calculating means and the square root calculating means each include a memory table in which an output value corresponding to an input value is written in advance, and the input value is used as an address value of the memory table. It is desirable that the memory table is read out by giving the memory table.

The square calculating means may be configured to switch and use the same memory table in a time-division manner.

The second circuit means includes a memory table in which an output value with respect to an input value is written in advance, and gives the lower [NK] bits of each of the two envelope components as an address value of the memory table to store the memory table. It is desirable to have a configuration for reading.

In this configuration, the amplitude judging means selects one of the upper K bits of the two input envelope components, the output of the adding means in the first circuit means, or the output of the first circuit means (the output of the square root calculating means). Can be used to determine the amplitude value.

Apart from the above configuration, the means for obtaining the two envelopes also includes a square operation means for obtaining the respective square values for the two envelope components, and two square values output from the square operation means. And a square root calculating means for calculating a square root of a square addition value output from the adding means. The square calculating means and the square root calculating means provide the input value as an address value, and wherein each memory table for outputting a previously written value against, when the square root calculation means, the output of the adding means is represented by J bits, the first square root operation memory the upper L ₁ bits is supplied as an address value Table and lower L ₂
And a second square root operation memory table in which bits are given as address values. Here, J, L ₁ and L ₂ are positive integers, and L ₁ , L ₁ <J and L ₁
There is a relationship of + L ₂ ≧ J.

Also in this case, it is possible to adopt a configuration in which the square computing means switches and uses the same memory table in a time-division manner.

In the case of this configuration, the amplitude determining means can determine the amplitude value using either of the two input envelope components, the output of the adding means, or the output of the first square root operation memory table.

(Operation)

The envelope signal R (t) is obtained as the square root of the sum of squares of the two in-phase and quadrature envelope components I (t) and Q (t) as shown in Expression (1). Here, when the amplitude of the envelope is large, the envelope components I (t), Q (t),
Regarding the square value and the square addition value, even if the lower bits are ignored, the accuracy does not decrease so much. On the other hand, when the amplitude is small, the upper bit is zero over a plurality of digits, and it is not necessary to input the address of the memory table.

Therefore, different processing is performed when the amplitude is large and when the amplitude is small. That is, when the amplitude is large, the number of bits necessary for the square addition value and the process of obtaining the square root from the value are reduced, and when the amplitude is small, a memory table having a small number of input addresses is used.

FIG. 1 is a block diagram showing a digital envelope generating apparatus according to a first embodiment of the present invention.

This device is a digital envelope generating device that receives two envelope components orthogonal to each other and obtains an envelope represented by the square root of the sum of squares of the two envelope components by digital processing. Characteristically, as means for obtaining two envelopes having different precisions from the same envelope component, first circuit means constituted by square operation ROMs 3, 4, a digital adder 5 and a square root operation ROM 6; A second circuit means constituted by a line generation ROM 7, and an amplitude judgment for judging whether the amplitude of an envelope output for two input envelope components is larger or smaller than a predetermined value. Amplitude determination circuit 8 as means
And an output selection circuit 9 as selection means for selecting one of two envelopes having different precisions based on the judgment output of the amplitude judgment circuit 8.

Input terminals 1 and 2 respectively have an in-phase envelope component I
(T), an orthogonal envelope component Q (t) is input. Here, the number of quantization bits of I (t) and Q (t) is N
Let it be a bit.

The square operation ROMs 3 and 4 are respectively N-bit I (t),
Q (t) is used as an address input, and a previously written square operation result is output. The digital adder 5
The outputs of the square operation ROMs 3 and 4 are added. Square root operation ROM6
Takes the output of the digital adder 5 as an address input and outputs a previously written square root operation result in response to this input. As a result, [I (t) ² + Q (t) ² ] ^1/2 is obtained in the output of the square root operation ROM 6.

The envelope generation ROM 7 receives a signal excluding the upper K bits of I (t) and Q (t) as an address input, and in response to the input, an envelope signal [I (t) written in advance.
² + Q (t) ² ] ^1/2 is output.

The amplitude judging circuit 8 examines the upper K bits of I (t) and Q (t), and when all the bits are zero, the output selecting circuit 9
Select the output of the envelope generation ROM 7 and connect it to the output terminal 10. Otherwise, the output of the square root operation ROM 6 is selected and connected to the output terminal 10.

FIG. 2 shows a method of distributing I (t) and Q (t) to each circuit.

If the number of quantization bits of I (t) and Q (t) is N bits, consider that the output is a square value in order to maintain the same accuracy as the input side at the outputs of the square operation ROMs 3 and 4. Then, each requires 2N bits. Further, in order to add the outputs of the square operation ROMs 3 and 4 while maintaining the accuracy, the number of output bits of the digital adder 5 is [2N +
1] bits are required. Therefore, the square root operation ROM6
Also requires [2N + 1] bits as the number L of input bits. However, if the input of the square root operation ROM 6 does not become zero or a value close to zero, the number of input bits L (further, the number of output bits of the square operation ROMs 3 and 4 and the number of operation bits by the digital adder 5) are reduced. However, the effect of the quantization error is small. This principle will be described below.

 FIG. 3 shows the input / output relationship of the square root operation.

In the square root operation, when the input x is relatively small,
The variation Δy _{1 of} y with respect to the variation Δx of x is large. Conversely, when the input x is relatively large, the variation Δy _{2 of} y with respect to the variation of x is small. Therefore, when the value of x is small, a small error Δx due to quantization gives a large error to the output, but when the value of x is large, the output error due to the error Δx due to quantization is small. For this reason, when there is no input of a small value, the output accuracy can be maintained even if the number of input bits of the square root operation is not so large.

Applying this to the embodiment shown in FIG. 1, when the input of the square root operation ROM 6 does not become zero or close to it, that is, the envelope of the modulated wave whose amplitude does not become zero or a value close to it is obtained. In the case of generation, the number of input bits of the square root operation ROM 6 can be reduced from [2N + 1], and the memory amount can be reduced. Further, the number of output bits of the square operation ROMs 3 and 4 can be reduced, and the amount of memory can be reduced.

Here, the number of bits N of I (t) and Q (t) is 10, and
The number of output bits of the square operation ROMs 3 and 4 is 10 which is half of 2N,
A case where the number of output bits M of the square root operation ROM 6 is 10 will be described.

Since the number of output bits of the square operation ROMs 3 and 4 is 10 bits, the number of input bits of the digital adder 5 is also 10 bits.
Bit. The number of output bits of the digital adder 5 is
In consideration of carry due to addition, the number of bits becomes 11 bits obtained by adding 1 bit to the number of input bits. The amount of memory at this time is that the square operation ROMs 3 and 4 each have 10 k bits, and the square root operation ROM 6 has 20 k bits.
Bits, for a total of 40k bits.

FIG. 4 shows the difference in the envelope output between the case where the number of input bits L of the square root operation ROM 6 is 11 and the case where 2N + 1 = 21 bits. In this figure, the value of the envelope when L = 21 on the vertical axis
Take R _1, taking a value R ₂ of the envelope in the case of the L = 11 on the horizontal axis.

As shown in this figure, when the envelope amplitude is zero or a value close thereto, the error in the output is larger when R = 11 and R ₁ ≠ R ₂ than when L = 21. Otherwise, R ₁ = R ₂ .

FIG. 5 shows an example of the spectrum of the envelope output. FIG. 5 (a) shows the spectrum obtained by the comparative example, and FIG. 5 (b) shows the spectrum obtained by the example of the memory configuration described above. In this example, a π / 4 shift QPSK modulated wave (roll-off rate 0.5) was used as a modulated wave whose envelope amplitude does not become zero.

In the comparative example shown in FIG. 5 (a), an envelope is directly obtained from an envelope component in one memory table using a memory of 600 k bits. The number of bits N of I (t) and Q (t) is 8 bits, which is two bits smaller than that of the embodiment shown in (b), and the number of output bits M is 10 bits, which is the same as in the embodiment.

As shown in FIG. 5, the number of bits N of I (t) and Q (t) is increased even though the memory amounts of the square operation ROMs 3 and 4 and the square root operation ROM 6 are 1/15 of the comparative example. As a result, the quantization noise level can be improved by about 3 dB. In this configuration, an L-bit digital adder 5 is required as compared with the case where processing is performed with one memory table, but the circuit scale for performing the addition of about 10 bits is 200
It is about the gate, and can be ignored compared to the circuit size of the ROM. Therefore, it can be easily integrated into a one-chip LSI together with three ROMs.

However, in the processing by the square operation ROMs 3 and 4, the digital adder 5, and the square root operation ROM 6, when the amplitude of the envelope is close to zero, the output accuracy of the square root operation ROM 6 decreases as shown in FIG.

Therefore, when the amplitude decreases, the envelope generation ROM 7
Select the output of, to prevent a decrease in accuracy. Envelope generation ROM7
Since the bits except for the upper K bits of I (t) and Q (t) are used as the address input, the number of address input bits is reduced by 2K bits in total. That is, the envelope generation RO
M7 memory capacity can be reduced to 1 / ^22K . In addition, a correct envelope cannot be generated for an input that uses the upper K bits, but for an envelope having a small amplitude that does not require the use of the upper K bits, there is no loss of digits during the calculation. Therefore, an extremely accurate envelope can be generated.

Therefore, when the upper K bits are all zero, the output of the envelope generation ROM 7 is selected, and otherwise, the output of the square root operation ROM 6 is selected, so that the accuracy is obtained regardless of the amplitude of the envelope. Envelopes can be generated well.

FIG. 6 is a block diagram showing a digital envelope generating apparatus according to a second embodiment of the present invention.

This embodiment differs from the first embodiment in that the magnitude of the envelope is not determined from I (t) and Q (t) but is determined by the output of the digital adder 5. Other configurations and operations are the same as those of the first embodiment.

FIG. 7 is a block diagram showing a digital envelope generating apparatus according to a third embodiment of the present invention.

This embodiment differs from the first embodiment in that the magnitude of the envelope is not determined from I (t) and Q (t) but is determined by the output of the square root operation ROM 6. Other configurations and operations are the same as those of the first embodiment.

FIG. 8 is a block diagram showing a digital envelope generating apparatus according to a fourth embodiment of the present invention.

The first embodiment differs from the first embodiment in that instead of using separate squaring ROMs 3 and 4 for the input of I (t) and Q (t), the squaring ROM 12 is used in a time-sharing manner. different. Squared operation ROM in the first to third embodiments
3 and 4 store exactly the same data. Therefore,
By reducing this to one and performing operations on I (t) and Q (t) in a time-division manner, the amount of memory can be further reduced.

That is, I (t) input from the input terminals 1 and 2,
Q (t) is selected by the input selection circuit 11, and the square operation ROM1 is selected.
By selecting the output of 2 by the output selection circuit 13,
The square operation ROM 12 is used in time division. Input selection is I
(T) and Q (t) are alternately sampled at twice the frequency. Output selection can be performed by using a latch circuit or the like.

In this embodiment, the amplitudes of the envelopes are I (t) and Q (t).
However, as in the second embodiment or the third embodiment, the determination may be made based on the output of the digital adder 5 or the output of the square root operation ROM 6.

FIG. 9 is a block diagram showing a digital envelope generating apparatus according to a fifth embodiment of the present invention.

In this embodiment, instead of generating two envelopes by separating I (t) and Q (t), two envelopes are generated at the stage of finding the square root of the sum of squares. And different. That it is an aspect of this embodiment, as the square root calculating means, when the output of the digital adder 5 is represented by J bits, a first square root ROM6-1 the upper L ₁ bits is supplied as an address value is to include a second square root ROM6-2 the lower L ₂ bits is supplied as an address value. J, L ₁ and L ₂ are positive integers, and L ₁ ,
There is a relationship of L ₂ <J and L ₁ + L ₂ ≧ J.

FIG. 10 shows the square root operation ROM 6 of the output of the digital adder 5.
The distribution method to -1, 6-2 is shown.

The square root operation ROM 6-2 receives the J bits output from the digital adder 5 except for the upper [J-L ₂ ] bits. For this reason, a correct envelope cannot be generated for an input that uses such high-order bits. However, all the high-order [J-L ₂ ] bits are zero, that is, for an envelope with a small amplitude, A more accurate output can be generated as compared with the square root operation ROM 6-1 which operates without bits.

Therefore, the amplitude judging circuit 8 examines the upper [J-L ₂ ] bits of the output of the digital adder 5, and when all are zero, the output selecting circuit 9 selects the output of the square root operation ROM 6-2 and outputs it. Connect to terminal 10. Also, the upper [J-L ₂ ]
If any of the bits are not zero, the square root operation ROM6
-1 is selected and connected to the output terminal 10. Thus, an envelope can be generated with high accuracy regardless of the magnitude of the amplitude of the envelope.

In the present embodiment, the provision of the square root operation ROM 6-2 increases the total amount of memory. However, even when L ₁ = 11, for example, the memory amount of the square root operation ROM 6-2 is about 20 k bits, which is very large. Not an increase.

FIG. 11 is a block diagram showing a digital envelope generating apparatus according to a sixth embodiment of the present invention.

This embodiment is different from the first embodiment in that the amplitude of the envelope is not determined by the output of the digital adder 5 but is determined by I (t) and Q (t) as in the first embodiment. Different from the fifth embodiment. Other configurations and operations are the same as those of the fifth embodiment.

FIG. 12 is a block diagram showing a digital envelope generating apparatus according to a seventh embodiment of the present invention.

The fifth embodiment is different from the third embodiment in that the magnitude of the amplitude of the envelope is determined not by the output of the digital adder 5 but by the output of the square root operation ROM 6-1 as in the third embodiment. Different from the example. Other configurations and operations are the same as those of the fifth embodiment.

FIG. 13 is a block diagram showing a digital envelope generating apparatus according to an eighth embodiment of the present invention.

This embodiment does not use separate squaring ROMs 3 and 4 for the input of I (t) and Q (t), but uses the squaring ROM 12 in a time-sharing manner as in the fourth embodiment. Is different from the fifth embodiment. In this embodiment, the amplitude of the envelope is determined based on the output of the digital adder 5. However, as in the sixth embodiment or the seventh embodiment, the amplitude of the envelope is determined.
The determination can be made based on the values of (t) and Q (t) or the output of the square root operation ROM 6-1.

〔The invention's effect〕

As described above, the digital envelope generation device of the present invention can generate the envelope of a modulated wave with high accuracy and a small memory amount. For this reason, when this device is integrated, the chip size can be reduced, and the cost and power consumption can be further reduced.

The digital envelope generating apparatus of the present invention has an effect that the whole apparatus can be reduced in size, cost and power consumption when used in a drain voltage controlled linear transmitting apparatus.

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital envelope generating apparatus according to a first embodiment of the present invention. FIG. 2 is a diagram showing a method of distributing I (t) and Q (t) to each circuit. FIG. 3 is a diagram showing an input-output relationship of a square root operation. FIG. 4 is a diagram showing a difference in envelope output between a case where the number of input bits L of the square root operation ROM is 11 and a case where 2N + 1 = 21 bits. FIG. 5 is a diagram showing an example of an envelope spectrum. FIG. 6 is a block diagram of a digital envelope generating apparatus according to a second embodiment of the present invention. FIG. 7 is a block diagram of a digital envelope generating apparatus according to a third embodiment of the present invention. FIG. 8 is a block diagram of a digital envelope generating apparatus according to a fourth embodiment of the present invention. FIG. 9 is a block diagram of a digital envelope generating apparatus according to a fifth embodiment of the present invention. FIG. 10 is a diagram showing a method of distributing the output of the digital adder. FIG. 11 is a block diagram of a digital envelope generating apparatus according to a sixth embodiment of the present invention. FIG. 12 is a block diagram of a digital envelope generating apparatus according to a seventh embodiment of the present invention. FIG. 13 is a block diagram of a digital envelope generating apparatus according to an eighth embodiment of the present invention. FIG. 14 is a block diagram of a conventional digital envelope generator. 1, 2, ... input terminals, 3, 4, 12, ... square operation ROM, 5
... Digital adder, 6, 6-1 and 6-2 ... Square root operation ROM, 7 ... Envelope generation ROM, 8 ... Amplitude judgment circuit,
9 ... output selection circuit, 10 ... output terminal, 11 ... input selection circuit, 13 ... output selection circuit.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-283803 (JP, A) JP-A-3-34709 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H03D 1/00 H03F 1/02

Claims (3)

(57) [Claims] 1. A digital envelope generating apparatus which receives two envelope components orthogonal to each other and obtains an envelope represented by a square root of a sum of squares of the two envelope components by digital processing. Means for obtaining two envelopes having different accuracy from the components; and amplitude determining means for determining whether the amplitude of the envelope output for the two input envelope components is larger or smaller than a predetermined value. Selecting means for selecting one of the two envelopes having different precisions based on the judgment output of the amplitude judging means. 2. The means for obtaining two envelopes includes: when two input envelope components are each represented by a positive integer N bits, the positive integers K and n satisfying 1 ≦ K <N and K + n ≦ N. The first circuit means for obtaining an envelope using each of the upper K + n bits, and the second circuit means for obtaining an envelope using each of the lower [NK] bits. Digital envelope generator. 3. The means for obtaining two envelopes comprises: a square operation means for obtaining respective square values for the two envelope components; and an addition means for adding two square values output from the square operation means. And a square root calculating means for calculating a square root of a square addition value output from the adding means, wherein the square calculating means and the square root calculating means provide an input value as an address value, and A memory table that outputs a value that has been written in advance, wherein the square root calculating means outputs a positive integer J
When expressed in bits, L _1, L ₂ <J and L ₁ + L ₂ ≧ J made with respect to the positive integer L _1, L _2, the first square root operation memory table the upper L ₁ bits is supplied as an address value And lower
L ₂ bits digital envelope generator according to claim 1 including a second square root operation memory table given as an address value.