JPH0132538B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a control method for monitoring and canceling an abnormal state such as an abnormal program loop in a device that executes a program in a computer system or the like.

(b) Technical background Many devices that execute programs or microprograms are used in computer systems and the like. In such a device, if there is an error in the program, the program may often become stuck in a loop state in which only a specific program step sequence is repeatedly executed. Once in this state, the device continues to remain in the loop without doing any useful work.

Generally, it is practically impossible to prove that there are no defects in a program, so some kind of release means is often provided to deal with the possibility of entering the above-mentioned state.

(c) Prior Art and Problems Conventionally, a mechanism called a watchdog timer or the like has been used to release the loop state as described above. This involves setting up a timer mechanism that generates an interrupt to the program after a certain period of time after startup, and creating a program that restarts the timer mechanism within the specified period of time if the program is operating normally. If the program enters into an abnormal loop and does not pass through the step of restarting the timer mechanism, this mechanism operates and generates an interrupt. If an interrupt occurs, at least the loop execution is interrupted and control can be transferred to a program for abnormality diagnosis.

However, such a method is insufficient, for example, if the abnormal loop includes a program step for restarting the timer mechanism, since the monitoring effect cannot be obtained. Also, since it is uneconomical to add a special mechanism for situations that occur rarely or will never occur, some better control method has been desired.

(d) Purpose of the Invention The purpose of the present invention is to provide a method which is more economical than the conventional method and which is capable of preventing a device from entering an abnormal loop that disables its own monitoring means such as a so-called watch/dog timer. Another object of the present invention is to provide a means for monitoring and canceling an abnormal loop, etc., which utilizes an interface monitoring mechanism and is capable of activating a routine for escaping the device from the state and taking necessary measures.

(e) Structure of the Invention According to the present invention, the purpose is to transfer an activation signal from a second device to a first device that executes a program;
In a system that transfers a confirmation signal from a first device that has received the activation signal to a second device, an error in which the activation signal occurs continuously by monitoring the alternation between the transferred activation signal and the confirmation signal. A monitoring means is provided that generates an interrupt in the first device when the state is detected, and the second device transmits the activation signal when it detects that the confirmation signal is not received within a predetermined time after sending the activation signal. This is achieved by a program control system characterized in that it is configured to generate the error state in a pseudo manner by re-occurring and have the monitoring means detect it.

That is, generally when a computer system is composed of a plurality of devices, there is a first device and a second device that exchange signals with each other. A mechanism is often installed between these devices to monitor the signal exchange interface, detecting abnormalities in the signal exchange sequence, etc., and preventing the expansion of abnormal conditions by proceeding with processing based on the incorrect signals. do. for that,
When detecting an abnormality in the interface, the detection mechanism generates an interrupt to the running program of the device on the signal receiving side, interrupts the processing of the device, and forcibly starts the program for handling the abnormality. In many cases, a method of taking appropriate measures is adopted. As such a monitoring mechanism, there is a mechanism that monitors the alternation of a start signal and its confirmation signal and generates an interrupt when an error is detected. To,
This is necessary for early detection of a situation where a previous command is lost due to the next command being issued by mistake.

If the interrupt means based on this detection mechanism is operated in the abnormal loop state, the purpose of canceling the loop can be achieved without providing any special means.

Therefore, as in the above configuration of the present invention, when there is no response signal from the first device within a certain period of time, the second device detects an abnormality in the first device, and in that case, the control signal between the two devices is changed. By using a mechanism that monitors transmission and reception, and ignoring the normal sequence in which activation signals and confirmation signals are generated alternately, the activation signal is forcibly generated again and sent to the first device.
By generating an interrupt to the device, it becomes possible to monitor and release an abnormal loop in the first device without providing a special mechanism.

(f) Embodiment of the invention FIG. 1 is a block diagram showing an embodiment of the invention. In the figure, 1 is a channel processing device (CHP) which is an example of a first device that executes a program monitored by implementing the present invention. A central processing unit (CPU) 2 is an example of a second device that exchanges signals with the CHP 1, and shares a part of the function of monitoring the CHP 1 by implementing the present invention.

As is well known, the CHP 1 has a function of controlling input/output operations of so-called peripheral devices of this computer system via a channel device, and the input/output operations are
It is started by a command from CPU2.

For this purpose, there is an interface between the CPU 2 and the CHP 1 that includes at least an activation source 3, a response line 4, and a command transfer line 5 for exchanging signals. CPU2
When sending a command, the command data is transferred to the command transfer line 5.
At the same time, a start signal pulse is sent on the start line 3 as a start signal to convey command transfer to the processor 6 of the CHP 1. In the normal case, the processor 6 starts receiving commands by the signal on the activation line 3, and upon receiving the signal on the command transfer line 5, returns a confirmation signal pulse to the CPU 2 as a confirmation signal via the response line 4.
This enables the CPU 1 to transfer the next command data.

This interface has a monitoring circuit 7,
The sequence of the above command transfer signals is monitored. A starting line 3 is connected to the set side terminal 9 of the latch 8 of the monitoring circuit 7, and a response line 4 is connected to the reset side terminal 10, and the signal of the starting line 3 is connected as shown in part a of the time chart in FIG. It is set at the falling edge of the pulse, and reset at the falling edge of the signal pulse on the response line 4.

The monitoring circuit 7 has an AND gate 11 whose output signal line 12 becomes an input to the interrupt circuit of the processor 6. The input of AND gate 11 is latch 8
The set output 13 and start signal line 3 of the Therefore, as shown in FIG. 2b, if the CPU 2 sends the activation signal 21 again while the latch's set output signal 20 is present, an interrupt signal as shown at 22 is generated on the output signal line 12 of the AND gate 11. , an interrupt occurs to the processor 6.

The interrupt function described above has conventionally been provided for the purpose of detecting a state in which an activation signal is repeatedly issued to the activation line 3 due to an abnormality in the CPU 2 or the like.

In the present invention, after the CPU2 transfers the command, the CHP1
The time from when the confirmation signal is received on the response line 4 is monitored as shown in the processing flow of FIG.
That is, in processing block 30 for starting the command transfer process, a timer is set to a predetermined time. This timer may be an interval timer, etc. that is commonly used in processing equipment, and the time length to be set is an appropriate time length that is not shorter than the time it takes to receive the confirmation signal from CHP1 when the system is normal. I'll keep it.

Processing block 31 sends the activation signal and command data to the interface as described above. Thereafter, a loop including block 32 waits for a confirmation signal from CHP1. If a confirmation signal is obtained, the process exits the loop and proceeds to block 33, resets the timer, and then proceeds to block 34 for normal processing.

In block 35 of the confirmation signal waiting loop, the timer is checked, and if the set time has been reached, the loop is exited and block 36 is proceeded to. at this point
Since CPU2 has not received the confirmation signal from CHP1, it will not send a new command if it follows the normal sequence. However, if no signal is returned to response line 4 after the time set in the timer has elapsed, CHP1
assumes that there is some kind of abnormality in the CHP1, and forcibly sends an illegal command to generate an interrupt to CHP1.

That is, in block 36, when the CPU 2 transmits a command indicating that it is a forced illegal command transmission in the same manner as in the case of the normal command, the monitoring circuit 7
According to the above-mentioned functions of Fig. 2 time chart b
In this state, the output signal line 12 of the monitoring circuit 7 becomes 22.
The processor 6 of the CHP 1 is activated as follows, and an interrupt is generated in the processor 6 of the CHP 1. After block 36, the CPU 2 proceeds to block 37 and performs any abnormality processing within its own device, such as cleaning up the command that is currently being sent.

In the processor 6, even if an abnormal loop occurs, the execution of the loop is interrupted and a predetermined interrupt processing program is activated when the above-mentioned interrupt occurs, similar to a known interrupt function. This interrupt processing program performs a process of storing at least status data of an abnormal state, similar to known abnormality processing.

In this case, the program can know that the interrupt has been forcibly generated by the CPU 2 by analyzing the command data sent from the CPU 2 via the command transfer line 5. Therefore, it is possible to easily distinguish this from a true interface abnormality that is detected independently by the interface monitoring circuit 7, and to take appropriate measures.

(g) Effects of the invention As is clear from the above explanation, according to the present invention, it is possible to monitor and release abnormal program loops, etc.
Since this is possible without the need to provide a special mechanism, there is a significant industrial effect by improving the reliability of the system without sacrificing economic efficiency.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart of the interface monitoring circuit, and FIG. 3 is a flowchart of the processing of the CPU. In the figure, 1 is a channel processing device (CHP);
2 is the central processing unit (CPU), 3 to 5 are various signal lines of the interface, 6 is the CHP processor, 7
is the interface monitoring circuit, 8 is the latch, 12
denotes an output signal line of the monitoring circuit, and 30 to 37 denote processing blocks.

Claims (1)

[Claims] 1. A start signal is transferred from a second device to a first device that executes a program, and the first device that receives the start signal
In a system for transmitting a confirmation signal from a device to a second device, the alternation between the transferred activation signal and the confirmation signal is monitored, and when an error condition in which the activation signal occurs consecutively is detected, a first The device is provided with a monitoring means that generates an interrupt, and when the second device detects that the confirmation signal is not received within a predetermined time after sending the activation signal, the second device generates the activation signal again and generates a pseudo signal. A program control method, characterized in that it is configured to generate an error state and cause the monitoring means to detect it.