JPS61226845A - Watch dog timer - Google Patents

Abstract

PURPOSE:To monitor and detect a stall with one watch dog timer for all action levels by adding a resetting signal selecting circuit in the watch dog timer used for the information processing system. CONSTITUTION:In accordance with the action level in respective steps of a logical device 4, plural resetting signals 6-8 are inputted to a resetting signal selecting circuit 2, and the resetting signals 6-8 are alternatively selected by a selecting control signal 5. Consequently, the stall can be monitored and detected by one watch dog timer only ranging over all action levels of the logical device 4. When the stall is detected, by investigating the condition of the resetting signal selecting control signal, it can be known by which action level the stall occurs.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to failure detection in information processing systems, and more particularly to a watchdog timer for constantly monitoring a stalled state of a logical device and detecting it early.

Conventional technology The conventional watchdog timer is a software (
For example, a timer circuit monitors a reset signal generated by an operating system (O8) at regular intervals, and if a reset signal does not arrive after a preset time has elapsed, it is determined that a stall has occurred.

However, with conventional watchdog timers, there is only one reset signal that can be monitored, so for example, if this is a signal that can be generated by no-aware software, it can be used until the software is ready to operate (for example, during hardware initialization or O8 ), the monitoring function must be stopped, and even if a stall occurs during that time, it cannot be detected.

Furthermore, if the reset signal is a signal generated by hardware, there is a drawback that a stall in firmware or software running on the hardware cannot be detected.

Furthermore al! As shown in Figure 2, in order to realize the monitoring function for each of the three states: a state in which only the hardware is operational, a state in which the firmware is operational but the software is not yet operational, and a state in which the software is operational.
There was a drawback that multiple watchdog timers and an OR circuit for summarizing the results were required. ◎ Problems that the invention aims to solve The purpose of the present invention is to solve the above drawback, that is, there is only one reset signal This watch solves the problem that monitoring cannot be performed until it becomes operational, and that multiple watchdog timers are required to monitor multiple operating states of hardware, firmware, software, etc. The purpose is to provide a dog timer.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention generates reset signals of different operation levels from the logic device at each stage of hardware, firmware, and software, and also generates reset signals from the logic device at the respective stages of hardware, firmware, and software. A timer reset signal is obtained by generating a signal for selectively controlling each of the reset signals, inputting the above-mentioned signals to a reset signal selection circuit, and having the selection circuit selectively select each of the above-mentioned reset signals. is input to a timer circuit, and the timer circuit outputs the stall detection signals of each stage.

Operation Since the present invention is configured as described above, a plurality of reset signals corresponding to different operation levels at each stage of the logic device are input to the reset signal selection circuit, and this selection circuit receives selection control signals from the logic device. alternatively before yIJ
Since the set signal is selected, stalls at each stage at each operating level of the logic device can be monitored and detected.

Example Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, which shows a block diagram of an embodiment of the present invention, a watchdog timer 1 of the present invention is shown.

The reset signal selection circuit 2 and the timer circuit 3,
Reset signals 6, 7.8 and a reset signal selection control signal 5 are input from the logic device 4 to the selection circuit 2. When the logic device 4 is powered on, as shown in FIG.
First, the hardware starts operating, and after the initial settings of the hardware are completed, the firmware that runs on that hardware is loaded and started. After that, when the firmware functions and completes a predetermined process, it starts loading the software (usually O8), and transfers control to the software when it completes normally. The IR operation level is multiplexed at the hardware level, firmware level, and software level.

Reset signals 6, 7, and 8 correspond to each operation level, and are signals that are repeatedly generated at regular intervals to indicate that the operation at each level is being executed normally, and that are not generated when a stall condition occurs. It is.

The generation and stop of the reset signal 6 is controlled by hardware, the reset signal 7 is controlled by firmware, and the reset signal 8 is controlled by software, and the operating levels are in this order from lower to upper.

The reset signal selection control signal 5 is a signal that instructs which of the three reset signals 6, 7.8 is to be used as the timer reset signal 9 depending on the operating level of the logic device 4.

The reset signal selection circuit '2a selects one effective highest reset signal from the three reset signals according to the instruction of the IJ set signal selection control signal 5, and outputs it as the timer reset signal 9. .

The timer circuit 3 monitors the time interval at which the timer reset signal 90 is generated, and generates a stall detection signal 10 if the timer reset signal 9 is not generated for a predetermined period of time or more.

While the logic device 4 is operating at the hardware level, that is, before the firmware operates, the reset signal 6 passes through the reset signal selection circuit 2 and becomes the timer reset signal 9 according to the instructions of the reset signal selection control signal 5. It is subject to time monitoring in circuit 3. This is between time t. and time t1 in FIG.

When the logic device 4 is operating at the firmware level, that is, when the hardware is in an operating state but the software is not yet operating, the reset signal 7 is subject to time monitoring by the timer circuit 3, and the reset signal 8 is monitored at the software level. The time will be monitored. These are time t1 and time 1 in FIG. 2, respectively. and time t2
Hereafter.

Effects of the Invention As explained above, according to the present invention, by adding a reset signal selection circuit to a conventional watchdog timer, a single watchdog timer can be used for all operating levels of a logic device. This has the effect of monitoring and detecting stalls. Also, when a stall is detected,
By examining the state of the reset signal selection control signal,
This has the advantage that it is possible to know at what operating level the stall has occurred.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a diagram showing the timing of each operation level of a logic device. 1... Watchdog timer of the present invention, 2...
. . . Reset signal selection circuit, 3 . . . Timer circuit, 4 . . . Logic device to be monitored, 5.
...Reset signal selection control signal, 6...
Reset signal controlled by hardware, 7...
... Reset signal controlled by firmware, 8.
...Reset signal controlled by software,
9...Timer reset signal, 10...
Stall detection signal. 1st

Claims (1)

[Claims] In a watchdog timer in which a timer circuit monitors a reset signal generated at regular intervals in order to detect a stall state of a logic device, the timer circuit monitors a reset signal that is generated at regular intervals in order to detect a stall state of a logic device. a reset signal selection circuit that receives a reset signal sent from the logic device, selectively selects each of the reset signals according to a reset signal selection control signal also sent from the logic device, and inputs the selected reset signal to the timer circuit; A watchdog timer characterized by being provided with.