JPH01321728A - Control method for analog/digital converter - Google Patents
Control method for analog/digital converterInfo
- Publication number
- JPH01321728A JPH01321728A JP15521688A JP15521688A JPH01321728A JP H01321728 A JPH01321728 A JP H01321728A JP 15521688 A JP15521688 A JP 15521688A JP 15521688 A JP15521688 A JP 15521688A JP H01321728 A JPH01321728 A JP H01321728A
- Authority
- JP
- Japan
- Prior art keywords
- analog
- capacitor
- turned
- voltage
- input voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 11
- 239000003990 capacitor Substances 0.000 claims abstract description 28
- 239000004065 semiconductor Substances 0.000 abstract description 34
- 238000006243 chemical reaction Methods 0.000 abstract description 19
- 238000005070 sampling Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はアナログ/デジタル変換器の制御方法に関し、
特に半導体基板上に構成され半導体集積回路に内蔵され
るチョッパ比較器を用いたR−2R抵抗ラダー方式のア
ナログ/デジタル変換器を提案するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for controlling an analog/digital converter;
In particular, we propose an R-2R resistance ladder analog/digital converter using a chopper comparator constructed on a semiconductor substrate and built into a semiconductor integrated circuit.
第2図は例えばチョッパ型比較器を用いたアナログ/デ
ジタル変換器(以下^/D変換器という)として既に知
られているR−2R抵抗ラダー方式の^/D変換器の回
路図である。抵抗アレー9の各端部にには、例えば基準
電圧%Vの正側基準電源入力端子10及び基準電圧OV
の負側基準電源入力端子11が各接続されている。スイ
ッチ群7には抵抗アレー9における抵抗を相互に接続し
ている各接続点の電圧及び4ビツトの逐次近似レジスタ
8の値が人力されている。スイッチ群7の出力たる参照
電圧V IIEFを第1の半導体スイッチ1を介してキ
ャパシタ5の一端に与えており、また電圧入力端子6の
入力端子VINを第2の半導体スイッチ2を介して;1
−ヤパシタ5の一端に与えている。キャパシタ5の他端
はインバータ4の入力端と接続されており、インバータ
4には第3の半導体スイッチ3を並列接続し7ている。FIG. 2 is a circuit diagram of an R-2R resistance ladder type ^/D converter, which is already known as an analog/digital converter (hereinafter referred to as ^/D converter) using, for example, a chopper type comparator. At each end of the resistor array 9, for example, a positive reference power input terminal 10 of a reference voltage %V and a reference voltage OV are connected.
The negative side reference power input terminals 11 of each are connected to each other. The voltage at each connection point connecting the resistors in the resistor array 9 and the value of a 4-bit successive approximation register 8 are manually input to the switch group 7. The reference voltage V IIEF, which is the output of the switch group 7, is applied to one end of the capacitor 5 through the first semiconductor switch 1, and the input terminal VIN of the voltage input terminal 6 is applied through the second semiconductor switch 2;
-It is given to one end of Yapasita 5. The other end of the capacitor 5 is connected to the input end of an inverter 4, and a third semiconductor switch 3 is connected in parallel to the inverter 4.
キャパシタ5により、半導体スイッチl、2.3を後述
するタイミングでオン、オフさせることにより電圧入力
端子6の入力電圧V 1 Hとスイッチ群7の参照電圧
V REFとの差を得る。インパーク4の出力は制御回
路12に与えられている。制御回路12はインバータ4
の出力及び制御回路12の内部タイミングにより、逐次
近似レジスタ8及び半導体スイッチ1,2.3を制御す
る。なお、前記第1.第2.第3の半導体スイッチ1,
2,3、キャパシタ5及び・インバータ4によりチョッ
パ比較器を構成している。The difference between the input voltage V 1 H of the voltage input terminal 6 and the reference voltage V REF of the switch group 7 is obtained by using the capacitor 5 to turn on and off the semiconductor switches 1 and 2.3 at timings to be described later. The output of the impark 4 is given to the control circuit 12. The control circuit 12 is the inverter 4
The successive approximation register 8 and the semiconductor switches 1, 2.3 are controlled by the output of and the internal timing of the control circuit 12. In addition, the above-mentioned No. 1. Second. third semiconductor switch 1,
2, 3, capacitor 5, and inverter 4 constitute a chopper comparator.
逐次近似レジスタ8の出力8−0.8−1.8−2.8
−3はビットO,ビット1.ビット2.ビット3であり
、以下、出力状態を4ビツトまとめて16進数016〜
F+6で表している。Output of successive approximation register 8 8-0.8-1.8-2.8
-3 is bit O, bit 1. Bit 2. This is bit 3, and below, the output status is summarized as 4 bits in hexadecimal numbers 016~
It is expressed as F+6.
次にこのA/D変換器の動作を第2図及び第3図により
説明する。第3図はアナログ/デジタル変tM <以下
^/D変換という)を行う場合のタイミングチャートで
あって横軸が時間となっている。Next, the operation of this A/D converter will be explained with reference to FIGS. 2 and 3. FIG. 3 is a timing chart when analog/digital conversion tM <hereinafter referred to as ^/D conversion) is performed, and the horizontal axis is time.
先ず半導体スイッチ3をオンし、インバータ4の入力端
と出力側とを同電位にする。この電位V。First, the semiconductor switch 3 is turned on, and the input terminal and output side of the inverter 4 are brought to the same potential. This potential V.
はインバータ4の入出力特性により定まる。次に半導体
スイッチ2をオンし、キャパシタ5を電圧入力端子6の
入力電圧VINと前記電位■。との電位差を与えて充電
する。is determined by the input/output characteristics of the inverter 4. Next, the semiconductor switch 2 is turned on, and the capacitor 5 is connected to the input voltage VIN of the voltage input terminal 6 and the potential (2). Charge the battery by applying a potential difference between the battery and the battery.
その後、半導体スイッチ2をオフし、更に半導体スイッ
チ3をオフした後に半導体スイッチ1をオンさせ、キャ
パシタ5にスイッチ群7が出力する参照電圧V B E
yを与える。このとき、逐次近似レジスタ8の値はr
816Jとなっており、スイッチ群7の参照電圧V R
EFは抵抗アレー7の%Vの電圧が選択されて出力され
ている。このときインバータ4の入力電圧VINがV
l、l> ’A VREF (7)場合はインバータ4
の入力側の電位は電位■。より低く、それ故その出力は
rlJになり、一方VINく’A VREFの場合は電
位■。より高くその出力は「0」になる。いま、V I
N> ’A VREF T:あったため、次に逐次近似
レジスタ8の値をrc、、Jにし、スイッチ群7が3/
4 V REFを選択するようにする。Thereafter, the semiconductor switch 2 is turned off, and then the semiconductor switch 3 is turned off, and then the semiconductor switch 1 is turned on, and the reference voltage V B E outputted by the switch group 7 to the capacitor 5 is
Give y. At this time, the value of the successive approximation register 8 is r
816J, and the reference voltage V R of switch group 7
For EF, a voltage of %V of the resistor array 7 is selected and output. At this time, the input voltage VIN of the inverter 4 is V
If l, l>'A VREF (7), inverter 4
The potential on the input side of is the potential ■. lower, so its output will be at rlJ, while VIN is at potential ■ if VREF. Higher the output will be "0". Now, VI
N>'A VREF T: Next, set the value of successive approximation register 8 to rc,,J, and set switch group 7 to 3/
4 Make sure to select V REF.
更に再度半導体スイッチ3,2をオンさせ、キャパシタ
5を再充電した後、半導体スイッチ1をオンさせて、電
圧入力端子6の入力電圧■、とスイッチ群7の参照電圧
3/4 V REFとを比較する。このような動作を4
回繰返して4ビットのA/D変換動作を終了し、4ビツ
トの逐次近似レジスタにA/D変換値が設定される。Furthermore, after turning on the semiconductor switches 3 and 2 again and recharging the capacitor 5, turning on the semiconductor switch 1, the input voltage at the voltage input terminal 6 and the reference voltage 3/4 V REF at the switch group 7 are set. compare. This kind of action is 4
The 4-bit A/D conversion operation is repeated several times, and the A/D conversion value is set in the 4-bit successive approximation register.
そして、このように半導体スイッチ2.3をオンさせる
ことにより、漏洩電流によるキャパシタ5の放電を防い
でいる。By turning on the semiconductor switch 2.3 in this manner, discharge of the capacitor 5 due to leakage current is prevented.
前述したR−2+1抵抗ラダー方式のA/rl変換器の
制御方法は、スイッチ群が出力する参照電圧を変更する
都度キャパシタを再充電するため、瞬時的に変動する入
力電圧をA/D変換するためには、その入力電圧をサン
プリングするサンプルホールド回路を入力電圧端子6の
前段に設ける必要がある。The control method of the R-2+1 resistor ladder type A/rl converter described above performs A/D conversion of the input voltage that changes instantaneously in order to recharge the capacitor each time the reference voltage output by the switch group is changed. In order to do this, it is necessary to provide a sample and hold circuit for sampling the input voltage at a stage preceding the input voltage terminal 6.
また再充電のために半導体スイッチがオン、オフする動
作時間を必要として、A/D変換動作が遅いという問題
がある。Further, there is a problem that the A/D conversion operation is slow because the semiconductor switch requires operation time for turning on and off for recharging.
本発明は前述した問題に鑑み、サンプルホールド回路を
用いず、瞬時的に変動する入力電圧を迅速にA/D変換
できるA/D変換器の制御方法を提供することを目的と
する。SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a method for controlling an A/D converter that can quickly A/D convert an input voltage that fluctuates instantaneously without using a sample-and-hold circuit.
本発明に係るアナログ/デジタル変換器の制御方法は、
キャパシタの充電をA/D変換を行う期間に一度行う。The method for controlling an analog/digital converter according to the present invention includes:
The capacitor is charged once during the A/D conversion period.
第2.第3のスイッチがともにオンし、第1のスイッチ
がオフして、キャパシタはアナログからデジタルに変換
すべき入力電圧により充電される。Second. The third switch is turned on together, the first switch is turned off, and the capacitor is charged with the input voltage to be converted from analog to digital.
第2のスイッチをオフに保持し、第3のスイソチがオフ
して第1のスイッチがオンすると、参照電圧がキャパシ
タに与えられる。入力電圧と参照電圧との差に関連して
参照電圧が順次変更される。When the second switch is held off and the third switch is turned off and the first switch is turned on, a reference voltage is applied to the capacitor. The reference voltage is sequentially changed in relation to the difference between the input voltage and the reference voltage.
これにより、アナログ/デジタル変換器の出力電圧がキ
ャパシタ充電時の入力電圧になる。As a result, the output voltage of the analog/digital converter becomes the input voltage when charging the capacitor.
以下本発明をその実施例を示す図面によって詳述する。 The present invention will be described in detail below with reference to drawings showing embodiments thereof.
第1図は本発明に係るアナログ/デジタル変換器の制御
方法によるその動作のタイミングチャートであり、A/
D変換器には第2図に示したA/D変換器を用いる。FIG. 1 is a timing chart of the operation of an analog/digital converter according to the method of controlling the analog/digital converter according to the present invention.
The A/D converter shown in FIG. 2 is used as the D converter.
さ°ζ、A/D変換動作を開始するに当たり、先ず半導
体スイッチ3に続いて半導体スイッチ2がオンする。こ
のとき、従来のA/D変換器と同様にインバータ4の人
、出力電圧は、インバータ4の人。To start the A/D conversion operation, first the semiconductor switch 3 is turned on, followed by the semiconductor switch 2. At this time, as with conventional A/D converters, the output voltage is the same as that of inverter 4.
出力特性で定まる電位■。になり、キャパシタ5は電圧
入力端子6の入力端子VINと電位v0との電位差によ
って充電される。その後半導体スイッチ2のオフに続い
て半導体スイッチ3がオフし、半導体スイッチ1がオン
する。そしてチョッパ比較器をこのような状態に保ち、
先ず逐次比較レジスタ8の出力を816にセットし、ス
イッチ群7の参照電圧% VREFを選択して、入力電
圧v1と参照電圧% VREFとの差を得る。Potential determined by output characteristics■. The capacitor 5 is charged by the potential difference between the input terminal VIN of the voltage input terminal 6 and the potential v0. After that, semiconductor switch 2 is turned off, semiconductor switch 3 is turned off, and semiconductor switch 1 is turned on. And keep the chopper comparator in this state,
First, the output of the successive approximation register 8 is set to 816, the reference voltage % VREF of the switch group 7 is selected, and the difference between the input voltage v1 and the reference voltage % VREF is obtained.
このとき、vlN>〃vREFであるからインバータ4
の出力は「0」となる。そして次に同様に3/4V R
EFとの差を得る。このときも半導体スイッチ1.2.
3はともにオン、オフ動作をさせていないからキャパシ
タ5は最初に充電した入力電圧VINに保持されている
ので、半導体スイッチ2がオフする直前の入力電圧VI
Nとの差を得ることになる。At this time, since vlN>〃vREF, inverter 4
The output of is "0". And then similarly 3/4V R
Get the difference with EF. At this time as well, semiconductor switches 1.2.
Since capacitor 5 is held at the initially charged input voltage VIN since neither of the capacitors 3 and 3 are turned on or off, the input voltage VI immediately before the semiconductor switch 2 is turned off is maintained at the input voltage VIN that was initially charged.
You will get the difference from N.
以降、スイッチ群7の参照電圧5/8 VIEFとの比
較、11/16 V REFとの比較もすべて半導体ス
イッチ2がオフする直前の入力電圧VINに対して行わ
れ、最後に半導体スイッチ2がオフする直前の入力電圧
VINのA/D変換値が逐次近似レジスタ8から得られ
る。”こ6ように^/D変換している期間、従来のよう
に半導体スイッチ1,2.3を切換えないからA/D変
換動作が極めて速くなる。From then on, the comparison with the reference voltage 5/8 VIEF of the switch group 7 and the comparison with 11/16 V REF are all performed with respect to the input voltage VIN immediately before the semiconductor switch 2 is turned off, and finally when the semiconductor switch 2 is turned off. The A/D conversion value of the input voltage VIN just before the input voltage VIN is obtained from the successive approximation register 8. ``During this period of ^/D conversion, the semiconductor switches 1, 2, and 3 are not switched as in the conventional case, so the A/D conversion operation becomes extremely fast.
以上詳述したように本発明は、入力電圧を与える第2の
半導体スイッチをA/D変換動作の開始時にオンさせて
、アナログをデジタルに変換すべき入力電圧でキャパシ
タを充電した後にオフさせてその状態を保ち、その後は
逐次近似レジスタの値で選択されたスイッチ群からの参
照電圧と、キャパシタの充電電圧との差を得て参照電圧
を逐次変更し、A/D変換器の出力電圧をキャパシタ充
電時の入力電圧になすから、迅速に^/D変換が行え、
変動する入力電圧に対応でき、サンプルボールド回路を
要しないA/D変換器を提供できる優れた効果を奏する
。As described in detail above, the present invention turns on the second semiconductor switch that supplies the input voltage at the start of the A/D conversion operation, charges the capacitor with the input voltage to be converted from analog to digital, and then turns it off. This state is maintained, and after that, the difference between the reference voltage from the switch group selected by the value of the successive approximation register and the charging voltage of the capacitor is obtained, and the reference voltage is successively changed to change the output voltage of the A/D converter. Since it is used as the input voltage when charging the capacitor, ^/D conversion can be performed quickly.
This provides an excellent effect of providing an A/D converter that can respond to varying input voltages and does not require a sample bold circuit.
第1図は本発明に係るアナログ/デジタル変換器の制御
方法によるアナログ/デジタル変換動作のタイミングチ
ャート、第2図はR−2R抵抗ラダー方式のアナログ/
デジタル変換器の回路図、第3図は従来の制御方法によ
るアナログ/デジタル変換動作のタイミングチャートで
ある。
1.2.3・・・半導体スイッチ 4・・・インバータ
5・・・キャパシタ 6・・・電圧入力端子 7・・・
スイッチ群 8・・・逐次近似レジスタ 9・・・抵抗
アレー12・・・制御回路
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a timing chart of an analog/digital conversion operation according to the analog/digital converter control method according to the present invention, and FIG. 2 is a timing chart of an analog/digital conversion operation using an R-2R resistance ladder method.
The circuit diagram of the digital converter, FIG. 3, is a timing chart of analog/digital conversion operation using a conventional control method. 1.2.3...Semiconductor switch 4...Inverter 5...Capacitor 6...Voltage input terminal 7...
Switch group 8...Successive approximation register 9...Resistor array 12...Control circuit In the drawings, the same reference numerals indicate the same or equivalent parts.
Claims (1)
タに変換するデジタル/アナログ変換部の出力と、アナ
ログをデジタルに変換すべき入力電圧とを第1,第2の
スイッチを夫々介してキャパシタに与え、第3のスイッ
チによりキャパシタの充電を可能にしており、キャパシ
タの充電電圧に関連して前記制御回路のデジタルデータ
を決定するR−2R抵抗ラダー方式のアナログ/デジタ
ル変換器の制御方法において、 前記第2,第3のスイッチをともにオンさ せ、第1のスイッチをオフさせて前記キャパシタを前記
入力電圧で充電し、充電後に第2,第3のスイッチをと
もにオフさせ、第1のスイッチをオンさせてその状態を
保ち、前記デジタル/アナログ変換部の参照電圧を順次
変化させてアナログ/デジタル変換器の出力電圧を、前
記キャパシタ充電時の入力電圧になすことを特徴とする
アナログ/デジタル変換器の制御方法。1. The output of the digital/analog converter that converts digital data output by the control circuit into analog data and the input voltage to be converted from analog to digital are applied to the capacitor via the first and second switches, respectively, and the third In the method for controlling an analog/digital converter of an R-2R resistance ladder type, the second switch enables charging of a capacitor, and determines digital data of the control circuit in relation to the charging voltage of the capacitor. Both the third switch is turned on, the first switch is turned off to charge the capacitor with the input voltage, and after charging, both the second and third switches are turned off, and the first switch is turned on to charge the capacitor with the input voltage. A method for controlling an analog/digital converter, characterized in that the output voltage of the analog/digital converter is made equal to the input voltage at the time of charging the capacitor by sequentially changing the reference voltage of the digital/analog converter. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63155216A JP2623298B2 (en) | 1988-06-23 | 1988-06-23 | Control method of analog / digital converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63155216A JP2623298B2 (en) | 1988-06-23 | 1988-06-23 | Control method of analog / digital converter |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01321728A true JPH01321728A (en) | 1989-12-27 |
JP2623298B2 JP2623298B2 (en) | 1997-06-25 |
Family
ID=15601055
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63155216A Expired - Fee Related JP2623298B2 (en) | 1988-06-23 | 1988-06-23 | Control method of analog / digital converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2623298B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2760153A1 (en) * | 1997-02-24 | 1998-08-28 | Mitsubishi Electric Eng | METHOD FOR CONTROLLING AN ANALOGUE-DIGITAL CONVERTER |
US6288668B1 (en) | 1995-02-22 | 2001-09-11 | Fujitsu Limited | Analog to digital converter, encoder, and recorded data reproducing apparatus |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5561136A (en) * | 1978-10-31 | 1980-05-08 | Fujitsu Ltd | Analog-digital converter |
JPS62298230A (en) * | 1986-06-17 | 1987-12-25 | Nec Corp | Analog-digital converter |
-
1988
- 1988-06-23 JP JP63155216A patent/JP2623298B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5561136A (en) * | 1978-10-31 | 1980-05-08 | Fujitsu Ltd | Analog-digital converter |
JPS62298230A (en) * | 1986-06-17 | 1987-12-25 | Nec Corp | Analog-digital converter |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6288668B1 (en) | 1995-02-22 | 2001-09-11 | Fujitsu Limited | Analog to digital converter, encoder, and recorded data reproducing apparatus |
US6288665B1 (en) | 1995-02-22 | 2001-09-11 | Fujitsu Limited | Analog to digital converter, encoder, and recorded data reproducing apparatus |
FR2760153A1 (en) * | 1997-02-24 | 1998-08-28 | Mitsubishi Electric Eng | METHOD FOR CONTROLLING AN ANALOGUE-DIGITAL CONVERTER |
US5877719A (en) * | 1997-02-24 | 1999-03-02 | Mitsubishi Electric Engineering Co., Ltd. | Method of controlling analog-to-digital converter |
DE19738561C2 (en) * | 1997-02-24 | 2002-06-27 | Mitsubishi Electric Eng | Method for controlling analog-digital converters |
Also Published As
Publication number | Publication date |
---|---|
JP2623298B2 (en) | 1997-06-25 |
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