JPH01320558A - Microprogram controller - Google Patents

Abstract

PURPOSE:To accelerate processing speed by suppressing the write of a microinstruction in which the detection of error correction where second one-bit error information coincides with first one-bit error information held previously is performed when the second one-bit error information is detected to a control storage. CONSTITUTION:When a one-bit error is detected by the error detection of the microinstruction at an EDAC circuit 4, microprogram control is suppressed by a one-bit error detecting signal line (b), and one-bit error correction is performed. The microinstruction on which the error correction is applied is stored in a data register 3, and also, is sent to a control storage 1, and furthermore, it is stored in a data register 5, and is set on a flag register 6. Hereinafter, when the one-bit error is detected at the EDAC circuit 4, it is compared with the one-bit error information stored in the register 5 by a comparator 7, and when coincidence is obtained, a control storage part 9 suppresses the rewrite of correction data from the EDAC circuit 4 on the control storage 1. Thus, the processing speed can be accelerated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram control device, and more particularly to a method for writing 1-bit error correction data into a control memory of a microprogram control device.

Conventionally, this type of microprogram control device has a control memory 1 in which microinstructions are stored, a selector 2, a data register 3, and 1-bit error correction, 2-bit error detection, as shown in FIG. Functional circuit [hereinafter referred to as EDA
C (Error Detection Andcor)
4 and a control storage controller 10.

Regarding the EDAC circuit 4's 1-bit error correction 2-bit error detection function (EDACI! Noh), "Error Detection and Correction System" (Special Publication No. 53-20367) and "Coding Theory" (Takashio, Nobuki Tokura) , co-authored by Yoshihiro Iwadare and Yasuyoshi Inagaki, published by Corona Publishing, 1975).

The microinstruction read from control memory 1 is sent to selector 2.
is stored in the data register 3 via the EDAC circuit 4.
An error check is performed.

When a 1-bit error is detected in the microinstruction by the error check of the EDAC circuit 4, the microinstruction is corrected by the EDAC circuit 4, and the corrected microinstruction is stored in the data register 3 and is stored regardless of the history. Written to control memory 1. While this writing to the control memory 1 is being performed, the EDAC circuit 4 sends 1 bit,
A 1-bit error detection signal is output, and microprogram control is inhibited by this 1-bit error detection signal.

When the EDAC circuit 4 completes writing the modified microinstruction into the control memory 1, the inhibition of microprogram control is released and microprogram control is restarted.

In such a conventional microprogram control device, when a 1-bit error is detected in a microinstruction read from the control memory 1, the microinstruction corrected by the EDAC circuit 4 is always written to the control memory 1. Even when it is unnecessary to write the corrected microinstruction to the control storage 1, such as when a fixed error occurs, the corrected microinstruction is still written to the control storage 1.

Further, the control memory 1 is composed of a RAM (random access memory), and writing to the control memory 1 generally takes longer than the data register 3 composed of a flip-flop. For example, writing to control memory 1 takes 63 steps more than writing to data register 3. Therefore, when the above-mentioned fixed error occurs, there is a disadvantage that unnecessary writing to the control memory 1 inhibits microprogram control until the writing is completed.

The present invention has been made to eliminate the drawbacks of the conventional ones as described above, and provides a microprogram control that can shorten the inhibition time of microprogram control and improve processing speed. The purpose is to provide equipment.

A microprogram control device according to the present invention is a microprogram control device including an error correction detection means for correcting and detecting an error in a microinstruction read from a control memory, wherein the error correction detection means detects an error. holding means for holding the first 1-bit error information;
After the microinstruction for which the error correction detection was performed by the error correction detection means when the first 1-bit error information was detected is written into the control memory, the error correction detection means detecting means for detecting a match between the second one-bit error information detected by the first one-bit error information held in the holding means; When a match between the second 1-bit error information and the second 1-bit error information is detected, the microinstruction of the micro-instruction whose error was corrected and detected by the error correction detection means when the second 1-bit error information was detected is detected. It is characterized by comprising a suppressing means for suppressing writing to the control memory.

Next, an example of the square noodles of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 6, a microprogram control device according to an embodiment of the present invention includes a control memory 1, a selector 2, a data register 3. , an EDAC circuit 4, a flag register 6, a comparator 7, an AND circuit 8, and a control storage controller 9.

Microinstructions are stored in control memory 1, and the microinstructions read from control memory 1 are stored in data register 3 via selector 2.

The controller 1/controller 2 selects one of the microinstruction read from the control memory 1 and the 1-bit error correction data from the EDAC circuit 4 and sends it to the data register 3.

The microinstruction stored in data register 3 is EDAC
The signal is sent to the circuit 4 as well as to a controlled section (not shown) via the control signal line a.

The EDAC circuit 4 performs 1-bit error correction and 2-bit error detection on the microinstruction sent from the data register 3, and sends the microinstruction with 1-bit error correction to the control memory 1 and the selector 2.

Further, the EDAC circuit 4 sends the 1-bit error information at this time, such as the syndrome at the time of 1-bit error correction and information about which bit the error has occurred, to the data register 5 and the comparator 7.

Furthermore, the EDAC circuit 4 has a 1-bit factory detection signal line l.
A 1-bit error detection signal is outputted to the data register 5 and flag register 6 via 1-1, and the 1-bit error detection signal is also sent to the controlled section to inhibit microprogram control.

The data register 5 stores 1-bit error information when the EDAC circuit 4 corrects a 1-bit error. The 1-bit error information stored in the data register 5 is compared by the comparator 7 with the 1-bit error information when the EDAC circuit 4 next performs 1-bit error correction.

The comparator 7 outputs "1" to the AND circuit 8 when the 1-bit error information is equal, and outputs "0" to the AND circuit 8 when the 1-bit error information is unequal.

AND circuit 8 connects the output from flag register 6 and comparator 7
It performs a logical AND operation with the output from the , and outputs the result of the operation to the control storage controller 9 .

The control storage controller 9 controls writing of microinstructions that have undergone 1-bit error correction into the control storage 1 in accordance with the calculation result from the AND circuit 8 .

Next, the operation of an embodiment of the present invention will be explained with reference to FIG.

If no 1-bit error has occurred in the microinstruction read from control memory 1, flag register 6 is set to "0".

The microinstruction read from the control memory 1 is stored in the data register 3 via the selector 2, and the microinstruction is sent to the controlled unit through the control signal line a, thereby performing microprogram control. be exposed.

At the same time, the microinstruction stored in the data register 3 is sent to the EDAC circuit 4, and the EDAC circuit 4 detects an error in the microinstruction.

1 due to microinstruction error detection in EDAC circuit 4.
When a bit error is detected, a 1-bit error detection signal is output to the controlled section via the 1-bit error detection signal line, and microprogram control is inhibited.

Further, the EDAC circuit 4 performs 1-bit error correction on the microinstruction, stores the 1-bit error-corrected microinstruction in the data register 3 via the selector 2, and sends it to the control memory 1. Furthermore, the EDAC circuit 4
stores the 1-bit error information at this time in the data register 5, and sets "1" in the flag register 6.

At the timing when the flag register 6 is set to 1', the output from the flag register 6 is still "0", so the AND circuit 8 outputs "0" to the control storage controller 9 regardless of the comparison result of the comparator 7. I will do it.

Therefore, in the control memory 1, the corrected data from the EDAC circuit 4 is rewritten under the control of the control memory controller 9.

When the rewriting in the control unit +*i is completed, the suppression of microprogram control is released and microprogram control is restarted.

After this, when a 1-bit error is detected in the EDAC circuit 4, the EDAC circuit 4 outputs a 1-bit error detection signal to the controlled section using the 1-bit error detection signal ab to suppress microprogram control.

Further, the EDAC circuit 4 performs 1-bit error correction on the microinstruction, stores the 1-bit error-corrected microinstruction in the data register 3 via the selector 2, and sends it to the control memory 1. Furthermore, the ED at this time
The 1-bit error information from the AC circuit 4 is compared with the 1-bit error information stored in the data register 5 by the comparator 7.

If the comparison result of the comparator 7 does not match, "0" is output from the AND circuit 8 to the control memory controller 9, and in the control memory 1, E is output by $17911 of the control memory controller 9.
The corrected data from the DAC circuit 4 is rewritten.

At this time, the data register 5 stores 1-bit error information from the EDAC circuit 4, and the flag register 6
“1” is stored in .

When the rewriting in the control memory 1 is completed, the suppression of microprogram control is released and microprogram control is restarted.

On the other hand, if the comparison result of comparator 7 is a match, the outputs from flag register 6 and comparator 7 are both “1”.
Therefore, “1” is sent from the AND circuit 8 to the control storage controller 9.
” is output. As a result, the control memory controller 9 inhibits rewriting of the corrected data from the EDAC cycle 1i!14 in the control memory 1, and the inhibition of microprogram control is released and microprogram control is restarted. Ru.

Similarly, when a 1-bit error is detected in the EDAC circuit 4, the comparator 7 compares the 1-bit error information detected before the detection of the 1-bit error and stored in the data register 5 with the 1-bit error information. and when the comparison result shows a match, the EDAC circuit 4 transfers the data to the control memory 1.
By inhibiting the rewriting of corrected data from the memory, unnecessary writing to the control memory 1 that occurs when a fixed error occurs can be eliminated. Therefore, the time for inhibiting microprogram control can be shortened, and the processing speed can be improved.

As explained above, according to the present invention, the first 1-bit error information detected by the error correction detection means that performs error correction detection in the microinstruction read from the control memory and the first 1-bit error information After the microinstruction whose error was corrected and detected by the error correction detection means when the 1-bit error information of 1 was detected is written into the control memory, the second 1-bit error information detected by the error correction detection means is 1-bit error information, and when the comparison results match, the microinstruction is stored in the control memory of the microinstruction whose error correction was detected by the error correction detection means when the second 1-bit error information was detected. By inhibiting the writing of , the inhibition time for microprogram control can be shortened and the processing speed can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional example. Explanation of symbols of main parts 1...Control memory 3.5...Data register 4...1 and error correction 2-bit error detection function circuit 6... Flag register 7... Comparator 8... AND circuit 9... Control storage control section

Claims (1)

[Claims] (1) A microprogram control device including an error correction detection means for correcting and detecting an error in a microinstruction read from a control memory, which retains first 1-bit error information detected by the error correction detection means. after the micro-instruction whose error has been corrected and detected by the error correction detection means when the first 1-bit error information is detected is written into the control memory; detection means for detecting a match between the second 1-bit error information detected by the error correction detection means and the first 1-bit error information held in the holding means; When a match between the 1-bit error information and the second 1-bit error information is detected, the error correction detection means performs the error correction detection when the second 1-bit error information is detected. 1. A microprogram control device, comprising: inhibiting means for inhibiting writing of the microinstruction to the control memory.