JPH01319957A - Integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the deformation of a lead, and to realize the increase of pins by fastening a lead fixing frame onto the underside of the lead near a bump on the inside of an LSI chip. CONSTITUTION:Bumps 2 are arranged on the outer circumferential section of the surface of an LSI chip 1. The device hole 4 of an insulating film 3 and a lead fixing frame 8 are punched previously, copper foil is fast stuck onto the film 3, and specified leads 5, wiring patterns 6 and electrodes 7 for a test are formed through known etching and a plating technique. The bumps 2 and the leads 5 are positioned at 1:1, and both are thermocompression-bonded by a bonding tool. The fixing frame 8 is fastened onto the undersides of the leads at a position among the bumps and chip edges. Accordingly, the deformation of the leads 5 is prevented, and the increase of pins is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to integrated circuits, and more particularly to integrated circuit devices assembled by tape automated bonding.

[Conventional technology]

Conventionally, in the production of integrated circuits, TAB (Tape Automated Bo) is used to automate assembly.
A method in which all pins are bonded simultaneously (so-called gigantic bonding) is often adopted.

FIGS. 3(a) and 3(b) are a plan view and a sectional view taken along the line B-B' for explaining the conventional TAB assembly method.

L, SI chip 1 has bumps 2 formed thereon. A device hole 4 is formed in the insulating film 3, and a lead 5 protrudes in the form of a cantilever. Insulating film 3 and LSI
The chips 1 and the leads 5 are aligned and the bumps 2 are welded together.

[Problem to be solved by the invention]

In the conventional TAB type LSI device described above, there is no lead fixing frame near the tip of the lead 5 connected to the bump 2, and the lead 5 has a cantilever structure protruding into the device hole 4. If the lead pitch is narrowed in order to connect many leads, the lead width becomes narrow and the lead strength decreases. As a result, there is a drawback that the leads are deformed (sagging and pitch irregularities) due to stress in the pre-bonding process. Furthermore, there is a drawback that edge touching occurs between the LSI chip 1 and the leads 5 in the steps after bonding, which is difficult to realize in an LSI chip that requires many leads.

An object of the present invention is to provide a GK8 circuit that can be assembled using the TAB method without deforming the leads even if there are many leads.

[Means to solve the problem]

The present invention provides an integrated circuit in which bumps protruding from the outer periphery of the surface of an integrated circuit chip are bonded to leads provided on an insulating film, in which the bumps are fixed to the bottom surface of the leads including the chip edges outside the bumps on the surface of the integrated circuit chip. Consists of a lead fixing frame.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line AA', showing a first embodiment of the present invention.

Bumps 2 are arranged on the outer periphery of the surface of the LSI chip 1. On the other hand, the device hole 4 and lead fixing frame 8 of the insulating film 3 are punched out in advance, and the insulating film 3 is
A copper foil is adhered thereon, and predetermined leads 5, wiring patterns 6, and test electrodes 7 are formed by well-known etching and plating techniques. After that, match bump 2 and lead 5 one to one.
Align the edges and heat and press the two together using a bonding tool. The lead fixing frame 8 is fixed to the lower surface of the lead at a position between the bump and the chip edge.

FIG. 2 is a plan view showing a second embodiment of the invention.

This embodiment is realized by an LSI chip 1 having bumps 2 arranged in a staggered manner. Since the lead fixing frame 8 is fixed to the lower surface of the leads including the chip edges outside the bumps of the LSI chip, it has the same advantages as the first embodiment.

〔Effect of the invention〕

As explained above, the present invention fixes the lead fixing frame to the lower surface of the leads in the vicinity of the bumps inside the LSI chip, thereby preventing lead deformation (sloping and pitch irregularities) in the work process before bonding. This can be prevented, and as a result, multiple bins can be realized. Second, edge touching between bumps and chip edges can be prevented, and a highly reliable LS'I device can be realized.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are a plan view and a sectional view taken along the line A-A' for explaining the first embodiment of the present invention, and FIG. 2 is for explaining the second embodiment of the present invention. Plan view for Figure 3 (a>
, (b) are a plan view and a sectional view taken along the line BB' for explaining the conventional TAB assembly method. DESCRIPTION OF SYMBOLS 1... LSI chip, 2... Bump, 3... Insulating film, 4... Device hole, 5... Lead,
6... Wiring pattern, 7... Test electrode, 8...
Lead fixation (b) Fig. 1 Fig. 2

Claims (1)

[Claims] Multiple TAs protruding from the outer periphery of the integrated circuit chip surface
In an integrated circuit in which a B lead connection bump and an external lead provided on an insulating film are directly bonded and connected, a lead fixing frame is fixed to a lower surface position of the lead including a chip edge outside the TAB lead connection bump of the integrated circuit chip. An integrated circuit comprising: