JPH01318264A - Self-extinction element - Google Patents

Abstract

PURPOSE:To reduce stationary loss and switching loss by combining a PIN base structure with an anode-emitter short-circuiting structure. CONSTITUTION:An N emitter 2 as a cathode element is disposed on a P base layer 3 in the form of an island, and a short-circuiting layer 71 comprising an N<++> layer is provided between a buffer layer 7 comprising an N<+> layer and an anode electrode 51 for short-circuiting between the buffer layer 7 and the anode electrode 51. The short-circuiting layer 71 extends through a center section located lognitudinally of a projected image so as to intersect the projected image perpendicularly to the same. When a junction area between the anode electrode 51 and the short-circuiting layer 71 is assumed to be A1 and an area of the anode electrode 51 to be A2, the element is designed such that A1/A2 is 20% or less. Hereby, stationary loss and switching loss are reduced and hence a self-extinction element such as GTO having good turn-off characteristics can be yielded.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a power self-extinguishing element such as a gate turn-off thyristor.

B1 Summary of the Invention The present invention provides a self-extinguishing element in which a portion corresponding to a base layer made of an N-type semiconductor is composed of, for example, an N− layer and an N′ layer, and the N° layer and an anode electrode are short-circuited by a short layer. In this case, if the Noyote layer is arranged perpendicularly to the projected image of the cathode element so as to pass through the center thereof (by suppressing the short-circuit ratio to 20% or less), turn-off loss and steady-state loss can be reduced. This is aimed at the effect of being able to reduce turn-off loss without increasing , while also having good turn-on characteristics.

C Conventional technology GTOJ (hereinafter referred to as rGTOJ).

) is increasingly demonstrating its features as a self-extinguishing element for electric power in the field of high withstand voltage and large current.

However, GTOs with high withstand voltages have large steady-state losses and switching losses, and reductions in these losses are required.

Examples of countermeasures for steady loss and switching loss are described below.

(Regarding steady loss) Figure 4 is a diagram showing the structure of a conventional GTO, where l is a gate layer made of a P layer (hereinafter referred to as "P gate layer");
II is a buried gate layer made of a P" layer, 2 is an emitter layer made of an N" layer (hereinafter referred to as "N emitter layer"),
21 is a cathode electrode, 3 is a base layer made of P layer (hereinafter referred to as "P base layer"), 4 is a base layer made of N layer (hereinafter referred to as "N base layer"), and 5 is an emitter made of P layer. layer (hereinafter referred to as "P emitter layer"), 51 is an anode electrode.

In the GTO shown in FIG. 4, the width of the N base 4 increases as the withstand voltage increases. Here, generally N base 4
There is the following relationship between the width W and the on-voltage VTM.

However, 3. τ3 is large, emitter symmetry is good,
When 10<j<100OA/cm', β-q/'r
, q: charge, charge layer Tumann constant.

1゛: absolute temperature, j: current density, b=D, /Dp.

b' = b/(b+1), DI, , Dp: diffusion coefficient of electrons and holes in the base region, τ2. τ, 2N base.

r) the lifetime of the base minority carrier, W,.

W, N base, P base width, W=W, 10W.

tN: Effective impurity amount of P emitter, A, Bo.

Co: Constant As can be seen from the above, as the width W of the N base increases, the on-state voltage increases, and as a result, the steady-state loss increases. G.T.O.
Most of the increase in steady-state loss accompanying the increase in withstand voltage is due to the increase in the width W of the N base.

To solve this problem, taking a buried gate type GTO as an example, a GTO with a PIN base structure as shown in FIG.
is proposed. In the PIN base structure, the portion corresponding to the N base of the PN base structure shown in FIG.
The width of the base layer (combined portion of base layer 6 and buffer layer 7) made of N-type semiconductor is about 2/2 of that of the PN base structure at the same withstand voltage. The advantage is that only 3 is required.

Therefore, the steady loss in the PIN structure is correspondingly small.

(Regarding switching loss) Switching loss includes turn-on loss and turn-off loss. Turn-on loss is generally closely related to the gate structure of the device and the lifetime of minority carriers.

Turn-off loss is particularly problematic as the element increases in voltage resistance.

Turn-off loss is divided into loss during falling time (fall loss) and loss during tail time (tail loss). 6th
The figure shows turn-off characteristics, and solid lines (1), chain lines (2), and dotted lines (3) indicate current, voltage, and power loss, respectively. Among these losses, the tail loss sometimes accounts for nearly 90% of the total turn-off loss. Therefore, reducing this tail loss is most effective in reducing turn-off loss.

Tail loss is due to Tilmi flow. Tirumi style is GT
In the turn-off process of O, excess carriers in the P base layer 3 are extracted from the P gate layer l, and the P base layer 3, N
When the main junction between the bases 4 is restored, excess carriers remaining in the N base layer 4 disappear. This is the current that flows due to both.

Since the N base layer 4 does not have a gate part like the P base layer 3, excess carriers are not drawn out from the gate part and the P base layer 4 does not have a gate part.
It disappears by recombining with carriers injected from the emitter layer 5. When the device is made to have a high withstand voltage, the impurity concentration of the N base layer 4 becomes lower and the width increases.
The number of excessive carriers will increase. Furthermore, in order not to significantly impair the turn-on characteristics due to the increase in the width of the N base layer 4,
The lifetime of the carrier in the N base layer 4 must be made long. Therefore, the higher the withstand voltage of the GTO is, the more the Tilmi current increases and the tail loss increases.

To solve this problem, taking a buried gate type GTO as an example, an anode-emitter short structure as shown in FIG. 7 has been proposed. This structure is a structure in which a part of the N base layer 4 is shorted to the anode electrode 51, and the excess carriers in the N base layer 4 during the tail time can be drawn out by the anode electrode. Therefore, the anode-emitter short structure has the advantage of low tail loss and, as a result, low switching loss.

D1 Problems to be Solved by the Invention Above, we have described typical structures that are effective in reducing the steady-state loss and switching loss that increase with the increase in the withstand voltage of GTOs. However, these structures include wholesalers as described below.

Although the PIN-based structure is effective in reducing steady-state loss,
It has little effect on reducing switching loss. However, as the main junction recovers, the excess carriers remaining at the end in the N base layer 4 gather in the highly concentrated buffer layer 7, and since the lifetime of the carriers in the buffer layer 7 is relatively short, the excess carriers disappear slightly. Although fast, the anode-emitter short structure does not have any great effect.

Although the partially anode-emitter short structure is effective in reducing switching loss, it is hardly effective in reducing steady-state loss. In addition, in reducing switching loss, that is, reducing tail loss, the effect of drawing out excess carriers in the N base layer 4 is limited to the part where the anode emitter is shorted and the vicinity. In some cases, the number is as high as 10%.

As a new method to solve these problems, the present inventor has already proposed a structure that combines a PIN base structure and an anode emitter short structure (Japanese Patent Application No. 62-3245
No. 2) This is a combination of a GTO with a PIN-based structure and an anode-emitter short structure, which reduces steady-state loss. are doing.

FIG. 8 is a diagram showing blocking of a new structure applied to a buried gate type GTO. Here, the N-base layer 6 has an impurity concentration of I x 10I3a toms/cm' or less, and its thickness is determined by the design value of the forward withstand voltage of the GTO. In addition, the portion & of the buffer back 7 located above the P emitter layer 5 in the figure prevents the end of the depletion layer spreading to the N-base layer 6 from reaching the P emitter layer 5 when the device is in a forward blocking state. In order to avoid significant impairing of carrier injection from the P emitter layer 5, the peak impurity concentration is set to 5x 10'5-I x 10"a toms/
cm3, and the thickness is 50 to 90 μm. Further, from the buffer layer 7 to the anode electrode 5. The part short-circuited to the anode electrode 5. The surface impurity concentration is 1×10”a toms/cm to obtain good ohmic contact with
It is 3 or more.

Examples of manufacturing methods for obtaining this new structure are described below.

Regarding part a of the buffer layer 7, Japanese Patent Application No. 58-2514
As shown in No. 72, an N-type impurity is debossed, a relatively low concentration layer is formed thereon by epitaxial growth, and then a heat treatment is performed. Furthermore, the b portion of the buffer layer 7 is formed by depositing an N-type impurity with a higher β degree than the epitaxial growth surface before the above heat treatment using the method shown in Japanese Patent Application No. 59-227575.

The device with the new structure shown in FIG. 8 has the following effects.

■Because it has a PIN-based structure, the N-base width is approximately 2/3 that of the conventional GTO structure with the same withstand voltage.
Therefore, steady loss is reduced by 30% or more.

■Compared to the conventional anode emitter short structure, which was effective in reducing tail loss, which accounts for a large proportion of switching loss, tail loss can be further reduced by several 10%. .

■This phenomenon can be explained as follows. During the tail time, the last remaining excess carriers in the N base gather in the highly concentrated N° layer (part a) as the main junction recovers. The collected excess carriers are transferred to a high concentration, low resistance N° layer (a
17 and is drawn out from the N0 layer (part b) forming the short layer to the anode electrode 51.

This effect is as if a buried gate layer was provided in the N base layer, like the buried gate layer l provided in the P base layer 3.

Therefore, while the conventional anode emitter short structure could only extract excess carriers from the shorted part of the anode emitter and the vicinity, the new structure shown in Figure 8 can quickly extract excess carriers from the entire area. can.

As described above, this new structure is an excellent method that can simultaneously reduce steady-state loss and switching loss. However, since there are three parts of the low-resistance N° layer 7, the GTO
The disadvantage was that the turn-on characteristics of the 2000W were significantly impaired.

An object of the present invention is to provide a self-extinguishing element such as a GTo which reduces steady-state loss and switching loss and also has good turn-on characteristics.

E9 Means for Solving Problems The present invention provides a P base layer made of a P type semiconductor, an N base layer made of an N type semiconductor, a buffer layer having a higher impurity concentration than the N base layer, and a P emitter made of a P type semiconductor. The layers are laminated in this order, cathode elements are arranged in an island shape on the P base layer, an anode electrode is provided on the P emitter layer, and a short circuit is formed between the buffer layer and the anode electrode. In a self-switching element that is turned off by drawing current from a gate layer provided on the P base layer, the short layer is provided with a short layer made of an N-type semiconductor to It is characterized in that it is arranged so as to pass through the center in the direction and be perpendicular or substantially perpendicular to the projected image, and the ratio of the bonding area between the anode electrode and the short layer to the anode electrode area is 20% or less.

F. Embodiment FIG. 1 is a diagram showing a part of the GTO of the present invention (one layer and two parts of a unit GTO), and the same reference numerals as in FIGS. 4 and 5 indicate the same or equivalent parts. . In this GTO, an N emitter layer 2 forming a cathode element is arranged in an island shape on a P base layer 3, and a buffer layer 7 made of an N0 layer and an anode electrode 5. A short layer 7 made of an N'' layer is provided between the N emitter layer 2 and the +. '＋ij
1° and an anode electrode 5. arranged perpendicularly to the projected image. and short layer 7. The joint area with A1,
If the area of the anode electrode 51 is A, then AI/A2
The X I OO (short rate) is designed to be 20% or less. 8 has a P emitter layer.

Next, I would like to talk about the test regarding the short rate.The manufacturing method and impurity concentration of the GTO having the structure shown in FIG. This is the same as that described in the explanation of the structure in the section ``Problems to be Solved'', and the short layer pattern was mesh-like. When the minimum gate trigger current of 1 g+ was lowered for each GTO, it was found that ■□ increased as the short-circuit ratio increased, and reached as much as a dozen A when the Noyot ratio exceeded 20%. In addition, in these prototypes, when the short rate is 10% or less, there is no significant difference in turn-on characteristics and on-state characteristics, but when it exceeds 10%, both characteristics gradually deteriorate, and when it exceeds 20%, it suddenly deteriorates. It was found that the condition gradually deteriorated.

On the other hand, in the conventional anode emitter short structure that does not have a PIN base structure, a short ratio of around 50% is usually used. This does not have a PIN-based structure, so
This is because even if the short-circuit rate was large, the value of Itl was suppressed to several A or less, and therefore no attention was paid to the short-circuit rate.

Furthermore, in order to investigate the influence of the arrangement pattern of the short layer,
Two types of GTO, a conventional GTO in which a short layer was provided directly below the N emitter layer, that is, so as to overlap its projected image, and a GTO according to the present invention, with a short ratio of 7%, were manufactured using the same manufacturing method as in the previous test. I made a prototype. The element diameter of these GTOs is 46 mmφ, the peak impurity concentration of the N base layer (N-Tang) is 2XIO"atoms/am', and the thickness is 7
00 μm, the peak impurity concentration of the N buffer layer (N' layer) is 2.3x lO"atoms/cm", and its thickness is 95 μm.The peak impurity concentration of the 1-shot layer (N'° layer) is sx 10 The short layer of the GTO according to the present invention was a strip pattern with a width of 200 μm.

For these GTOs, I gt and on-state voltage (vT,
4), there was almost no difference, but there was a big difference when looking at the tail loss. Figure 2 shows the prototype device at a junction temperature of 125°C and a cut-off current of 50°C.
0A, overcharge voltage peak (660Q) Shows the Tilmi flow part of the new waveform of OV.

For comparison, FIG. 2 also shows the results for an element with a short circuit ratio of 0%. (1) to (3) in Figure 2
) are the Tilmi flow portions of an element with a short circuit ratio of 0%, an element with a conventional structure, and an element of the present invention, respectively. From this result, it can be seen that the short layer arrangement pattern according to the present invention is considerably more effective in reducing the Tilmi flow than the conventional method.

Further, FIG. 3 similarly shows the turn-off loss of the prototype device. In FIG. 3, S and ~S3 are elements with a short circuit rate of 0%, respectively;
This corresponds to an element with a conventional structure and an element of the present invention. It can also be seen from FIG. 3 that the element of the present invention is effective in reducing switching loss.

The reason why the arrangement pattern of the Schiff-8 layer according to the present invention is more effective in reducing the Tilmi flow, that is, drawing out excess carriers in the N base layer during turn-off than the conventional arrangement pattern, will be described below.

First, regarding a GTO that does not have a PIN base structure, in this case, excess carriers in the N base layer at turn-off are concentrated directly under the cathode element. In particular, it tends to concentrate directly below the center of the cathode element. So,
It has been considered most effective to arrange the short layer pattern of the conventional anode emitter short structure near the center directly under the cathode element. However, in a GTO with a PIN base structure, excess carriers protrude from the cathode element due to the action of the low-resistance N bubble 77 layer, and the unit GT
It spreads throughout O. In addition, due to interaction with adjacent unit GTOs, excess carriers tend to concentrate particularly in a band shape passing through the center of the projected image of the cathode element of the unit GTO and intersecting almost perpendicularly. Therefore, the method of arranging a short layer in a pattern as in the present invention is most effective for extracting excess carriers.

Note that even when the present invention is applied to a static induction thyristor (S I Th) in which the main current conducting portion is formed of a PN junction, exactly the same effect can be obtained.

G1 Effects of the Invention According to the present invention, since the anode emitter short structure is combined with the PIN base structure, steady loss and switching loss can be reduced. and P.I.
By finding the relationship between the short-circuit rate and the turn-on characteristics and on-state characteristics in the N-based structure, the short-circuit rate was set to 20.
% or less, the turn-on characteristics and on-state characteristics are not impaired. Furthermore, focusing on the spread of excess carriers, the short layer is placed so as to pass through the center of the projected image of the cathode element in the longitudinal direction and to be perpendicular or approximately perpendicular to the projected image, further reducing the Tilmi flow. This makes it possible to reduce turn-off loss, for example, by about 50% without increasing turn-on loss and steady-state loss, compared to when a conventional short layer arrangement pattern is adopted. .

[Brief explanation of the drawing]

FIG. 1 is a structural diagram showing an element according to an embodiment of the present invention, and FIG.
The figure is a waveform diagram showing the Tilmi flow, Figure 3 is a comparison diagram showing the turn-off loss of each element, and Figure 4. 5, 7, and 8 are cross-sectional views showing conventional examples, and FIG. 6 is a graph showing turn-off characteristics. l...P gate layer, 2...N emitter layer, 3...
P base layer, 5. . . . Anode electrode, 6 . . . N-base layer, 7 . Gate 2 7X◆Babhua kidney 2 \Emitsuta layer 71・\0 Noyotori 3 P base layer
8-P4 emitter layer 6\-base layer Figure 4 Figure 5 Cross-sectional view of conventional example
6. Cross-sectional diagram of conventional example. Figure 6. Turn-off characteristic diagram. Figure 7. Cross-sectional diagram of conventional example. Figure 8. Cross-sectional diagram of conventional example.

Claims (1)

[Claims] (1) A P base layer made of a P type semiconductor, an N base layer made of an N type semiconductor, a buffer layer with a higher N type impurity concentration than the N base layer, and a P emitter layer made of a P type semiconductor are laminated in this order. Cathode elements are arranged in the form of islands in the P base layer, an anode electrode is provided in the P emitter layer, and an N-type semiconductor is provided between the buffer layer and the anode electrode to short-circuit them. In a self-turning element that is turned off by drawing a current from a gate layer provided on the P base layer, the short layer passes through the center of the projected image of the cathode element in the longitudinal direction. A self-extinguishing element, which is arranged so as to be perpendicular or substantially perpendicular to the projected image, and a ratio of a bonding area between the anode electrode and the short layer to an anode electrode area is 20% or less.