JPH04287373A - Gate turn off thyristor - Google Patents

Abstract

PURPOSE:To reduce the turn off loss of an anode-emitter shorted type GTO of high withstand voltage which has a pnipn structure, without damaging other characteristics such as gate current. CONSTITUTION:As shown by figure, in a GTO to which this invention is applied, a second part where carrier injection is restrained, i.e., a region 62 whose impurity concentration is lower than other region is formed in a P-type emitter layer 6, and a first part 61 of the P-type emitter layer 6 which part is a region where the injection amount of carrier is large is formed so as to be adjacent to a shorted layer 43.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate turn-off thyristor (hereinafter abbreviated as GTO), and more particularly to a junction structure suitable for reducing loss in a high voltage GTO.

0002

2. Description of the Related Art In order to increase the breakdown voltage of a GTO, the n-type base layer is generally made thicker, but this increases the on-voltage and turn-off loss, which increases the power loss generated in the device. For this reason,
Low loss is an important point for high-voltage GTOs. In order to reduce the loss of a high-voltage GTO, it is necessary to reduce the thickness of the n-type base layer to make the entire device thinner. A conventional technique that can maintain a high breakdown voltage and make the element thin is to provide an n-type semiconductor layer (hereinafter abbreviated as n-type buffer layer) with a higher impurity concentration than the n-type base layer in a region adjacent to the p-type emitter layer. The structure (hereinafter abbreviated as pnipn structure) is well known in general thyristors. When designing this structure, the following points must be taken into consideration. Due to carriers (leakage current) generated in the voltage blocking state, p
The type emitter layer operates and a small amount of holes are injected, but in order to obtain a high breakdown voltage, it is necessary to make the n-type buffer layer sufficiently thicker than the diffusion length of minority carriers to recombine and annihilate the injected holes. . However, in the anode short-circuit type GTO, the generated carriers are discharged from the short circuit, making it difficult for the p-type emitter layer to operate, so the thickness of the n-type buffer layer can be made thinner than when there is no short circuit. Therefore, in order to make the GTO high withstand voltage and low loss, it is necessary to use a p
It is effective to apply the nipn structure. However, at this time, since the short circuit resistance is reduced by the n-type buffer layer, the gate current required to trigger the GTO (hereinafter abbreviated as trigger gate current) becomes significantly large. Conventional techniques to solve this problem include a structure in which the short circuit is limited to a portion of the n-type emitter layer in the length direction, as described in Japanese Patent Application Laid-Open No. 63-265465, and a structure in which the short-circuit part is limited to a part of the n-type emitter layer in the length direction, and A structure in which a ring-shaped short circuit portion is provided as described in 88-57 is known.

0003

[Problems to be Solved by the Invention] In the above-mentioned conventional technology, since the ratio of the area of the p-type emitter layer to the anode surface increases, more holes are injected from the p-type emitter layer, and the number of excess carriers inside the device increases. However, there was a problem in that the turn-off loss increased and the loss generated by the element increased despite the pnipn structure.

The present invention has been made in view of the above points, and it is an object of the present invention to provide an anode-emitter shorted GTO having a pnipn structure with high breakdown voltage, low loss, and small trigger gate current.

[0005]

[Means for Solving the Problems] The above object can be achieved by providing means for suppressing injection of carriers from the anode side into the outer p-layer or its vicinity on the anode side. Means for suppressing carrier injection include configuring the outer p-layer from a high and low impurity concentration region or a thick and thin region, and providing a Schottky junction or an insulating layer near the outer p-layer. There is.

[0006]

[Function] By providing a means to suppress carrier injection, the short circuit resistance does not become small, so the trigger gate current does not increase. Moreover, by providing the above means, turn-off loss increases even if the area of the p-type emitter layer increases. can be prevented. Furthermore, if the short-circuit portion is located adjacent to a region where carrier injection is not suppressed, the turn-off loss can be further reduced due to the carrier discharge effect of the short-circuit portion during turn-off.

[0007]

[Embodiments] Examples of the present invention will be described below with reference to the drawings. Identical and equivalent parts in each drawing are given the same reference numerals.

FIGS. 1, 2, and 3 show an embodiment of an anode emitter short-circuited GTO embodying the present invention. FIG. 1 shows a quarter of the planar pattern on the cathode side, and FIG. A
FIG. 3 shows a longitudinal cross section along the line, and FIG. 3 shows a planar structure on the anode side. In the figure, a circular semiconductor substrate 1 has a p-type emitter layer 6, an n-type base layer 4, a p-type base layer 3, and an n-type emitter layer 6, an n-type base layer 4, a p-type base layer 3, and an
It has four consecutive layers of type emitter layer 2. On the main surface of the cathode side, a large number of elongated n-type emitter layers 2 are arranged in a six-layered ring shape with the longitudinal direction radial, and around them, a p-type base layer 3 is formed as an n-type emitter layer. 2
It is exposed so as to surround it. The n-type base layer 4 has a first portion 41 adjacent to the p-type base layer 3;
and a second portion (buffer layer) 42 adjacent to the p-type emitter layer 6 and having a higher impurity concentration than the first portion; and a second portion 4
2. It consists of a third portion 43 adjacent to the p-type emitter layer 6 and the main surface on the anode side and having a higher impurity concentration than the second portion 42. The p-type emitter layer 6 consists of a first portion 61 and a second portion 62 having a lower impurity concentration. On the main surface on the anode side, a first portion 61 and a second portion 62 of the p-type emitter layer 6 are arranged between the first portion 61 and a portion where each ring of the n-type emitter layer 2 is projected. 2 part 6
The third portion 43 of the n-type base layer 4 is placed in the remaining portion. An anode electrode 30 is provided on the entire main surface on the anode side, and a cathode
A cathode electrode 10 is provided on each n-type emitter layer 2 on the main surface of the main side.
, a gate electrode 20 is provided on the p-type base layer 3, respectively. A gate electrode 20 is provided to surround each n-type emitter layer 2. The surface where the pn junction is exposed is protected by an oxide film or silicone rubber, but is not shown in the figure. The third portion 63 of the n-type emitter layer 6 has a plurality of n
It is formed in a region projected toward the anode side of the region where the gate electrode 20 is provided between the type emitter layers 2, and consideration is given to increasing the area of the p emitter layer and preventing a decrease in short circuit resistance due to the pnin p structure. . In this embodiment, the impurity concentration of the second portion 62 of the p-type emitter layer 6 is set to be lower than that of the first portion 61 of the p-type emitter layer 6. Therefore, the area of the p-type emitter layer as a whole becomes larger, but since the amount of carriers injected from the second portion 62 is smaller than that from the first portion 61, excess carriers are generated in the entire device when conducting. As a result, turn-off loss can be reduced. moreover,
In this embodiment, the p-type emitter layer 6 has a large amount of carrier injection.
Since the third portion 43 (shorting layer) of the n-base layer 4 is formed adjacent to the first portion 61 of the n-base layer 4, carriers are quickly discharged from the shorting layer at the time of turn-off, which reduces turn-off loss. can be further enhanced. Furthermore, by arranging the first portion 61 with a large amount of carrier injection and the second portion 62 with a small amount of carrier injection in the p-type emitter layer 6, it is possible to reduce the increase in the on-voltage. Incidentally, in this embodiment, a structure in which the p-type emitter layer 6 is composed of only the second portion 62, that is, a structure in which the concentration of the entire p-type emitter layer is reduced, is also effective in reducing turn-off loss. However, the inventors have investigated that in order to prevent the on-voltage from increasing, the peak value of the impurity concentration of the p-type emitter layer should be set at 5×1017.
Atoms/cm3 to 3×1018Atoms/cm
3, and in order to obtain the desired characteristics, the impurity concentration must be controlled with high precision within this range. Therefore, it becomes difficult to manufacture the device, and in the case of a large-diameter device, the characteristics tend to vary within the device plane. In contrast, in the present invention, as shown in FIG. 2, the characteristics can be improved not only by changing the impurity concentration of the first portion 61 and the second portion 62 of the p-type emitter layer 6, but also by changing their dimensions X1 and X2. Since it can be changed, desired characteristics can be easily obtained. Moreover, only one element can partially handle X1 and X2
can be easily changed using a photomask pattern, for example, the characteristics can be adjusted for each ring of the n-type emitter layer 2 in FIG. 1 to make the switching operation of the entire device uniform and improve the cut-off withstand capability.

FIG. 4 is a longitudinal sectional view of another embodiment to which the present invention is applied. This embodiment differs from the previous embodiment in that the p-type emitter layer 6 is composed of a first portion 61 and a third portion having the same impurity concentration on the surface and a smaller thickness. That is, the junction depth of the third portion 63 from the anode-side main surface is shallower than that of the first portion 61. Therefore, the first portion 61 and the third portion of the p-type emitter layer 6
The second portion 42 of the n-type base layer 4 adjacent to the portion 63 of
The vertical dimensions L1 and L3 of are set to satisfy the relationship L1≦L3. Therefore, among the carriers injected from the third portion 63 of the p-type emitter layer, those that reach the first portion 41 of the n-type base layer 4 without being annihilated by recombination are It will be less than that from part 61. Therefore, this structure also reduces excess carriers during conduction and reduces turn-off loss. Furthermore, by combining this embodiment with the above embodiment, that is, by making the impurity concentration of the third portion 63 of the p-type emitter layer 6 lower than that of the first portion 61 in FIG. 4, the turn-off loss can be further reduced. increases.

Now, in the embodiments shown in FIGS. 2 and 4, the fact that the p-type emitter layer 6 is partially provided with a region in which the amount of carrier injection is suppressed has the effect of reducing the loss. First, second and third portions 61 of the mold emitter layer
, 62, 63, and the shorting layer 43 are not limited to these embodiments. For example, a structure as shown in FIG. 5 may be used. In this embodiment, a second portion of the p-type emitter layer is formed adjacent to the shorting layer 43.

A method of manufacturing the anode side of a GTO according to the present invention is shown in FIGS. 6 and 7. Although these are shown for the GTO of the embodiment shown in FIG. 4, they can be applied to each of the embodiments described above. FIG. 6 shows a manufacturing method using thermal diffusion. First, an n-type buffer layer 4 is formed on a semiconductor substrate 1 in advance.
After partially providing the shorting layer 43 and the first part 61 of the p-type emitter layer 6 on the second layer, a p-type impurity such as boron is deposited on the entire main surface on the anode side, and further drive-in is performed as appropriate. Second portion 6 of p-type emitter layer 6
form 2. Note that the second portion 6 of the p-type emitter layer 6
2 may be selectively deposited. On the other hand, FIG. 7 shows a manufacturing method using epitaxial growth. First, the second portion 62 of the p-type emitter layer 6 is formed over the entire main surface on the anode side by epitaxial growth. Then the shorting layer 43 and the first portion 6 of the p-type emitter layer 6
1 is provided partially.

A longitudinal sectional view of a GTO according to another embodiment of the present invention is shown in FIGS. 8 and 9. In the embodiment of FIG. 8, a Schottky junction 10 is used to suppress carrier injection on the anode side.
0 is partially provided. When triggering the GTO, the Schottky junction acts as a barrier for electrons because it is in a state close to thermal equilibrium in a low injection state before becoming conductive. Therefore, since this portion is not short-circuited, the trigger gate current does not increase even if the pnipn structure is used. Furthermore, even when conductive, almost no holes are injected from the Schottky junction, so excess carriers are reduced and turn-off loss can be reduced. On the other hand, in the embodiment shown in FIG. 9, an n-type semiconductor layer 9 is provided, but since this semiconductor layer and the anode electrode 30 are not short-circuited by an insulator 200 (for example, silicon oxide), the trigger gate current increases. do not. Furthermore, since it is an n-type semiconductor layer, no holes are injected, and turn-off loss can also be reduced. Also,
Since the n-type semiconductor layer 9 can be formed in the same way as the shorting layer 43,
It can be manufactured using almost the same process as conventional methods.

The planar structure on the anode side is not limited to that shown in FIG. 3 above. Other planar structures are shown in FIGS. 10, 11, and 12. In each figure, only the outline of the n-type emitter layer 2 is shown by a broken line. In any of the planar structures, as in the case of FIG. 3, the shorting layer 43 is formed in the region where the gate electrode 20 is provided between the plurality of n-type emitter layers 2 projected toward the anode side to reduce the shorting resistance. Preventing the decline. In FIG. 10, the first portion 61 of the p-type emitter layer 6 and the shorting layer 43 are formed in an elongated strip shape, and the second portion 62 of the p-type emitter layer 6 surrounds the first portion 61 and the shorting layer 43. It is set up like this. In FIG. 11, the first and second portions of the p-type emitter layer 6 have the same pattern structure as in FIG. 10, but since the shorting layer 43 is formed in the shape of a small hole, the shorting resistance is even higher than in the case of FIG. As a result, the trigger gate current is reduced. In FIG. 12, the shorting layer 43 is provided in a ring shape throughout the device as in FIG. 3, but the p-type emitter layer 6
The first portion 61 is formed in the second portion 62 of the cylindrical member 61 in the form of small holes. Such a pattern has the advantage that alignment of the patterns of the n-type emitter layer 2 and the p-type emitter layer 6 does not require much precision. In addition,
The above planar structure can be used in combination with the embodiments shown in FIGS. 8 and 9. In that case, the second portion 6 of the p-type emitter layer 6
2 is replaced with a Schottky junction or a non-shorted n-type semiconductor layer.

Since the GTO of the present invention has a high breakdown voltage and reduced turn-off loss, efficiency can be improved in a large-capacity device to which the GTO is applied. This is particularly effective in an inverter device as shown in FIG. 13, which requires high-speed switching. However, FIG. 13 shows a part of the main circuit, and the snubber circuit and freewheel diode connected in parallel to the GTO are omitted.

[0015]

As described in detail above, according to the present invention, an anode short-circuited GTO having a pnipn structure with high breakdown voltage and low loss can be obtained.

[Brief explanation of the drawing]

[Figure 1] Figure 1 shows an anode short-circuited GTO implementing the present invention.
cathode side plane pattern.

FIG. 2 is a sectional view taken along the cutting line in FIG. 1;

FIG. 3 shows the planar structure of the anode side of the embodiment.

FIG. 4 is a longitudinal sectional view of another embodiment.

FIG. 5 is a longitudinal sectional view of another embodiment.

FIG. 6 shows the manufacturing method of the present invention.

FIG. 7 shows the manufacturing method of the present invention.

FIG. 8 is a longitudinal cross-sectional view of another embodiment of the invention.

FIG. 9 is a longitudinal cross-sectional view of another embodiment of the invention.

FIG. 10 shows a planar structure of another anode side according to the present invention.

FIG. 11 shows a planar structure of another anode side according to the present invention.

FIG. 12 shows a planar structure of another anode side according to the present invention.

FIG. 13 shows a part of the main circuit of an inverter device to which the GTO of the present invention is applied.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1... Semiconductor base, 2... N-type emitter layer, 3... P-type base layer, 4... N-type base layer, 41... First part of n-type base layer, 42... Second part of n-type base layer, 43... Third part of n-type base layer, 6... P-type emitter layer, 61... First part of p-type emitter layer, 62... First part of p-type emitter layer, 63... P-type emitter layer First portion, 9... n-type semiconductor layer, 10... cathode electrode, 20... gate electrode, 30
... Anode electrode, 100 ... Schottky junction region, 20
0...Insulator.

Claims (18)

[Claims] Claim 1: A first portion having at least four pnpn layers between a pair of main surfaces, an intermediate n layer adjoining the intermediate p layer, and a first portion adjacent to the first portion and the outer p layer. a second portion having a higher impurity concentration than the second portion; and a third portion adjacent to the second portion and one main surface and having a higher impurity concentration than the second portion; A semiconductor substrate adjacent to the surface and a second portion of the intermediate n-layer and consisting of the first portion and a second portion having a lower impurity concentration, on one main surface of the semiconductor substrate, an outer p-layer and The third of the middle n-layer
an anode electrode that contacts the outer n-layer on the other main surface of the semiconductor substrate; a cathode electrode that contacts the intermediate p-layer and surrounds the outer n-layer on the other main surface of the semiconductor substrate; A gate turn-off thyristor characterized by having a gate electrode. 2. The gate turn-off thyristor according to claim 1, wherein the first and second portions of the outer p-layer have substantially the same thickness. 3. The gate turn-off thyristor of claim 1, wherein the thickness of the first portion of the outer p-layer is greater than that of the second portion of the outer p-layer. 4. In claim 1, 2 or 3, the semiconductor substrate has a circular shape, and the outer n layer is divided into a number of elongated shapes, each of which has a longitudinal direction radial on the other main surface. The first and second portions of the outer p-layer are arranged in a multi-ring shape, and are arranged so that each ring of the outer n-layer is overlapped with the other main surface when projected onto the main surface of the other. A gate turn-off thyristor featuring: 5. A first portion having at least four pnpn layers between a pair of main surfaces, wherein the intermediate n layer is adjacent to the intermediate p layer, and the first portion is adjacent to the first portion and the outer p layer. The outer p-layer is adjacent to one main surface and the second part of the intermediate n-layer, and the first part and the second part have a lower impurity concentration than the first part. a semiconductor substrate consisting of two parts; an anode electrode in contact with the outer p-layer and the second part of the intermediate n-layer on one main surface of the semiconductor substrate; 1. A gate turn-off thyristor comprising: a cathode electrode that contacts the layer; and a gate electrode that contacts the intermediate p layer and surrounds the outer n layer on the other main surface of the semiconductor substrate. 6. The gate turn-off thyristor according to claim 5, wherein the first and second portions of the outer p-layer have substantially the same thickness. 7. The gate turn-off thyristor of claim 5, wherein the thickness of the first portion of the outer p-layer is greater than that of the second portion of the outer p-layer. 8. In claim 5, 6, or 7, the semiconductor substrate has a circular shape, and the outer n layer is divided into a plurality of elongated shapes, each of which has a longitudinal direction radial on the other main surface. The first and second portions of the outer p-layer are arranged in a multi-ring shape, and are arranged so that each ring of the outer n-layer is overlapped with the other main surface when projected onto the main surface of the other. A gate turn-off thyristor featuring: 9. A first portion having at least four pnpn layers between the pair of main surfaces, wherein the intermediate n layer is adjacent to the intermediate p layer, and the first portion is adjacent to the first portion and the outer p layer. the outer p-layer is adjacent to one main surface and the second part of the intermediate n-layer, and the first part and the second part with a smaller thickness 2, on one main surface of the semiconductor substrate, the outer p
an anode electrode in contact with the outer n-layer on the other main surface of the semiconductor substrate, a cathode electrode in contact with the second portion of the intermediate p-layer on the other main surface of the semiconductor substrate, A gate turn-off thyristor comprising a gate electrode in contact with and surrounding an outer n-layer. 10. The gate turn-off thyristor according to claim 9, wherein the impurity concentration at the main surface of one of the first and second portions of the outer p-layer is approximately the same. 11. The gate turn-off thyristor according to claim 9, wherein the impurity concentration at one main surface of the first portion of the outer p-layer is higher than that of the second portion of the outer p-layer. 12. In claim 9, 10 or 11, a third portion having a higher impurity concentration than the second portion of the intermediate n-layer is provided at a portion of the second portion of the intermediate n-layer that contacts the anode electrode. A gate turn-off thyristor characterized by the provision of a gate turn-off thyristor. 13. In claim 9, 10, 11 or 12, the semiconductor substrate has a circular shape, and the outer n layer is divided into a large number of elongated shapes, each of which has a radial shape in the longitudinal direction on the other main surface. and are arranged in a multi-ring shape, and the first and second parts of the outer p-layer are ring-shaped and arranged so that each ring of the outer n-layer overlaps with the other main surface when projected onto the other main surface. A gate turn-off thyristor characterized by: 14. At least pnpn4 between the pair of main surfaces.
a first portion having an intermediate n-layer adjacent to an intermediate p-layer; a second portion adjacent to the first portion and the outer p-layer and having a higher impurity concentration than the first portion; It consists of a second part and a third part that is adjacent to one main surface and has a higher impurity concentration than the second part, and the outer p layer is adjacent to one main surface and the second part of the middle n layer. A semiconductor substrate comprising a semiconductor substrate, which is in ohmic contact with the outer p-layer and the third portion of the intermediate n-layer on one main surface of the semiconductor substrate, and has a Schottky structure between it and the second portion of the intermediate n-layer. - an anode electrode forming a junction, on the other main surface of the semiconductor substrate, a cathode electrode contacting the outer n layer, on the other main surface of the semiconductor substrate,
A gate turn-off thyristor comprising a gate electrode that contacts an intermediate p-layer and surrounds an outer n-layer. 15. In claim 14, the semiconductor substrate has a circular shape, and the outer n layer is divided into a plurality of elongated shapes, each of which is formed into a multi-ring shape with its longitudinal direction radial on the other main surface. arranged, an outer p layer and an intermediate n
A gate turn-off characterized in that the portion of the second portion of the layer that is in contact with the anode electrode is ring-shaped and is arranged so as to overlap each ring of the outer n layer when projected onto the other main surface. Thyristor. 16. At least pnpn4 between the pair of main surfaces.
a first portion having an intermediate n-layer adjacent to an intermediate p-layer; and a second portion adjacent to the first portion and the outer p-layer and having a higher impurity concentration than the first portion. a semiconductor substrate in which the outer p-layer is adjacent to one main surface and the second portion of the intermediate n-layer; an insulating layer disposed on the second portion; an anode electrode in contact with the second portion of the outer p layer and the intermediate n layer on one main surface of the semiconductor substrate; the other main surface of the semiconductor substrate; A gate turn-off thyristor comprising: a cathode electrode in contact with the outer n-layer; and a gate electrode on the other main surface of the semiconductor substrate, in contact with the intermediate p-layer and surrounding the outer n-layer. 17. In claim 16, the semiconductor substrate has a circular shape, and the outer n layer is divided into a plurality of elongated shapes, each of which is formed into a multi-ring shape with its longitudinal direction radial on the other main surface. The part of the outer p layer that is in contact with the anode electrode and the insulating layer are ring-shaped and the outer n
A gate turn-off thyristor characterized in that each ring of the layer is arranged to overlap the main surface of the other when projected onto it. 18. A semiconductor substrate comprising at least four pnipn layers, the outer p layer and the middle n layer having an anode electrode, the outer n layer having a cathode electrode, and the middle p layer having a gate electrode. 1. A gate turn-off thyristor, characterized in that the outer p-layer has means for suppressing carrier injection from the anode side.