JPH0131709B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a field-effect semiconductor device that can control channel current on and off at ultra-high speed.

[Technical background of the invention and its problems]

The operating speed of semiconductor integrated circuits is basically limited by carrier mobility. For this reason, various methods have been studied to construct integrated circuits using compound semiconductors such as GaAs and Al _x Ga _1-xAs , which have higher electron mobility than Si. Up to now, values of maximum electron mobility of about 8000 cm ² /V·sec have been obtained at room temperature. There have also been reports of attempts to improve the electron mobility value by an order of magnitude by cooling with liquid nitrogen, thereby significantly improving the operating speed of integrated circuits.

On the other hand, as is well known, complementary circuit configurations are useful for reducing power consumption of semiconductor integrated circuits.
Complementary circuits also have superior noise immunity. However, a typical complementary circuit is constructed using an n-channel element and a p-channel element, and its operating speed is limited by the lower value of electron mobility and hole mobility. In general, in the case of - group compound semiconductors (such as GaAs), the hole mobility is considerably lower than the electron mobility, and is only several hundred cm ² /V·sec at room temperature. Therefore, even if a complementary circuit is constructed using GaAs, the feature of high electron mobility is not utilized, and it is difficult to realize a high-speed operation circuit. Complementary circuits using n-channel elements and p-channel elements also have a problem in that the manufacturing process is more complex than integrated circuits using single conductive channel elements.

[Purpose of the invention]

The present invention enables channel current to be turned on and off at ultra-high speed using an externally controlled electric field, and also enables high-speed and low-power integrated circuits to be constructed by constructing a quasi-complementary circuit using a single conductive channel element. The purpose is to provide a semiconductor device that can be realized.

[Summary of the invention]

A semiconductor device according to the present invention includes a first semiconductor layer of a predetermined conductivity type serving as a current channel, and a non-conductive second semiconductor layer provided in contact with the first semiconductor layer and accommodating a current carrier of the semiconductor layer. a laminate including a semiconductor layer, first and second control electrodes provided on both sides of the laminate via an insulator layer, and a voltage between the first and second control electrodes. is applied to move a current carrier between the first and second semiconductor layers to control on/off of the channel current.

Here, the non-conductive second semiconductor layer may be, for example, a semiconductor layer in which carrier traps are introduced at high density to provide non-conductivity, or a semiconductor layer in which carriers move in the direction (lateral direction) along the layer. A semiconductor layer or the like that is provided with a blocking barrier to provide substantially non-conductivity is used. In the following description, the first semiconductor layer will be referred to as a current channel layer, and the second semiconductor layer will be referred to as a carrier storage layer.

In the semiconductor device according to the present invention, when the external control voltage applied between the first and second control electrodes is zero,
There are two types: one type in which the carrier is localized in the current channel layer, and another type in which the carrier is localized in the carrier storage layer. The former is a normally-on type switch element, and the latter is a normally-off type switch element. Whether the carrier is localized in the current channel layer or the carrier storage layer at zero external control voltage is determined by the built-in electric field. Methods for generating such a built-in electric field include introducing interfacial charges near the interface between the insulator layer and the semiconductor layer, and selecting materials for the control electrode and insulator layer to insulate the control electrode on the current channel layer side. There is a method of making the potential difference between the semiconductor layer and the carrier storage layer different from that on the carrier storage layer side.

〔Effect of the invention〕

The switching operation speed of the semiconductor device according to the present invention is not determined by the travel time of the carrier between the source and drain as in a normal MOS transistor, but is determined by the time of carrier movement between the adjacent current channel layer and the carrier storage layer. Ru. normal
The distance between the source and drain of a MOS transistor is several μm, and even with the most advanced microfabrication technology,
It is less than 1 μm. On the other hand, the average carrier movement distance during current switching in the device according to the present invention is about the thickness of the current channel layer and the carrier storage layer, which is different from the current thin film manufacturing technology such as molecular beam epitaxy. It can be easily realized even with a thickness of several hundred Å or less. Therefore, according to the present invention, an ultra-high speed current switching element can be obtained.

Further, the semiconductor device according to the present invention is of an electric field control type and has low power consumption. Moreover, normally
A pseudo-complementary circuit can be constructed by combining normally on-type elements and normally off-type elements with on-type and normally off-type elements in the same conductive channel. Therefore, according to the present invention, by selecting a conductivity type with high mobility, it is possible to realize various logic circuits, memory devices, etc., which are extremely high-speed and have low power consumption, as integrated circuits. Furthermore, it becomes possible to combine a pseudo-complementary circuit composed only of electrons and a pseudo-complementary circuit composed only of holes, increasing the degree of freedom in the design of integrated circuits.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view schematically showing the element structure of one embodiment, and FIG. 2 is a sectional view. In these figures, 1 is a current channel layer, and 2 is a non-conductive carrier storage layer that accommodates current carriers. Current channel layer 1 and carrier storage layer 2
In this example, semiconductor layers of the same type are successively stacked without creating any special barrier, and terminal electrodes 3 and 4 are provided at both ends of this stack to allow current to flow. Further, first and second control electrodes 7 and 8 are provided on both surfaces of this laminate with insulator layers 5 and 6 interposed therebetween, respectively. For convenience of explanation, spatial coordinate axes are shown in these figures, but the x direction is enlarged approximately 10 times as much as the other two directions.

If we explain the direction in which the channel current flows in the current channel layer 1 using these spatial coordinates, the first and second
Among the directions in which the control electrodes 7 and 8 face each other, that is, the y and z directions perpendicular to the x direction, the y direction is here assumed to be the direction in which the channel current flows. 2 terminal electrodes 2, 3
are arranged at predetermined intervals.

The carrier storage layer 2 is obtained by introducing high-density electron traps into an n-type semiconductor layer formed continuously by using an ion implantation method or the like, when the current channel layer 1 is an n-type semiconductor layer. This electron trap can also be introduced by adding impurity atoms with deep energy levels. In either case, the effective electron trap concentration is more than twice the existing donor concentration, thereby making the carrier storage layer 2 substantially non-conductive even if all the electrons in the current channel layer 1 are stored.

With such a configuration, the carrier storage layer 2
When a sufficiently strong electric field exists toward the current channel layer 1, conduction electrons in the current channel layer 1 move to the carrier storage layer 2 and are captured by an electron trap.
The current channel layer 1 is depleted and has no electrons contributing to conduction, and even if a voltage is applied between the terminal electrodes 3 and 4, no channel current flows. When the electric field is opposite to the above, electrons are emitted from the electron trap, move to the current channel layer 1, become conduction electrons, and a current flows between the terminal electrodes 3 and 4. Such an electric field can be controlled by applying an external control voltage Vc between the control electrodes 7 and 8, thereby controlling the current on and off.

In the case where an electron trap is introduced as the carrier storage layer 2, it takes a certain amount of time for electrons to be emitted from the electron trap, which is disadvantageous for ultra-high-speed switching operation. Therefore, an embodiment in which the carrier movement between the current channel layer and the carrier storage layer can be controlled only by the drift electric field is shown in FIG. 3 in correspondence with FIG. 2. Portions corresponding to those in FIG. 2 are given the same reference numerals as in FIG. 2. This example is
The carrier storage layer 2 is the same n-type semiconductor layer as the current channel layer 1 and has insulator regions 9 and 1 inside.
0 is used. insulator region 9,
10 is buried across the carrier storage layer 2 from end to end in the Z direction.

With this configuration, the insulator regions 9 and 10 form a high potential barrier against the movement of electrons in the y direction (lateral direction) within the carrier storage layer 2. That is, even if the electrons inside the carrier storage layer 2 are free electrons, they do not contribute to conduction between the terminal electrodes 3 and 4, and are substantially rendered non-conductive. Therefore, as explained in FIG. 2, by applying a control voltage between the control electrodes 7 and 8 and selecting whether to collect electrons on the current channel layer 1 side or on the carrier storage layer 2 side, , channel current is controlled on and off. Since electron movement in this case is rate-limited only by the drift electric field, a faster switching operation is possible than when the carrier storage layer of FIG. 2 is used.

By the way, there are two types of switch elements: a normally-off type that is off when the external control voltage is zero, and a normally-on type that is on when the external control voltage is zero. In the device of the present invention, a normally-off type,
It can be realized in either normally-on type. In each of the above embodiments in which electrons are used as carriers, in order to make the normally-off type, for example, Na from the surface of the insulating layer 6 is added near the interface between the insulating layer 6 and the carrier storage layer 2.
A positive interfacial charge with an appropriate areal density is formed by ion implantation or the like. Cross-sectional views of the device in this case are shown in FIGS. 4a and 4b. In these figures, 11 indicates the above-mentioned interfacial charge. FIG. 4a shows the case when the control voltage Vc=0, and the electrons 12 are localized in the carrier storage layer 2 due to the built-in electric field due to the interfacial charges 11, so that no channel current flows. Figure b shows the case where a constant positive voltage is applied as the control voltage Vc, and at this time the electrons 12 overcome the built-in electric field and move into the current channel layer 1, contributing to conduction.

In order to obtain a normally-on type element, contrary to the above, a positive interfacial charge may be formed near the interface between the insulating layer 5 and the current channel layer 1. As a result, electrons are localized in the current channel layer 1 when the control voltage Vc=0, and the channel current can be turned off by applying a constant negative voltage as the control voltage Vc.

Note that a normally-on type device can be realized without actively forming a built-in electric field and therefore without localizing electrons within the current channel layer.

An example of switching characteristics in the device structure shown in FIG. 3 will be explained below. The current channel layer 1 and carrier storage layer 2 were made of n-type Si with a donor concentration of 1×10 ¹⁶ /cm ³ , and the insulator layers 5 and 6 were made of SiO ₂ . Also, using the element dimensions written in Figure 3, L ₀ = 2.0 μm, L ₁
= L ₄ = 0.5 μm, L ₂ = L ₃ = 0.2 μm, W ₁ = W ₄ = 500
Å, W ₂ =W ₃ =800 Å. In addition, the insulator layer 6
The positive charge density near the interface with the carrier storage layer 2 is
Ns=6×10 ¹¹ cm ^-2 . FIG. 5 shows the current I-control voltage Vc characteristic when such numerical values are used. The current I is the width in the Z direction in Figure 1.
The value is per 1 μm. As is clear from the figure,
When a voltage V _D =1.0V is applied between the terminal electrodes 3 and 4, the current I changes from 5.4×10 ^-8 A/μm to 1.9× by changing the control voltage V _C from 0 to 1.0V.
It increases about 350 times to 10 ^-5 A/μm. Control voltage V _C
= 0, a slight current flows, but this is because the tail of the electron distribution localized in the carrier storage layer 2 remains slightly in the current channel layer 1 due to the built-in electric field, so to speak, as a leak current.

In the above case, when V _D = 1.0V and V _C = 0, a voltage higher than the internal voltage in the thickness direction (x direction) will be applied between electrodes 2 and 4 in the lateral direction (y direction). However, the electronic mechanism that turns off as expected even in this case will be explained using computer simulation results. In the calculation, the above interfacial charge density
In order to provide a condition equivalent to N _S using an external voltage with good symmetry, V _A = -0.6V is applied to the first control electrode 7, and V _B =0.6V is applied to the second control electrode 8 virtually. It was to be. The element dimensions are exactly the same as the conditions described above. Figure 6 shows the two-dimensional distribution of potential V(x,
y), Figure 7 shows the two-dimensional distribution of electron concentration n(x,
y). In either case, x and y are the same as in Figure 3.
It uses coordinates. In order to clearly distinguish between the semiconductor layer region and the insulator layer region, the former is shown by a solid line and the latter by a broken line on the curved surface. Furthermore, the magnification rate in the x direction is 10 times that in the y direction. In FIG. 6, -V(x, y) versus (x, y) is given to make it easier to understand the change in electron potential energy ψ. There is a large difference in electron energy between the semiconductor layer and the insulator layer, and in reality, in terms of electron potential energy, there is a high plateau with a vertical wall at the boundary with the solid line part in the broken line part, and the energy is reduced. Although it forms a barrier, this plateau is omitted in Figure 6.

As can be seen from FIG. 6, -V and therefore ψ become higher on the first control electrode 7 side due to the effect of the built-in electric field. As a result, as can be seen from FIG. 7, the electrons are pushed into the vicinity of the interface between the carrier storage layer 2 and the insulator layer 6 on the second control electrode 8 side. As already mentioned, these electrons are prevented from traveling in the y direction by the insulator regions 9 and 10 present in the carrier storage layer 2 and do not contribute to conduction. Also, as is clear from Figure 7,
Terminal electrode 3 and insulator region 9 in carrier storage layer 2
The electron concentration is extremely small in the region between
The voltage V _D between the terminal electrodes 3 and 4 is almost maintained in this region, and the potential gradient in the y direction is small in other regions. Furthermore, from the potential distribution in FIG. 6, a low electron energy barrier is formed in the region of the current channel layer 1 sandwiched between the insulator regions 9 and 10 in the carrier storage layer 2 and the insulator layer 5. I understand. In addition to the effect of the potential distribution described so far, this energy barrier works to further reduce the number of electrons contributing to conduction, and as a result, the current I
is almost completely blocked.

In the above embodiments, the device structure was shown very schematically. A more specific example of the structure in Figure 3 is shown in Figure 8.
This will be explained next using Figures a to d. First, as shown in FIG. 8a, a wafer in which an n-type layer 22 is epitaxially grown on a P ⁺ type Si substrate 21 is prepared. The n-type layer 22 contains a donor impurity of 1×10 ¹⁶ cm ⁻³ and has a thickness corresponding to the sum of the designed thicknesses of the current channel layer 1 and the carrier storage layer 2 described above. Then, the P ⁺ type substrate 21 in the element formation region of this wafer is etched to expose both sides of the n type layer 22, as shown in FIG. After that, as shown in Figure c, a selective oxidation method or the like is used to form a SiO ₂ film 23 for device isolation from the front surface so as to surround the device region, and from the back surface to form an electron barrier in the carrier storage layer. SiO ₂ film 2
Embed 4,26. After this, as shown in Figure d,
SiO ₂ films 26 and 27 are formed on both sides of the n-type layer 22, respectively.
Control electrodes 28 and 29 made of polycrystalline Si etc.
is formed, n ⁺ type layers 30 and 31 are diffused to take out current terminal electrodes, and terminal electrodes 32 and 33 are formed to complete the process.

As a result, a switch element is obtained in which the front side of the n-type layer 22 is used as a current channel layer, and the back side in which the SiO ₂ films 24 and 25 are embedded is used as a carrier storage layer. Whether to use the normally-on type or the normally-off type is determined by implanting Na ions from the front or back side at an appropriate acceleration voltage with the SiO ₂ films 26 and 27 formed.

By using the element structure of the present invention, a quasi-complementary circuit can be constructed by combining a normally-on type element and a normally-off type element in the same conductive channel. An example of its configuration is shown in FIG. 9 using the element cross-sectional view of FIG. 2. The regions of each element A, B are indicated by the numbers in FIG. 2 with suffixes a, b. A is a normal type with electron carriers in which a positive interfacial charge is formed on the insulator layer 5a on the side of the current channel layer 1a.
The on-type element B is a normally off-type element in which a positive interfacial charge is formed on the insulator layer 6b on the side of the carrier storage layer 2b, and uses electrons as carriers. As shown in the figure, the first control electrode 7a of element A and the second control electrode 8b of element B are grounded, and the second control electrode 8a of element A and the first control electrode 7b of element B are commonly connected. and the signal input terminal (V _io ), and the terminal electrodes 3a,
Connect 3b in common and use it as a signal output terminal (Vout),
The terminal electrode 4b is grounded and the terminal electrode 4a is connected to a positive power supply voltage (Vo).

Now, when the input signal is V _io = 0, element A is in an on state because electrons are in the current channel layer 1a, and element B is in an off state because electrons are in the carrier storage layer 2d, so the output signal is Vout. =Vo. Next, when the input signal V _io exceeds a certain positive voltage, element A moves electrons into the carrier storage layer 2a and turns off, and element B moves electrons into the current channel layer 1b, turning it on. The output signal becomes Vout=0.

In this way, the inverter operation is performed with the configuration shown in FIG. In the above operation, one of the elements A and B is on while the other is off, so no through current flows and power loss is extremely small.
In addition, the carriers involved in the above operation are only high-mobility electrons, and the state transition is due to electron movement over a short distance in the thickness direction of the semiconductor layer, so ultrahigh-speed operation is possible.

Note that the structure in which the elements A and B constituting the inverter are integrally integrated may be a laminated structure or may be a structure in which they are arranged in a planar manner.

In the above description, an example is shown in which n-type Si is used as the semiconductor material, but other semiconductor materials can be used. Among these, use of a - group compound semiconductor or its mixed crystal, which has a high electron mobility, is more advantageous in terms of high-speed operation. In this case, if a material with a large energy bandgap and good crystal lattice matching with the semiconductor material is selected for the insulator layer, single crystal growth techniques such as molecular beam epitaxy and MOCVD can be applied to form the layer structure. Therefore, a high-performance device can be obtained. Such embodiments are described below.

In the structure shown in FIG. 3, an AlSb single crystal substrate with a thickness corresponding to the sum of the thicknesses of the insulator layer 6 and the insulator regions 9 and 10 is used as a starting substrate, and this is etched to form the insulator regions shown in FIG. Convex portions corresponding to 9 and 10 are formed. Next, an n-type InAs layer containing donor impurities of ^{1.times.10.sup.16} cm.sup. ^- 3 is grown by molecular beam epitaxy to form portions corresponding to the carrier storage layer 2 and current channel layer 1 shown in FIG. The convex portions formed corresponding to the convex portions of the current channel layer are removed by etching, and then an AlSb layer corresponding to the insulator layer 5 of FIG. 3 is grown again by molecular beam epitaxy. Finally, predetermined electrodes are formed to complete the device.

Figure 10 shows the normal graph obtained in this way.
The distribution of the electron concentration n (broken line) and the potential distribution (solid line) when the control voltage V _C =0 of the off-type element are shown. The AlSb layers as insulator layers are each 500 Å, n-
The InAs layer has a carrier storage layer part and a current channel layer part of 400 Å each, and the carrier storage layer side
This is a case where the interfacial charge density of the AlSb layer is Ns=8×10 ¹¹ cm ^-2 . Electrons are concentrated on the right side of point M in the figure, that is, in the carrier storage layer. The distribution of the potential V shown in FIG. 10 is based on the assumption that interfacial charges of -Ns/2 and +Ns/2 are distributed at the AlSb layer interfaces on both sides, respectively, taking symmetry into consideration.

A control voltage V _C =
When applying 1.405V, n and -V in the InAs layer
The change in is the result of turning left and right at point M in FIG. 10, and electrons gather in the positive current channel layer.

Similar structure with positive interfacial charge on the current channel layer side
If formed at the interface of the AlSb layer, it becomes a normally-on type device.

Next, an example in which a built-in electric field is formed without introducing interfacial charges by ion implantation will be described. As is well known, the potential difference between metal and semiconductor in MIS structures changes depending on the work function of the metal, the insulator, and the electron affinity of the semiconductor. Therefore, by appropriately selecting materials in each of the above embodiments, it is possible to form a potential gradient within the semiconductor layer. To give a specific example, 1
×10 ¹⁶ cm ^-3 n-type Si thickness 400 with donor impurity
Prepare a sample of 200 Å on both sides.
After forming the SiO ₂ film, Au was added as the first control electrode.
An Al electrode is formed as an electrode and a second control electrode.
At this time, the distributions of the potential V and the electron concentration n in the x direction are shown in FIG. 11 by solid lines and broken lines, respectively. As shown in the figure, an internal electric field is formed, the half of the n-type Si layer on the Au electrode side is sufficiently depleted, and electrons are localized on the Al electrode side half. If the half on the Al electrode side is made into a carrier storage layer with non-conductivity as in the embodiment described above, a normally-off type device can be obtained, and if the half on the Au electrode side is made into a carrier storage layer, a normally on type device is obtained. An element is obtained. These elements must be of proper polarity.
On/off control can be performed using a control voltage of 0.9V.

In the above embodiments, an inverter in which two elements are combined has been described, but various logic circuits, memory devices, etc. can be constructed by combining three or more elements. Further, in the above embodiments, electrons are used as current carriers, but if it is more advantageous to use holes in terms of mobility or other aspects, a similar element can be constructed using a p-type semiconductor. Therefore, when a functional element is realized by combining a plurality of elements, an element that uses electrons and an element that uses holes may be combined as necessary.

[Brief explanation of drawings]

Fig. 1 is a perspective view schematically showing the element structure of one embodiment of the present invention, Fig. 2 is a sectional view of the same, Fig. 3 is a sectional view showing the element structure of another embodiment, and Figs.
b is a diagram for explaining the operation of a normally-off type element due to interface charge introduction, Figure 5 is a diagram showing an example of current-control voltage characteristics of a normally-off type element with the structure of Figure 3, and Figure 6 is Similarly, FIG. 7 is a diagram showing the potential distribution within the element, FIG. 7 is a diagram similarly showing the electron concentration distribution within the element, FIGS. 8 a to d are diagrams showing a more specific manufacturing process example of the structure of FIG. 3, and FIG. 10 is a diagram showing a quasi-complementary inverter combining two elements, FIG. 10 is a diagram showing the potential and electron concentration distribution in an element of an example using a compound semiconductor, and FIG. 11 is a diagram showing still another example. FIG. 2 is a diagram showing the potential and electron concentration distribution within the device. 1... Current channel layer (first semiconductor layer), 2...
Carrier storage layer (second semiconductor layer, 3, 4... current terminal electrode, 5, 6... insulator layer, 7... first control electrode, 8... second control electrode, 9, 10... insulator region ( barrier), 11...interfacial charge, 12...electron (carrier).

Claims (1)

[Claims] 1. A first semiconductor layer, a non-conductive second semiconductor layer provided in contact with the first semiconductor layer, and both sides with these first and second semiconductor layers in between. opposing first and second control electrodes provided respectively through an insulator layer, and the first semiconductor layer;
first and second terminal electrodes provided at a predetermined interval to flow a channel current in a direction perpendicular to the direction in which the first and second control electrodes face each other; A semiconductor device characterized in that a voltage is applied between control electrodes to move a current carrier between the first and second semiconductor layers to control on/off of a channel current. 2 The second semiconductor layer has a high density carrier layer.
The semiconductor device according to claim 1, which is made non-conductive by introducing a trap. 3. The semiconductor device according to claim 1, wherein the second semiconductor layer is made non-conductive by providing therein a barrier that prevents the carrier from traveling in a direction parallel to the direction of the channel current. .