GB2258344A - Lt-gaas semiconductor device - Google Patents

Abstract

A semiconductor device e.g. a FET, includes a substrate (1) with source (3) and drain (4) regions and a gate electrode (5) which controls conduction in a channel (7) between the source and drain. The gate electrode 5 is insulated by a dielectric layer of LT-GaAs material (6) from the channel. A separating layer (8) of ALGaAs shifts the channel out of contact with the dielectric layer (6), forming a 2-D carrier gas at a AlGaAs/GaAs interface, extending between the source and drain. The LT-GaAs layer is formed by MBE and etching. A complementary pair of such devices is also disclosed. <IMAGE>

Description

LT-GaAs SEMICONDUCTOR DEVICE DESCRIPTION This invention relates to a semiconductor with an improved gate structure and has particular but not exclusive application to a field effect transistor (FET).

A number of different gate structures have previously been proposed for FETs and a review is given in Chapter 2 of InGaAs Field-Effect Transistors, Klaus Heime, John Wiley & Sons Inc, 1989.

In a GaAs MESFET, current flowing in a doped semiconductor channel between a source and drain is controlled by a metallic gate which forms a Schottky contact with the semiconductor channel. This diode contact is reverse biased by an applied gate voltage typically to form a depletion region in the channel so as to control current flow between the source and drain in dependence upon the gate voltage. In an alternative structure, known as a JFET, a diffused pn-junction is utilised instead of the Schottky contact.

An alternative gate structure gives rise to a device known as a MISFET. In this device, a gate consists of an electrode to receive a gate voltage, which overlies an insulating, dielectric layer formed over the channel. The gate voltage produces by a capacitive action an electrostatic field in the channel which creates and controls the flow of carriers in the channel, in dependence upon the applied gate voltage.

In a MISFET, carriers in the channel are attracted by the gate voltage rather than being partially repelled as in a MESFET or JFET, this attraction of carriers being known as an enhancement mode of operation.

Depending upon the type of doping of the channel, the carriers in the channel region can be electrons or holes. Also, depending on the polarity of the gate voltage, an accumulation layer or an inversion layer of charge is formed in the region of the gate in the channel, that controls the density carriers in the channel in dependence upon the value of the gate voltage. The dielectric layer inhibits current flow between the channel and the gate electrode.

Insulated gate FETs has been implemented in Si for many years and are known as MOSFETs wherein the insulating layer for the gate is formed of SiO2 which can readily be grown on the Si substrate. However, for GaAs devices, an insulating layer cannot be so easily formed. There have been many attempts in the past to deposit an insulating gate structure on the surface of GaAs. For example, one approach taken in the past is to deposit silicon dioxide or alkali metal fluorides on the surface of GaAs. Also, much work has been done upon the use of natural oxides of GaAs as the insulating material. However, none of these approaches has yielded a device with the performance and reliability of a silicon NOSFET.

In accordance with the present invention, it has been appreciated that low temperature (LT) GaAs material is suitable for forming an improved insulating layer in an insulated gate structure, for use in a GaAs semiconductor device. A discussion of LT-GaAs will now be given.

The usual method of achieving GaAs homoepitaxy in a MBE system is to cause beams of As, and Ga to impinge on a GaAs substrate which is held at a temperature between 550-6500C. - J.E. Davey and T. Pankey, J. Appl. Phys.

39, 151 (1968). At such high temperatures the excess of arsenic on the surface of the growing layer evaporates which results in the growth of a good quality crystalline film with the stoichiometry of a near perfect crystal lattice. If the temperature of the film is lowered to near the region of 2000C, the excess arsenic does not have a chance to evaporate, resulting in it being incorporated into the growing film. For such growth temperatures, the excess of As atoms in the layer is around 1%, which represents a dopant concentration of approximately 1020 cam 3, which is an extremely high concentration. The As grown layer is heavily defected, but it is possible to anneal out most of the damage if the temperature is raised to 6000C for a suitable period such as ten minutes in the MBE chamber before the sample is removed.The resulting layer is of a high crystal quality and possesses a high electrical resistivity and a large breakdown strength. Such material is referred to in the art as LT-GaAs. In accordance with the invention, it has been appreciated that LT-GaAs ofers an intrinsic compatability with GaAs which permits the formation of improved insulated gate structures in a GaAs semiconductor device.

Thus, in accordance with the invention, there is provided a semiconductor device comprising means defining a semiconductor region, gate means for capacitatively inducing an electric field in the region for controlling electrical characteristics thereof, said gate means including an electrode for receiving an applied gate voltage and an electrically insulating dielectric layer between the electrode and the region, said dielectric layer being formed of LT-GaAs material.

Preferably the invention includes separating means for separating the channel from the dielectric layer.

The invention has particular but not exclusive application to the fabrication of MISFETs and embodiments thereof will now be described by way of illustrative example with reference to the accompanying drawings, wherein: Figure 1 is a schematic sectional view of a MISFET according to the invention; Figure 2 is a sectional view of a MISFET according to the invention with a buried channel; and Figure 3 is a sectional view of a MISFET with a patterned gate for producing an array of quantum dots.

An illustration is given in Figure 1 of a GaAs MISFET structure, which utilises a layer of Lt-GaAs as the gate insulator. The device consists of a GaAs substrate 1 with a lightly p doped region 2. Heavily doped n source and drain regions 3, 4 are formed in the region 2.

A conductive gate 5 overlies the substrate 1. The gate is formed on a layer of LT GaAs insulation material 6 which overlies the substrate 1 between the source and drain regions 3, 4.

In use, bias voltages are applied to the source 3 and gate as shown schematically and an electron channel 7 is created electrostatically which extends between the source and drain regions.

Thus, the voltage applied to the gate 5 capacitively induces an electron channel, the value of the gate voltage controlling the density of carriers in the channel and hence the conduction between the source and drain regions.

Those skilled in the art will appreciate that the structure of the device has a certain resemblance to the structure of an Si-MOSFET, but implemented in GaAs where LT-GaAs takes the place of the silicon dioxide gate insulation.

The device can be manufactured by an MBE method and the LT-GaAs insulation layer 6 can be grown in the manner described hereinbefore, i.e. by an MBE method, typically at a temperature in a range of 150-3500C, with subsequent annealing at a somewhat higher temperature.

Investigations of the internal structure of an annealed LT-GaAS reveals that the material has arsenic inclusions of the order of the 6nm in diameter, spaced on average 20nm apart - A.C. Warren, J.M. Woodall, J.L. Freeouf, D. Grischkowsky, D.T. McInturff, M.R.

Nelloch, and N. Otsuka, Appl. Phys. Lett., 57, 1331 (1990). It is currently thought that these centres act as traps for carriers in the bulk of the material thereby resulting in its high resistivity. Thus, the thicknesses of the layer 6 should be selected to be sufficient in order to present a suitably homogeneous spatial insulation property.

In the device shown in Figure 1, a positive gate voltage will attract electrons to the interface of the LT-GaAs layer 6 and the lightly doped GaAs region 2 forming an inversion layer of minority carriers, which in this case is electrons, which forms the conductive channel 7 between the source and drain regions 3, 4. An alternative structure could be formed with p-type source and drain regions 3, 4 and a n-type channel region 2, in which case an inversion layer will also be formed under the gate. Furthermore, it is possible to construct devices which produce an accumulation layer of majority carriers under the gate in the channel region 2. One example comprises a lightly doped n-type channel region 2 with n source and drain regions 3, 4.

Another example comprises a lightly doped p-type + channel region 2 with p source and drain regions 3, 4.

All the four examples are thus enhancement mode devices with either the inversion layer or the accumulation layer being controlled as a function of the voltage applied to gate electrode 1, and the respective accumulation or inversion layer controls carrier flow between the source and drain regions 3, 4. As long as the crystal is of high quality in the region of the GaAs/LT-GaAs interface between region 2 and LT-GaAs layer 6, a high mobility two-dimensional electron or hole gas is formed and the conductance along the channel 7 is thus controlled in an enhancement mode, in accordance with the source-gate voltage which capacitively induces an accumulation or inversion layer thereby controlling the level of conduction.This contrasts with the conventional MESFET or JFET wherein instead of capacitively inducing the controlling field, a reverse-bias diode structure is utilised for the gate, which produces a depletion region in the channel.

In practice, it may be difficult to achieve a satifactorily high quality crystal interface between the GaAs region 2 and the LT-GaAs layer 6. A solution to this difficulty is shown in Figure 2 wherein a AlGaAs buffer layer 8 is formed in the GaAs substrate 1 so as to form an interface with the lightly doped GaAs region 2. As is well known in the art, this particular heterojunction can be the site of a two-dimensional electron gas of an extremely high mobility, which indicates its near perfect crystalline quality and atomic abruptness. In Figure 2, this electron gas is used to define the electron channel, which is thereby buried in the substrate 1. The resulting buffering of the electron channel results in a higher charge mobility in the electron channel than in the structure of Figure 1.

In use, the gate voltage capacitively creates and controls the carrier flow in the channel region 7, the electric field extending through the gate insulation layer 6 and the AlGaAs buffer layer 8. It should be noted that the conductive channel can be formed either above or below the AlGaAs buffer layer with an insulated gate which is either above or below the channel region. In the latter case, such a structure is referred to herein as a backgated device, and examples will be described hereinafter with reference to Figures 4 and 5.

It will be appreciated that the buffer layer 8 could be utilised in any one of the four examples of the device described with reference to Figure 1.

In Figures 1 and 2, the gate 5 can either be formed as a metalisation layer or more conveniently as a heavily doped e.g. n GaAs region. If the latter is utilised, all the layers shown in Figures 1 and 2 can be formed by MBE methods on a GaAs substrate, which greatly facilitates fabrication. Since all of the materials are GaAs derived, they can be etched by common etching methods e.g. with citric acid, which greatly simplifies the formation of relevant geometries.

The invention has particular application to the formation of low dimensional systems which operate utilising individual or small numbers of charge carriers. Typically, the carriers are constrained to flow in a single crystal lattice direction e.g. along a quantum wire, or are constrained to a particular location e.g. a quantum dot. Such techniques are described in our co-pending UK patent application Nos.

9103083.3; 9100136.2 and 9101624.6. Conventionally, a two dimensional electron gas is formed in the substrate by a technique known as modulation doping H.L. Starter, R. Dingle, A.C. Gossard, W.

Wiegmann and M.D. Sturge, Solid State Comm., 29, 705 (1979) and H.L. Stbrmer, J. Phys. Soc. Jpn, 49, Suppl. A, 1013 (1980). The carriers in the gas are constrained to dots or wires by a surface pattern of electrodes that apply controlling fields to the electron gas. In modulation doping the polarity and density of charge carriers is primarily determined by the spatial distribution of dopant introduced into the substrate when the wafer is grown in an MBE chamber.

This contrasts with the devices shown in Figures 1 and 2 in which the density of charge carriers is determined primarily by the gate voltage.

Hitherto, it has been difficult to pattern gates insulated with SiO2 in order to create lateral 2 patterns, due mainly to the chemical inertness and mechanical toughness of SiO2. In contrast, GaAs is a more reactive material which can be reliably etched with many more simple and less hazardous etching techniques, e.g mild acid etch or dry plasma etching.

Accordingly, if LT-GaAs is used as a gate insulator, it can be much more easily patterned than a conventional SiO2 insulating layer.

Figure 3 shows an example of a low dimensional device in accordance with the invention, for producing an array of dots. The device consists of a GaAs substrate 1 with a lightly doped surface region 2, in to which heavily doped source and drain regions 3, 4 are formed. A LT-GaAs layer 6 is formed overlying the region 2 and is patterned by a suitable etchant to form an array of circular detents 9 therein. A gate electrode 10 overlies the layer 6.

When a bias voltage is applied to the gate electrode 10, carriers are attracted to the underside patterned gate where the field strength is sufficiently high, which in this case is only underneath the detents 9. The resulting pockets of carriers 11 will then contain individual or small numbers of electrons.

Examples of devices using dots are described in our co-pending patent application No. 9102582.5.

In an alternative structure, the detents 9 are replaced by elongate trenches so as to define quantum wires.

The trenches can be formed by a similar suitable etching method.

Although not shown in Figure 3, it will be appreciated that in practice the structure may include an ALIGaAs separating layer corresponding to the layer 8 of Figure 2, to separate the pockets of charge carriers 11 from the LT-GaAs layer 6, for the reasons previously discussed.

An example of an n-type backgated device as shown in Figure 4. The substrate 1 includes a lightly p-doped region 2. Heavily doped n source and drain regions 3, 4 are formed in the region 2. The source and drain regions 3, 4 are provided with metal contacts 13, 14.

In this device, the control gate is arranged as a back gate 15 which underlies a LT-GaAs layer 16, which itself underlies a separating AlGaAs layer 17.

In use, bias voltages are applied to the metal contacts 13, 14 and an electron channel is created electrostatically which extends between the source and drain regions 3, 4 by virtue of a control voltage being applied to the back gate 15. The value of the gate voltage controls the density of carriers in the channel and hence is a conduction between the source and drain regions. In the embodiment of Figure 4, the junction between the undoped GaAs substrate 2 and the AlGaAs layer forms a two-dimensional electron gas in a manner well known per se, which in this example, is used as the mechanism for conduction between the source and drain.

Referring to Figure 5, this shows a device similar to Figure 4 but with p source and drain regions 3, 4 with the result that with an appropriate bias regime, a two-dimensional hole gas is created at the interface of the substrate 2 and the AlGaAs layer 17.

The advantage of using LT-GaAs as the gate insulator 16 in Figures 4 and 5 as opposed to intrinsic GaAs is that the thickness of the material between the gate and the conducting channel can be made smaller due to the following reasons. Firstly, the breakdown strength of LT-GaAs is higher than intrinsic GaAs and so the field strength across the device can be made larger.

Secondly, the background doping density in LT-GaAs can be increased somewhere in the region of 1017 cm 3 to 1owl8 cm'3 before the layer has any appreciable contactivity i.e. far higher than normal GaAs. One problem which is encountered with backgated structures is that the top contacts tend to spike down to the substrate gate, leading to a large gate leakage current to the channel. When ordinary GaAs is used, it is necessary for the layer between the channel and the gate to be of the order of lpm in thickness. Due to the superior properties of LT-GaAs, this distance can be reduced leading to an increase in the transconductance of the device.

Referring to Figure 6, this shows a device with a normally on p-type channel, with gate insulation formed by LT-GaAs. More specifically, the device comprises a semi-insulating gallium arsenide substrate 1 with an undoped GaAs overlayer 2. P-type source and drain regions 3 and 4 are formed in the layer 2. Overlying gate electrode 5 is insulated by LT-GaAs layer 6 from conductive channel 7. Separation layer 8 comprising AlGaAs includes dopants that create a hole gas at the interface of the layers 2, 8.

In this structure, when no bias is applied to the gate 5, a hole gas exists at the heterojunction interface between the layers 2, 8. When a positive bias is applied to the gate, the positively charged holes in the hole gas are repelled from underneath the gate and hence the structure becomes insulating. This configuration has the advantage that it can be combined with the device shown in Figure 2 to provide complementary logic circuits.

Referring to Figure 7, this shows a first example of the complementary logic circuit incorporating a device in accordance with the invention. As shown in Figure 7, the transistor corresponds to the device described with reference to Figure 2 which comprises an n-channel, normally of transistor. The component parts of the transistor are annotated with the same reference numerals as in Figure 2. The transistor is additionally shown to include source and drain metallisation contacts 13, 14. The channel 7 is connected in series with a resistor R. between a positive rail +V and earth. An output Vout is taken between the resistor R. and the transistor. As the gate voltage +Vg is increased, the transistor switches from high to low conductivity.The output voltage Volt, r which is determined by the potential divider circuit defined by the resistor R. and the transistor, then switches from high to low voltage, when the transistor begins to conduct. The output voltage characteristic is shown as a graph in Figure 8. This circuit suffers from the fact that the current flows in the device all of the time. A more useful type of device is a complementary inverter, as will now be described with reference to Figure 9.

In this Figure, complementary transistor devices corresponding to those described with reference to Figures 2 and 6 are referenced as transistors T1 and T2 respectively. From the foregoing, it will be appreciated that transistor T1 is a normally off device whereas transistor T2 is a normally on device. The gates 5 of the transistors T1 and T2 are both connected to a gate voltage source Vg whereas the channels 7 of the devices are connected in a series between the voltage source +V5 and ground. A voltage output Vout is taken at the series connection between the channels 7 of the transistors T1, T2. The circuit thus provides a complementary inverter. When a positive bias Vg is applied to the gate terminals 5 of the transistors T1, T2, the normally-on, p-type device T2 switches off and the normally-off, n-type device T1 switches on. This action switches the output Vout of the device from on to off. Accordingly, the input/output voltage characteristic is as shown in Figure 10. As with normal silicon based complementary logic devices, the power consumption of the circuit shown in Figure 9 can be made low, which achieves numerous advantages as will be readily apparent to those skilled in the art.

Referring now to Figure 11, this shows the gallium arsenide substrate 1 formed with a two-dimensional electron gas defined by a GaAs/AlGaAs heterointerface or a delta-doped layer (very thin, very high concentration of dopants). Thus, typically, the device includes and AlGaas layer 20 which produces a two-dimensional electron gas 21. A gate electrode 5 is formed on a low temperature gallium arsenide layer 6.

Trenches 22, 23 isolate lateral regions 21a, 21b of the electron gas from a channel region 2 1c thereof, which underlies the gate electrode 5. Source and drain regions (not shown) are connected to the channel region 21c into and out of the plane of the paper, for example in the manner shown in Figure 2.

Additionally, heavily doped regions 25, 26 are formed laterally of the channel so as to form electrical connections with regions 21a, 21b of the two-dimensional electron gas. Thus, by applying control potentials to the regions 25, 26 a lateral bias can be applied to the two-dimensional electron gas in the channel region 21c. Accordingly, conduction in the channel 21c can be controlled by not only the bias supplied to gate 5, but also by the potential supplied to the regions 25, 26, which cooperate with the portions 21a, 21b of the two-dimensional electron gas so as to define in-plane gates.

Referring now to Figure 12, this shows a similar arrangement in which the trenches are replaced by Schottky gates. Like parts to those shown in Figure 11 are given the same reference numbers. Thus, Schottky gates 27, 28 are formed on lateral, longitudinal sides of the insulating LT-GaAs layer 6 so as to produce depletion regions 21d, 21e that correspond to the trenches 22, 23 shown in Figure 11. It will be appreciated that by applying a bias voltage to the electrode 25, an in-plane bias can be applied to the conductive channel region 21c of the two-dimensional electron gas. Whilst the conduction in channel 21c is typically produced by electrons, a two-dimensional hole-gas can be utilized if desired.

Claims (25)

1. A semiconductor device comprising means defining a semiconductor region, gate means for capacitivelyinducing an electric field in the region for controlling electrical characteristics thereof, said gate means including an electrode for receiving an applied gate voltage and an electrically insulating dielectric layer between the electrode and the region, said dielectric layer being formed of LT-GaAs material.

2. A semiconductor device according to claim 1 including separating means for separating the channel from the dielectric layer.

3. A semiconductor device according to claim 1 or 2 wherein said semiconductor region is defined in a GaAs substrate.

4. A semiconductor device according to any preceding claim including source and drain regions at opposite ends of the semiconductor region whereby to define a channel the conductivity whereof is controlled capacitively by the gate voltage.

5. A semiconductor device according to any preceding claim wherein said gate electrode is formed by a metallisation layer.

6. A semiconductor device according to any one of claims 1 to 5 wherein said gate electrode is formed of heavily doped semiconductor material.

7. A semiconductor device according to claim 2 wherein said separating means comprises a buffer layer for forming a two-dimensional electron gas for use as the conductive region.

8. A semiconductor device according to any preceding claim wherein said dielectric layer has a spatially modulated thickness whereby said gate means capacitively induces a spatially modulated carrier distribution in the semiconductor region.

9. A semiconductor device according to claim 8 wherein said spatially modulated field defines a plurality of dots.

10. A semiconductor device according to claims 8 or 9 wherein said spatially modulated field defines at least one wire.

11. A semiconductor device according to any preceding claim wherein the gate means is configured as a back gate.

12. A semiconductor device according to any preceding claim including a complementary pair of the devices with their conductive regions connected in series and their gate means connected to a common gate voltage source.

13. A semiconductor device according to any preceding claim including at least one in plane gate for controlling conduction in said region.

14. A semiconductor device according to claim 13 including a trench separating the in-plane gate from the region.

15. A semiconductor device according to claim 13 including a Schottky gate for providing a depletion region to separate the in-plane gate from said conductive region.

16. A semiconductor device substantially as hereinbefore described with reference to Figures 1, 2, 3, 4, 5, 6, 7 and 8, 9 and 10, 11 or 12 of the accompanying drawings.

17. A method of fabricating a semiconductor device comprising providing a GaAs substrate with conductive region forming on the substrate a dielectric layer of LT-GaAs material, and forming an electrode on said dielectric layer for capacitively inducing charge carriers in the region for controlling conduction thereof.

18. A method according to claim 17 wherein said LT-GaAs material is grown in an MBE system at a temperature whereat arsenic in excess of that required for stoichiometry is captured in said dielectric layer.

19. A method according to claim 18 wherein said dielectric layer is grown at a temperature of 150-3500C.

20. A method according to claim 18 or 19, wherein said dielectric layer is thereafter annealed at a temperature greater than the temperature at which it is grown.

21. A method according to any one of claims 17 to 20 wherein said dielectric layer is etched into a predetermined geometry.

22. A method according to claim 21 wherein said electrode is etched into a predetermined geometry.

23. A method according to any one of claims 17 to 22 wherein said dielectric layer is etched to have a spatially modulated thickness.

24. A method according to any one of claims 17 to 23 wherein said conductive region is separated from said dielectric layer.

25. A method of forming a semiconductor device substantially as hereinbefore described with reference to Figures 1, 2, 3, 4, 5, 6, 7 and 8, 9 and 10, 11 or 12 of the accompanying drawings.