JPH01315170A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH01315170A
JPH01315170A JP1107640A JP10764089A JPH01315170A JP H01315170 A JPH01315170 A JP H01315170A JP 1107640 A JP1107640 A JP 1107640A JP 10764089 A JP10764089 A JP 10764089A JP H01315170 A JPH01315170 A JP H01315170A
Authority
JP
Japan
Prior art keywords
wiring pattern
semiconductor
semiconductor pellet
package
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1107640A
Other languages
Japanese (ja)
Inventor
Tetsuo Matsumoto
哲郎 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1107640A priority Critical patent/JPH01315170A/en
Publication of JPH01315170A publication Critical patent/JPH01315170A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To contrive the reduction of production cost by forming a wiring pattern on a base face for attaching semiconductor pellets and by attaching them by insulator coated on the wiring pattern. CONSTITUTION:Bonding posts 3 are electrically connected through output terminal lead pins 6 for taking out the output of an inside circuit of a semiconductor pellet 2 and a wiring pattern 5. The wiring pattern 5 is not only formed on a base face area to which the semiconductor pellet 5 is not attached but also on the base face of the area to which the semiconductor pellet 2 is attached as a metallized layer. Therefore, an insulator 7 such as glass, polyimide resin or ceramic is coated on the wiring pattern 5 while attaching of the semiconductor pellet 2 is performed by the use of the insulator 7. Thereby the pattern forming face of a base 1 of a package can effectively be utilized, the base 1 can be made of ceramic of a single layer and production cost can be reduced sharply.

Description

【発明の詳細な説明】 本発明は低コストで製造できる半導体装置に関する。[Detailed description of the invention] The present invention relates to a semiconductor device that can be manufactured at low cost.

従来、集積回路（ＩＣ）や大規模集積回路（ＬＳＩ）の
如き半導体装置のパッケージをセラミック材料で作る場
合、セラミックを複数層重ねた積層パンケージ構造とす
るのが通常である。BACKGROUND ART Conventionally, when a package for a semiconductor device such as an integrated circuit (IC) or a large-scale integrated circuit (LSI) is made from a ceramic material, a laminated package structure in which a plurality of ceramic layers are stacked is usually used.

特に、半導体ペレットの大型化の傾向に伴って、ベレッ
ト付けを行うキャビティーの寸法も太き（しなげればな
らず、したがってリードピンとボンディングポストとの
間の配線がより多層とならざるｔ得なくなる。そのため
、パッケージの製造コストが相当高くなっ℃しまうと（
・う問題点が生じる。In particular, as semiconductor pellets tend to become larger, the dimensions of the cavities in which the pellets are attached also have to be made thicker. As a result, the manufacturing cost of the package becomes considerably high, and when the temperature rises (
・Problems arise.

本発明の目的は、前記した問題点を解消し、低コストで
配線パターンを形成し、半導体装置の製造コストを低減
することＫある。An object of the present invention is to solve the above-mentioned problems, form a wiring pattern at low cost, and reduce the manufacturing cost of a semiconductor device.

この目的を達成するため、本発明は、半導体ペレットの
取付時には半導体ペレットの下側になるベース面にも配
線パターンを形成すると共Ｋ、この配線パターン上に被
着される絶縁材料を用いてペレット付けを行うことを特
徴とするものである。In order to achieve this object, the present invention involves forming a wiring pattern on the base surface which becomes the underside of the semiconductor pellet when the semiconductor pellet is attached, and using an insulating material coated on this wiring pattern to It is characterized by attaching.

以下、本発明を図面に示す実施例にしたがって詳細に説
明する。Hereinafter, the present invention will be explained in detail according to embodiments shown in the drawings.

第１図は本発明による半導体装置の一実施例のパッケー
ジのペースを示す略平面図、第２図は本実施例の断面図
である。FIG. 1 is a schematic plan view showing the packaging of a package of an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a sectional view of this embodiment.

本実施例において、半導体装置のセラミック製パッケー
ジのペース１は単層セラミック構造であり、その中央部
には二点鎖線（第１図）で示す半導体ペレット２が取り
付けられる。In this embodiment, the ceramic package paste 1 of the semiconductor device has a single-layer ceramic structure, and a semiconductor pellet 2 shown by a two-dot chain line (FIG. 1) is attached to the center thereof.

半導体ペレット２の周囲にはワイヤボンディング用のボ
ンディングボスト３が配置されており、該ボンディング
ボスト３は後述のようにワイヤ４で半導体ペレット２の
上のポンディングパッドと電気的に接続される。A bonding post 3 for wire bonding is arranged around the semiconductor pellet 2, and the bonding post 3 is electrically connected to a bonding pad on the semiconductor pellet 2 by a wire 4 as described later.

前記ボンディングボスト３は、半導体ペレット２の内部
回路の出力を取り出すための出力端子用（又は内部回路
に入力ｌ供給する入力端子用）のリードピン６と配線パ
ターン５（一部のみを図示する）を介して電気的に接続
されている。本実施例では、配線パターン５は半導体ペ
レット２を取り付けないベース面領域のみならず、半導
体ペレット２が取り付けられる領域のペース面上にもメ
タライズ層として形成されている。The bonding boss 3 has a lead pin 6 and a wiring pattern 5 (only a part of which is shown) for an output terminal for taking out the output of the internal circuit of the semiconductor pellet 2 (or for an input terminal for supplying input to the internal circuit). electrically connected via. In this embodiment, the wiring pattern 5 is formed as a metallized layer not only on the base surface region where the semiconductor pellet 2 is not attached, but also on the space surface in the region where the semiconductor pellet 2 is attached.

このような配線パターン５の上にもペレット付けを行う
ため、本実施例では、配線パターン５の上にガラス、ポ
リイミド系樹脂あるいはセラミック等の絶縁材料７を被
着すると共Ｋ、この絶縁材料７を用（・て半導体ペレッ
ト２の取り付けをも行うようになって（・る。In order to attach pellets to such a wiring pattern 5, in this embodiment, an insulating material 7 such as glass, polyimide resin, or ceramic is coated on the wiring pattern 5, and this insulating material 7 is Now the semiconductor pellet 2 can be attached using (・).

また、パッケージのペース１の上には、同じくセラミッ
ク材料よりなるキャップ９がガラス等の封止材８Ｖｃよ
って気密封止されて（・る。Further, on top of the package paste 1, a cap 9 also made of a ceramic material is hermetically sealed with a sealing material 8Vc such as glass.

本実施例においては、半導体ペレット２を取り付けるペ
ース面上にも配線パターン５を形成して（・るので、パ
ッケージのペース１のパターン形成面を有効利用でき、
ペース１を単層セラミックで作ることが可能である。し
たがって、パッケージのコスト、ひいては半導体装置自
体の製造コストを低減でき１回路動作の信頼性を向上で
きる。In this embodiment, the wiring pattern 5 is also formed on the paste surface on which the semiconductor pellet 2 is attached, so that the pattern forming surface of the paste 1 of the package can be used effectively.
It is possible to make PACE 1 from a single layer ceramic. Therefore, the cost of the package and, furthermore, the manufacturing cost of the semiconductor device itself can be reduced and the reliability of one circuit operation can be improved.

また、本実施例の場合、半導体ペレット２の取り付けの
ために配線パターン５上に被着される絶縁材料７を用（
・ているので、従来のように金（Ａｕ）材料を用（・て
金−シリコン共晶構造によりペレット付けを行う場合に
比べて大幅にコストを低減できる。In addition, in the case of this embodiment, the insulating material 7 coated on the wiring pattern 5 is used for attaching the semiconductor pellet 2.
・As a result, the cost can be significantly reduced compared to the conventional case of using gold (Au) material and attaching pellets with a gold-silicon eutectic structure.

第３図は本発明の他の１つの実施例を示すパッケージの
ペースの略断面図であり、リードピンは省略されて（・
る本実施例では、パッケージのペース１の中央部のペレ
ット取付部を斜面１１付きの凹部１０として構成し、こ
の凹部１０の底面および斜面１１上に配線パターン５を
メタライズ層により形成したものである。本実施例にお
（・ても、ペースｌのペレット取付領゛域上にも配線パ
ターン５が形成され、かつ該配線パターン５上に被着さ
れる絶縁材料７でペレット付けを行って−・るので、半
導体装置の製造コストに低減できる上に、ワイヤボンデ
ィングをより確実かつ良好に行うことができる。FIG. 3 is a schematic cross-sectional view of a package pace showing another embodiment of the present invention, with lead pins omitted (.
In this embodiment, the pellet attachment part at the center of the package paste 1 is configured as a recess 10 with a slope 11, and a wiring pattern 5 is formed on the bottom surface of the recess 10 and on the slope 11 using a metallized layer. . In this embodiment, the wiring pattern 5 is also formed on the pellet attachment area of the paste 1, and the pellet attachment is carried out using the insulating material 7 coated on the wiring pattern 5. Therefore, the manufacturing cost of the semiconductor device can be reduced, and wire bonding can be performed more reliably and better.

また、第３図のバクケージ構造にお（・て、キャップ９
を二点鎖線で示す如く平板状セラミックで構成すること
により、さらに強固な気密封止を得ることが可能となる
。In addition, the cap 9 is attached to the back cage structure shown in Figure 3.
By constructing it with a flat ceramic as shown by the two-dot chain line, it becomes possible to obtain an even stronger hermetic seal.

第４図は本発明の他の１つの実施例を示すパッケージの
ペースの略平面図である。本実施例では。FIG. 4 is a schematic plan view of a package pace showing another embodiment of the present invention. In this example.

パッケージのペースが下層１人と上層ＩＢの２層セラミ
ック構造であるが、半導体ペレット２の取付領域のペー
ス面上にも配線パターン５が形成されて（・る。したが
って、配線およびペレット付けが前記両実施例と同様に
低コストかつ容易であり、微細メタライズ加工が不要と
なり、インダクタンス成分の減少による回路の動作安定
化ｌ得ることが可能である。Although the package has a two-layer ceramic structure with one lower layer and one upper layer IB, a wiring pattern 5 is also formed on the surface of the packaging area in which the semiconductor pellet 2 is attached. Like both embodiments, it is low cost and easy, eliminates the need for fine metallization, and stabilizes the operation of the circuit by reducing the inductance component.

以上説明したように５本発明によれば、半導体装置の製
造コストを大幅に低減できる。As explained above, according to the present invention, manufacturing costs of semiconductor devices can be significantly reduced.

【図面の簡単な説明】 第１図は本発明による半導体装置の一実施例におけるパ
ンケージのペースの略平面図。 第２図は本実施例の断面図、 第３図は本発明の他の１つの実施例におけるパッケージ
のペースの略断面図、 第４図は本発明のさらに他の１つの実施例におけるパッ
ケージのペースの略平面図である。 １・・・パッケージのペース、２・・・半導体ペレット
、３・・・ボンディングポスト、４・・・ワイヤ、５・
・・配線パターン、６・・・リードビン、７・・・絶縁
材料、８・・・封止材、９・・・キャップ。 第　　１　　図 第４図BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic plan view of a pancage space in an embodiment of a semiconductor device according to the present invention. FIG. 2 is a sectional view of this embodiment, FIG. 3 is a schematic sectional view of a package pace in another embodiment of the present invention, and FIG. 4 is a schematic sectional view of a package in another embodiment of the present invention. FIG. 3 is a schematic plan view of the pace. DESCRIPTION OF SYMBOLS 1... Package pace, 2... Semiconductor pellet, 3... Bonding post, 4... Wire, 5...
... Wiring pattern, 6... Lead bin, 7... Insulating material, 8... Sealing material, 9... Cap. Figure 1 Figure 4

Claims (1)

【特許請求の範囲】 １、パッケージのベース上に半導体ペレットを取り付け
てなる半導体装置において、半導体ペレットを取り付け
るベース面上にも配線パターンを形成し、この配線パタ
ーン上に被着した絶縁材料により半導体ペレットを取り
付けたことを特徴とする半導体装置。 ２、パッケージのベースがセラミックの単層構造よりな
ることを特徴とする特許請求の範囲第１項記載の半導体
装置。 ３、パッケージのベースのペレット取付部が凹んでいる
ことを特徴とする特許請求の範囲第２項記載の半導体装
置。[Claims] 1. In a semiconductor device in which a semiconductor pellet is attached to the base of a package, a wiring pattern is also formed on the base surface to which the semiconductor pellet is attached, and the semiconductor is A semiconductor device characterized by having a pellet attached. 2. The semiconductor device according to claim 1, wherein the base of the package is made of a ceramic single-layer structure. 3. The semiconductor device according to claim 2, wherein the pellet mounting portion of the base of the package is recessed.
JP1107640A 1989-04-28 1989-04-28 Semiconductor device Pending JPH01315170A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1107640A JPH01315170A (en) 1989-04-28 1989-04-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1107640A JPH01315170A (en) 1989-04-28 1989-04-28 Semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP57075348A Division JPS58192354A (en) 1982-05-07 1982-05-07 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH01315170A true JPH01315170A (en) 1989-12-20

Family

ID=14464317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1107640A Pending JPH01315170A (en) 1989-04-28 1989-04-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH01315170A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5775348A (en) * 1980-10-28 1982-05-11 Casio Comput Co Ltd Space signal generator
JPS58192354A (en) * 1982-05-07 1983-11-09 Hitachi Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5775348A (en) * 1980-10-28 1982-05-11 Casio Comput Co Ltd Space signal generator
JPS58192354A (en) * 1982-05-07 1983-11-09 Hitachi Ltd Semiconductor device

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