JPH01312837A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01312837A JPH01312837A JP14431388A JP14431388A JPH01312837A JP H01312837 A JPH01312837 A JP H01312837A JP 14431388 A JP14431388 A JP 14431388A JP 14431388 A JP14431388 A JP 14431388A JP H01312837 A JPH01312837 A JP H01312837A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- integrated circuit
- film
- semiconductor substrate
- nitride film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 150000004767 nitrides Chemical class 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000011347 resin Substances 0.000 abstract description 7
- 229920005989 resin Polymers 0.000 abstract description 7
- 230000035515 penetration Effects 0.000 abstract 2
- 230000001627 detrimental effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 10
- 230000002411 adverse Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000008280 blood Substances 0.000 description 1
- 210000004369 blood Anatomy 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 210000003734 kidney Anatomy 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置、特に半導体基板上に形成された
集積回路を保護するパッシベーション膜の構造に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a structure of a passivation film that protects a semiconductor device, particularly an integrated circuit formed on a semiconductor substrate.
従来より半導体デバイスへのコンタミネーション等の侵
入を防止し、デバイスの信頼性を高めるために、半導体
デバイスの表面上にバッジベージコン膜を形成している
。このパッシベーション膜はウェハ状態での最終工程に
おいて形成されるものであり、このパッシベーション膜
によりパッケージング工程および使用環境下において半
導体デバイスを閤械的、化学的に保護している。このよ
うなパッシベーション膜としては、従来より窒化膜と酸
化膜とが一般的に用いられている。BACKGROUND ART Conventionally, a badge-containing film has been formed on the surface of a semiconductor device in order to prevent contamination from entering the semiconductor device and improve the reliability of the device. This passivation film is formed in the final process in the wafer state, and mechanically and chemically protects the semiconductor device during the packaging process and usage environment. Conventionally, nitride films and oxide films have been commonly used as such passivation films.
しかしながら、窒化膜のみをパッシベーション膜として
採用した場合あるいは酸化膜のみをパッシベーション膜
として採用した場合には、それぞれ以Ｆのような欠点を
有している。However, when only a nitride film is used as a passivation film or when only an oxide film is used as a passivation film, each has the following drawbacks.
すなわち窒化膜を採用した場合には１．窒化膜の誘電率
が比較的高いため、半導体デバイスの縮小化に伴い配線
間の寄生容量が大きくなる等によりデバイスの特性に悪
影響を及ぼす。また、窒化膜を形成した際、窒化膜中に
比較的大きな残留ストレスが発生する。そして、このス
トレスが半導体デバイスに作用するので、上記と同様に
デバイスの特性に悪影響を及ぼす。In other words, if a nitride film is used, 1. Since the dielectric constant of the nitride film is relatively high, parasitic capacitance between interconnections increases as semiconductor devices are downsized, which adversely affects device characteristics. Further, when a nitride film is formed, a relatively large residual stress is generated in the nitride film. Since this stress acts on the semiconductor device, it adversely affects the characteristics of the device in the same manner as above.
一方、酸化膜を採用した場合には、酸化膜は、窒化膜に
比べその誘電率は低くまた膜ス１−レスも小ざいことか
ら、誘電率と膜ストレスの観点では窒化膜よりも有効で
はあるが、耐湿性や外部からのコンタミネーシ」ン（Ｎ
ａ等）に対するバリア効！！！等は、窒化膜に比べ劣る
。したがって、バッジベージ〕ン膜を酸化膜のみで構成
した場合にも、半導体Ｙバイスの信頼性が低下するとい
う問題がある。On the other hand, if an oxide film is used, it is less effective than a nitride film in terms of dielectric constant and film stress because the oxide film has a lower dielectric constant and a smaller film stress than a nitride film. However, moisture resistance and external contamination (N
Barrier effect against a)! ! ! etc. are inferior to nitride films. Therefore, even when the badge-based film is composed of only an oxide film, there is a problem in that the reliability of the semiconductor Y-vice is reduced.
そこで゛、第４図に示すように、バッジベージコン膜を
酸化膜と窒化膜の二層構成にすることが提案されている
。第４図はこの提案例にかかる半導体装置を示づ図Ｃ゛
あり、パッケージングされた半導体装ＩＮの一部断面を
示すらのである。同図に示すように、￥導体１．を根１
上に形成された集積回路部２を覆うように集積回路部２
上から半導体基板１上にかけて酸化膜３ａが形成されて
おり、さらにこの酸化膜３ａ上に窒化膜３ｂが形成され
ている。そして、半導体基板１．酎化模３ａおよび窒化
膜３ｂを覆うようにパッケージ樹脂４が形成されている
。なお、説明−トの配慮から同図には、集積回路部２と
してフィールド酸化膜２ａ９層間絶縁膜２［）、アルミ
配線２Ｃのみを明示している。Therefore, as shown in FIG. 4, it has been proposed that the badge-container film has a two-layer structure of an oxide film and a nitride film. FIG. 4 is a diagram C showing a semiconductor device according to this proposed example, and shows a partial cross section of a packaged semiconductor device IN. As shown in the figure, conductor 1. root 1
The integrated circuit part 2 is formed so as to cover the integrated circuit part 2 formed above.
An oxide film 3a is formed from above onto the semiconductor substrate 1, and a nitride film 3b is further formed on this oxide film 3a. Then, semiconductor substrate 1. A package resin 4 is formed to cover the nitride film 3a and the nitride film 3b. For ease of explanation, only the field oxide film 2a9, interlayer insulating film 2[), and aluminum wiring 2C are clearly shown as the integrated circuit portion 2 in the figure.
」−記のようにバッジベージコン膜３を酸化膜３ａと窒
化膜３ｂの２層橋造とする方法の概要は以下のとおりで
ある。まず、半導体基板１上に集積回路部２を形成した
後、全面に酸化層（図示省略）を形成する。そして、所
定のパターンニングが施されたマスク（図示省略）を用
い（゛適当に■ツブーングすることにより酸化膜３ａを
形成する。その（Ｑ、全面に窒化層（図示省略）を形成
し、上記と同一のマスクを用いて適当にエツチングする
ことにより窒化膜３ｂを形成づる。The outline of the method for forming the badge-basecon film 3 into a two-layer bridge structure of an oxide film 3a and a nitride film 3b as described in ``-'' is as follows. First, after forming the integrated circuit section 2 on the semiconductor substrate 1, an oxide layer (not shown) is formed on the entire surface. Then, using a mask (not shown) with a predetermined pattern, an oxide film 3a is formed by appropriately punching.A nitride layer (not shown) is formed on the entire surface, and then A nitride film 3b is formed by appropriate etching using the same mask as described above.
（発明が解決しようとする課題）
提案にかかる半導体装置は以上のように構成されている
ので、パッケージ樹脂４と酸化膜３ａとが）３する領域
５が形成されており、この領域５を介してパッケージ樹
脂４中に含まれているＮａやＦ（２ｏが酸化膜３ａに侵
入し、さらに酸化膜３ａを通過して集積回路部２にＦ）
入する。そのため、半導体デバイスの信頼性が低下する
という問題があった。(Problem to be Solved by the Invention) Since the proposed semiconductor device is configured as described above, a region 5 is formed where the package resin 4 and the oxide film 3a) Na and F (2O) contained in the package resin 4 penetrate into the oxide film 3a, and further pass through the oxide film 3a and enter the integrated circuit section 2.
Enter. Therefore, there was a problem in that the reliability of the semiconductor device decreased.
この発明は上記の課題を解消するためになされたもので
、集積回路部の特性トに悪影響を及ぼすことなく外部か
らのＮａやｌ−１２０等の侵入を防用することかでき、
信頼性の高い半導体装置を提供づることを目的とする。This invention was made to solve the above problems, and can prevent Na, l-120, etc. from entering from the outside without adversely affecting the characteristics of the integrated circuit section.
The purpose is to provide highly reliable semiconductor devices.
この発明は、半導体基板と、前記半導体基板上に形成さ
れた集積回路部と、前記集積回路部を覆うように前記束
積回路部上から前記半導体基板上にかけて形成された酸
化膜と、前記酸化膜を覆うように前記酸化膜上から前記
半導体基板上にｈ目Ｊで形成された窒化膜とを備えてい
る。The present invention includes a semiconductor substrate, an integrated circuit section formed on the semiconductor substrate, an oxide film formed from above the integrated circuit section to the semiconductor substrate so as to cover the integrated circuit section, and the oxide film formed on the semiconductor substrate. and a nitride film formed from the oxide film to the semiconductor substrate in h-th order J so as to cover the film.
この発明における半導体装置は、酸化膜により窒化膜が
集積回路部に及ぼす悪影響を防止する一方、前記窒化膜
により外部から前記集積回路部にＮａや）」２０等が侵
入するのを防止する。In the semiconductor device of the present invention, the oxide film prevents the adverse effects of the nitride film on the integrated circuit portion, and the nitride film also prevents Na, etc. from entering the integrated circuit portion from the outside.
第１図はこの発明にかかる半導体装置の一実施例を示す
断面図である。同図に示す実施例が第４図に示す提案例
と大きく異なる点は、本実施例において窒化膜３ｂが、
酸化膜３ａを覆うように、酸化膜３ａのみならず半導体
基板１上にも一定の幅ｄで形成され、パッケージ樹脂４
と酸化膜３ａとが直接）多重る領域がないことである。FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention. The major difference between the embodiment shown in the figure and the proposed example shown in FIG. 4 is that in this embodiment, the nitride film 3b is
A package resin 4 is formed not only on the oxide film 3a but also on the semiconductor substrate 1 with a constant width d so as to cover the oxide film 3a.
There is no region where the oxide film 3a and the oxide film 3a directly overlap.
モの他の構成については提案例と同一・である。The other configurations of the module are the same as the proposed example.
次に、第１図に示す半導体装置の製造方法について第２
図および第３図を参照しつつ以下に説明づる。まず、半
導体基板１上に集積回路部２を形成した後、仝而に酸化
層（図示省略）を形成する。Next, we will discuss the second method for manufacturing the semiconductor device shown in FIG.
This will be explained below with reference to the figures and FIG. First, after forming the integrated circuit section 2 on the semiconductor substrate 1, an oxide layer (not shown) is formed.
そして、所定のパターンニングが施されたマスク６を前
記酸化層上に形成する。その後、そのマスク６を用いて
そのパターンに応じて部分的に前記酸化層をエツチング
して第２図に示す酸化膜３ａを形成する。Then, a mask 6 with a predetermined pattern is formed on the oxide layer. Then, using the mask 6, the oxide layer is partially etched according to the pattern to form the oxide film 3a shown in FIG.
次に、マスク６を除去した後、全面に窒化層（図示省略
）を形成する。そして、所定のパターンニングが施され
たマスク７を前記窒化層上に形成し、そのマスク７を用
いてそのパターンに応じて部分的に前記省化腎を−［・
ｔｆングし７Ｃ第３図に示す一窒化Ｉｉ々３ｂを形成す
る３、その↑り、マスク７を除ムすることによりつ丁−
凸状態での−Ｌ稈を終了（Ｊる。Next, after removing the mask 6, a nitride layer (not shown) is formed on the entire surface. Then, a mask 7 with a predetermined pattern is formed on the nitride layer, and the mask 7 is used to partially cover the reduced kidney according to the pattern.
Then, by removing the mask 7, the mononitride layer 3b shown in FIG. 3 is formed.
Finish -L culm in convex state (J).
そして、アセンブリ１稈におい（、スクライブ−ｉイン
８に沿って切断し、ｆツブ状態にするａての後、パッケ
ージングを行い、第１図に示づ半導体装置を得る。Then, the assembly is cut along the scribe-i-in 8 and subjected to packaging to obtain the semiconductor device shown in FIG. 1.
以−Ｕのように二、半導体装置を構ｆ戊することにより
、酸化膜３ａど窒化膜３ｂの２）：４構造による利点を
保ｆｊシた状態で、バッタージＰＡ脂４中に含まれてい
るＮａやト（２０等の集積回路部２への侵入を確実に防
止りることがで、！る。寸なわら、集積回路部２は窒化
膜３ｂと直接接しくおらず、酸化１１ｕ３ａと接してい
るのぐ、窒化膜中の残留ストレスが集積回路部２に５え
る影響を酸化膜３ａにより８１止できるとともに、比誘
電率のような小さな酸化膜３ａにより配線間の寄生容Φ
を小さく抑えることができる。また、パッケージ樹脂４
と酸化膜３ａどがｖ１接接しでいる領域はないので、パ
ッケージ樹脂４中に含まれるＮａやＨ２０Ｗが１！Ｔｈ
積回路部２に侵入しようとしてｂ、その浸入は窒化膜３
ｂにより■庄される。By configuring the semiconductor device as shown in U, the advantages of the 2):4 structure of the oxide film 3a and nitride film 3b are maintained, while the components contained in the batterage PA fat 4 are It is possible to reliably prevent Na, T(20, etc.) from entering the integrated circuit portion 2. However, the integrated circuit portion 2 is not in direct contact with the nitride film 3b, and oxidized 11u3a and The oxide film 3a can prevent the influence of residual stress in the nitride film on the integrated circuit part 2 when it is in contact with the wiring, and the parasitic capacitance Φ between the wirings can be reduced by the oxide film 3a having a small dielectric constant.
can be kept small. In addition, package resin 4
Since there is no region where the oxide film 3a and the oxide film 3a are in contact with v1, the amount of Na and H20W contained in the package resin 4 is 1! Th
In an attempt to invade the integrated circuit part 2 b, the intrusion is caused by the nitride film 3
■Sho is carried out by b.
なお、￥導体基板１トに形成される窒化膜３ｂの幅ｄ
（第１図）は少なくども５μｒｒｔ以）Ｘあればよく、
好ましくは１０１ノｍ以上で・ある１、〔発明の効果〕
以１−のＪ″）に、この発明によれば、半導体）、を楡
トに形成された集積回路部の仝血を酸化膜にＪ：りでい
、さらにこの酸化膜の仝而を窒化膜によりマ′うように
構成したので、前記集積回路部の待ゼ［Ｉ−に悪影響を
及ばずことなく外部より前記集積回路部にＮａやＨ２Ｏ
等の浸入を防止でさ、信頼性の高い主導体装置を提供づ
ることかぐきる効果がある。Note that the width d of the nitride film 3b formed on the conductive substrate 1t
(Figure 1) should be at least 5 μrrt)
Preferably, the thickness is 101 nm or more. 1. [Effects of the Invention] According to the present invention, the semiconductor) is formed on the elm by removing the blood of the integrated circuit portion from the oxide film. In addition, since this oxide film is covered by a nitride film, it is possible to remove the integrated circuit part from the outside without adversely affecting the waiting state [I-] of the integrated circuit part. Na and H2O
This has the effect of providing a highly reliable main conductor device.
第１図はこの発明にかかる半導体装置を示す断面図、第
２図および第３図は第１図に示す半導体装置の製造方法
を示す図、第４図は提案例における半導体装置を示す断
面図である。
図において、１は半導体基板、２は集積回路部、３ａは
酸化膜、３ｂは窒化膜である。
なお、各図中同一符号は同一または相当部分を示す。FIG. 1 is a sectional view showing a semiconductor device according to the present invention, FIGS. 2 and 3 are views showing a method for manufacturing the semiconductor device shown in FIG. 1, and FIG. 4 is a sectional view showing a semiconductor device in a proposed example. It is. In the figure, 1 is a semiconductor substrate, 2 is an integrated circuit section, 3a is an oxide film, and 3b is a nitride film. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
回路部を覆うように、前記集積回路部上から前記半導体
基板上にかけて形成された酸化膜と、 前記酸化膜を覆うように、前記酸化膜上から前記半導体
基板上にかけて形成された窒化膜とを備えたことを特徴
とする半導体装置。(1) a semiconductor substrate; an integrated circuit section formed on the semiconductor substrate; an oxide film formed from above the integrated circuit section to above the semiconductor substrate so as to cover the integrated circuit section; and the oxide film. and a nitride film formed from above the oxide film to above the semiconductor substrate so as to cover the oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14431388A JPH01312837A (en) | 1988-06-10 | 1988-06-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14431388A JPH01312837A (en) | 1988-06-10 | 1988-06-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01312837A true JPH01312837A (en) | 1989-12-18 |
Family
ID=15359184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14431388A Pending JPH01312837A (en) | 1988-06-10 | 1988-06-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01312837A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5742094A (en) * | 1993-01-25 | 1998-04-21 | Intel Corporation | Sealed semiconductor chip |
-
1988
- 1988-06-10 JP JP14431388A patent/JPH01312837A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5742094A (en) * | 1993-01-25 | 1998-04-21 | Intel Corporation | Sealed semiconductor chip |
| US5856705A (en) * | 1993-01-25 | 1999-01-05 | Intel Corporation | Sealed semiconductor chip and process for fabricating sealed semiconductor chip |
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