JPH0131210B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a display device, and in particular, it is possible to easily convert a signal output to a monitor into a hard copy signal when copying the contents of a display screen to a hard copy device. This invention relates to a video control method that allows monitor display to be used without stopping by adding a circuit.

[Prior art and problems]

For example, when making a hard copy of the display screen of a display device such as a CRT display device, the frequency per dot is very high because the display device uses raster scanning to display signals on the display screen. fast. For example, 50.8cm
(20 inch) CRT operates at a video frequency of about 40MHz.

Therefore, it is not easy to use the video signal sent to the display section as it is for a printer because it requires a special high-speed IC.

Therefore, conventionally, as shown in FIG. 1, display data from a screen RAM (random access memory) 1 holding a display screen is transmitted to a video control section 2, and a separate oscillator 3 is used to generate, for example, a 40MHz video signal.・Generate clock VDCK. And if you don't make a hard copy,
Since the copy operation signal CPY is "0", inverter 4 outputs "1", and AND gates 5 and 11
is turned on, and the video clock VDCK output from the oscillator 3 is also transmitted to the first counter 9 and the video control section 2 via the AND gate 5 and the OR gate 8. As a result, the first counter 9 outputs the horizontal synchronizing signal HS, and this horizontal synchronizing signal HS is also transmitted to the second counter 10, which outputs the vertical synchronizing signal VS. In addition, the video control unit 2 uses the video clock VDCK transmitted to the video control unit 2 to convert the display data of the screen RAM 1 to this 40MHz clock.
The signal is read out by the video clock VDCK, and is output from the AND gate 11 as a display video signal to the display unit along with the horizontal synchronizing signal HS, vertical synchronizing signal VS, etc. In this way, this display video signal is outputted on the display surface of the display unit, and is displayed on a monitor, for example. Also, oscillator 3
The output of the frequency divider 6 is also transmitted to the frequency divider 6, and is divided into, for example, 20MHz, but since the copy operation signal CPY is "0", the AND gate 7 is off, and the output of the frequency divider 6 is divided into the AND gate 7. There is no output.

By the way, when copying the contents of the display screen displayed on the monitor to a hard copy device such as a printer, a copy operation signal is sent to the inverter 4.
Set CPY to "1". As a result, the AND gate 7 is turned on, and the inverter 4 is turned on.
outputs “0”, so AND gates 5 and 11
is turned off. Then, since the AND gate 7 is turned on, the 20MHz frequency-divided video clock generated from the frequency divider 6 is transmitted from the OR gate 8 to the video control section 2, and this frequency-divided video clock is then transmitted to the video control unit 2 from the OR gate 8.・The display data of the screen RAM 1 is read out by the video control unit 2 by the clock, and the above-mentioned OR
The signal is sent to a hard copy device together with the video clock output from gate 8, and a hard copy is thereby performed.

By the way, when this hard copy is being executed, the AND gate 11 is in the off state, so the display video signal is not transmitted to the display section, and therefore, the monitor display is not performed on the display section during hard copying. Therefore, during the hard copy operation, the operator is unable to determine whether or not what is actually copied is the same as what is displayed, which causes a sense of uneasiness. The reason why the monitor display is stopped during hard copying is that the video clock during hard copying is frequency-divided and slow as described above, so the horizontal and vertical synchronization signals are also slow, making it difficult to display a normal display image. This is because it is difficult to see.

[Purpose of the invention]

An object of the present invention is to copy the contents of a display screen to a hard copy device and use the signal output from the video control section to the monitor as it is as a hard copy signal, since the speed of the video signal is fast.・In order to improve the drawback that when copying, the output of video signals, etc. was reduced to half the speed and the monitor display had to be stopped during hard copying. An object of the present invention is to provide a video control method that does not stop display.

[Structure of the invention]

In order to achieve this object, the video control method of the present invention uses a video signal that is output from the video control section to the monitor as a hard copy signal when copying the contents of the display screen with a hard copy device. The control method includes an odd/even number indicating means for indicating whether the video signal is an odd numbered dot or an even numbered dot, an odd/even frame discrimination control means for determining whether the frame is an odd numbered dot or an even numbered dot of the video signal, and hardware. - video signal output means for outputting a video signal for copying, a first gate and a second gate controlled by the output signal of the odd-even frame discrimination control means, and a new New video clock output means for outputting a video clock signal is provided, the video clock is controlled based on the output signal obtained from the first gate or the second gate, and the new video clock signal is output from the new video clock output means. The present invention is characterized in that the new video clock signal is used to control the output of the hard copy video signal from the video signal output means.

[Embodiments of the invention]

An embodiment of the present invention will be described based on FIGS. 2 and 3.

FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of its operation.

In the figure, the same reference numerals as in other figures indicate the same parts, and 20
is a first counter, 21 is a second counter, 22 is a flip-flop for odd/even dot/frame discrimination control (hereinafter referred to as odd/even frame discrimination control FF);
23 is a video signal register, 24 is an AND gate, 25 is an OR gate, 26 is an AND gate, and 27 is an inverter.

The first counter 20, like the first counter 9 in FIG.
The first counter 20 counts the video clock VDCK and outputs the horizontal synchronizing signal HS shown in FIG. is output and transmitted to the AND gate 24 and the inverter 27. That is, as shown in Figure 3A, the video clock VDCK is 1, 2, 3, 4.
..., the least significant bit of the first counter 20 is first "0", then "1", then "0", etc.
It changes alternately. Therefore the video clock
When VDCK is an odd number such as 1, 3, etc., the least significant bit of this first counter 20 is "0", 2, 4.
. . . when it is an even numbered dot, it outputs "1", and it also functions as an odd/even number indicating means for indicating the odd numbered dot and the even numbered dot of the video signal.

The second counter 21, like the second counter 10 in FIG. 1, counts the horizontal synchronization signal HS output from the first counter 20 and outputs the vertical synchronization signal VS. This vertical synchronizing signal VS is not only output to the monitor display section but also transmitted to the odd/even frame discrimination control FF 22.

The odd-even frame discrimination control FF 22 outputs an odd-even dot/frame discrimination signal Q, which is a control signal for determining whether to extract an odd-numbered video clock or an even-numbered video clock from one screen frame. It is something that
For example, it is made up of JKFF. Each time the vertical synchronizing signal VS output from the second counter 7 is input to the input terminal of the odd-even frame discrimination control FF 22, the "1" and "0" states of the output are inverted.

Therefore, as shown in Figure 3 D, the odd-even dots
When the frame discrimination signal Q is at L level, it is at H level, and AND gate 24 is off, but AND gate 28 is on. At this time, when video clocks 1, 2, 3, etc. are input to the first counter 20 as shown in FIG. 3A,
When odd-numbered video clocks 1, 3, 5, etc. are input, the output of the least significant bit of the first counter 20 is "0" as described above, and this is transmitted to the inverter 27 and becomes "1". Because, and
From the gate 28, odd-numbered video clocks 1, 3, 5, . . . as shown between T ₁ and T ₂ in FIG.
A signal corresponding to 3,5...
...is output. When the horizontal scanning of the screen is finished and the vertical synchronizing signal VS is output from the second counter 21, this vertical synchronizing signal VS is also applied to the odd/even frame discrimination control FF 22, its output is inverted, and this time it becomes H Since the odd/even dot frame discrimination signal Q of the level is applied to the AND gate 24, the AND gate 24 is turned on, but since the L level is applied to the AND gate 28, it is turned off. Therefore, this time, Figure 3
As shown from _T2 onwards, even-numbered video clocks 2, 4, 6, . . . are output from the AND gate 26. In this way, a new 20MHz video signal whose frequency is divided in half by AND gate 26 is generated.
A clock signal is output.

The video signal register 23 is a video signal output means, and has a 1-bit configuration, for example. In the example shown in FIG. 3, odd-numbered video signals are sequentially output from the video signal register 23 by odd-numbered video clocks 1, 3, 5, . . . for each horizontal scanning line of one frame. After the next vertical synchronizing signal is output, the remaining half of the video signal is outputted by the even-numbered video clocks 2, 4, . . . for each horizontal scanning line. In this way, from the screen RAM 1 at least twice the video control unit 2
The oscillator 3 outputs a video signal.
A new video clock of 20 MHz with a frequency of 1/2 of 40 MHz from the video signal register 23 allows the entire video signal to be output from the video signal register 23. Therefore, the video signal output by the odd-numbered video clock and the video signal output by the even-numbered video clock output in this way are integrated into one by the buffer memory of the hard copy device.
A full hard copy video signal of the frame can be obtained.

Next, the operation of the video control system shown in FIG. 2 will be explained.

The oscillator 3 outputs 40 MHz video clocks VDCK1, 2, 3, . . . as shown in FIG.

As a result, the first counter 20 outputs a horizontal synchronizing signal HS as shown in FIG. 3C, and the second counter 21 outputs a vertical synchronizing signal VS as shown in FIG.
is output, and from the video control unit 2, the screen
The display video signal stored in RAM1 is output. These display video signals and horizontal synchronization signals
HS, vertical synchronization signals, etc. are sent to the monitor, and the data output from the screen RAM 1 is displayed.

By the way, the second counter 2 shown in FIG.
Since the output of 1 is applied to the input terminal of the FF for odd-even frame discrimination control, for example, the time shown in Fig. 3
In T ₁ , the Q of this FF22 for odd/even frame discrimination control is
The terminal outputs L level, and the terminal outputs H level. Therefore, AND gate 24 is turned off and AND gate 28 is turned on. At this time, the output of the least significant bit of the first counter 20 is
Since the video clock VDCK is "0" when it is an odd number and "1" when it is an even number, the inverter 27 outputs "1" when it is an odd number. Therefore, after time _T1 in FIG. 3, when the video clock VDCK is an odd number, AND gate 28, OR gate 25, and AND gate 26 are activated.
From there, a new video clock is output as shown in FIG. This new video clock uses oscillator 3
This new video clock is half the frequency of the 40MHz video clock output from the video signal register 23 when the data from the screen RAM 1 output from the video control section 2 is an odd numbered video clock. It will be set to . In this way, only odd-numbered data is set in the video signal register 23 in one screen frame after time _T1 . This is then sent to the hard copy device along with a new video clock and an odd/even dot frame discrimination signal.

When the vertical synchronization signal VS is output from the second counter 21 at time T ₂ in FIG. 3, the output of the odd/even frame discrimination control FF 22 is thereby inverted.
This time, as shown in FIG. 3D, the Q terminal becomes H level and the terminal becomes L level. Therefore, AND gate 24 is turned on and AND gate 28 is turned off. As a result, when the least significant bit of the first counter 20 becomes "1" and the video clock VDCK is an even number, the AND gate 24 and the OR gate 2 are activated.
5. A new video clock is output from the AND gate 26 as shown in FIG. If it is an even number, it will be set in the video signal register 23 and will also be sent to the hard copy device.

In this way, the displayed screen can be hard-copied without stopping the monitor screen display.

〔Effect of the invention〕

According to the present invention, it is possible to make a hard copy of a monitor display while looking at it using extremely simple means.

[Brief explanation of drawings]

FIG. 1 is a conventional video control system, FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of its operation. In the figure, 1 is the screen RAM, 2 is the video control unit, and 3
is an oscillator, 4 is an inverter, 5 is an AND gate, 6 is a frequency divider, 7 is an AND gate, 8 is an OR gate, 9 is a first counter, 10 is a second counter, 11 is an AND gate, 20 is a first counter, 21 is a second counter, 22 is a flip-flop for odd/even dot/frame discrimination control;
3 is a video signal register, 24 is an AND gate, 25 is an OR gate, 26 is an AND gate, 27 is an inverter, and 28 is an AND gate.

Claims (1)

[Claims] 1. In a video control method in which a video signal output from a video control unit to a monitor is used as a hard copy signal when copying the contents of a display screen with a hard copy device, an odd/even number indicating means 20 for indicating whether a frame is an odd numbered dot or an even numbered dot, and an odd/even frame discrimination control means 22 for determining whether a frame is an odd numbered dot or an even numbered dot of the video signal.
a video signal output means 23 for outputting a video signal for hard copy; a first gate 24 and a second gate 28 controlled by the output signal of the odd/even frame discrimination control means 22; A new video clock output means 26 is provided for outputting a new video clock signal obtained from the output of the second gate 28, and the video clock is controlled based on the output signal obtained from the first gate 24 or the second gate 28. A new video clock signal is obtained from the new video clock output means 26, and the output of the video signal for hard copy is controlled from the video signal output means 23 using this new video clock signal. Video control method.