JPH01311639A - Receiver for spread spectrum signal - Google Patents

Abstract

PURPOSE:To accurately and stably perform a pull-in operation with simple circuit constitution by forming a phase difference detection circuit used in a timing synchronous circuit in specific circuit constitution. CONSTITUTION:The phase difference detection circuit 6 in the timing synchronous circuit is constituted of delay lines 15 and 16 having the same delay time, a comparator 17 to compare the voltage of the output (p) of the delay line 16 with that of input (h) from an envelope detector, a comparator 18 to compare the output voltage (n) of the delay line 15 with a threshold voltage, an AND gate 10, a counter 20 which repeats counting with the cycle of clock input 24, a ROM21 to perform the code conversion of the output of the counter 20, a register 22 to perform the sampling of the output (u) of the ROM21 with pulse output (s) from the AND gate 19, and a D/A converter 23. In such a way, it is possible to perform pull-in to a synchronous state stably and accurately with simple circuit constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention relates to a receiving device using a matched filter in a direct spread spectrum communication system, which is a type of spread spectrum communication system. In particular, it concerns the synchronous circuit.

(Prior art and its problems) In the spread spectrum communication system, two-phase phase modulation (P
In the direct sequence method using SK), the carrier wave is binary phase modulated with information data, and then this is binary phase modulated with a pseudorandom code, which has a faster signal transmission rate than the data, and then transmitted. The carrier wave is subjected to two-phase phase modulation using the output obtained by multiplying the signal and the data, and is transmitted as a spread signal.

Figure 2 a to d are examples of waveforms on the transmitting side, where a is information data to be transmitted, b is a pseudorandom code, C is the product of both a and b, and d is two-phase phase modulated with the product output C. This is a spread signal. Here, a case is shown in which the length of one pin of the information data a is equal to the length of one period of the pseudorandom code.

FIG. 1 is a side view of the configuration of a demodulating section of a receiving apparatus that receives a spread signal. Although there are various demodulation methods, a circuit of a demodulation section using a matched filter 1 in an intermediate frequency band is shown.

2-g in FIG. 2 show examples of waveforms of each part of the reception demodulation section in FIG. 1. The matched filter 1 can be easily realized using, for example, a surface acoustic wave element, and when a desired received signal is input to it, it has a correlation peak at each period of the pseudo-random code, as shown in waveform e. output.

The receiving device demodulates data in synchronization with the position of this peak. That is, when the output e of the matched filter 1 is input to the synchronous detector 2 and synchronously detected using the carrier wave regenerated by the carrier wave regeneration circuit 4, an output having a waveform f is obtained. A demodulated output g is obtained by sampling this output f in the sampling determination circuit 3 at the peak position and determining whether it is positive or negative. By sampling at the peak position in this manner, it is possible to determine the S/N in a state where the S/N is improved by the ratio of the code rate of the pseudorandom code to the data transmission rate, that is, the spreading gain of the spread spectrum, relative to the input.

A timing synchronization circuit 27 is a synchronization circuit for adjusting the sampling timing to the position of this peak, which is composed of a circuit from an envelope detector 5 to a clock generation circuit 9.
It is. The output e of the matched filter 1 is the envelope detector 5
The phase difference between the detected output and the output clock of the clock generation circuit 9 is determined by the phase difference detection circuit 6, and the LPF
A voltage controlled oscillator (■C0
) 8 to match the timing of the output clock of the clock generation circuit 9 obtained from the output of this vcos with the peak position of the input signal.

FIG. 3 shows an example of the circuit configuration of the phase difference detection circuit 6 used in the timing synchronization circuit 27 in FIG. 2 analog gates 1
This is the input terminal of the gate pulse that controls the opening and closing of 0.11.
This is an input from the clock generation circuit 9.

FIG. 4 shows the waveforms of each part of the circuit in FIG. 3, where h is the input from the envelope detector 5, ! +J is the gate pulse input from 13.14, k and f are the analog gates) 10°11 output, and m is the output of the subtraction circuit 12. As shown in the figure, if there is a peak in the output from the envelope detector 5 at the switching point between the two gate pulses i and j, both gates 10.1
The DC components of the output of 1 become equal, and the DC component of the output m of the subtraction circuit 12 becomes 0. However, if the switching point between the two gate pulses 1+J and the peak position of the output shift, one of the gate outputs becomes larger depending on the magnitude and direction of the phase difference. The component becomes a positive or negative voltage corresponding to the direction of the phase difference. The output m corresponding to this phase difference passes through the LPFT to vc
Synchronization is achieved by controlling the frequency and phase of the os.

In order to detect the phase difference using the circuit shown in FIG. 3, in the first step the two gate pulses i and j of the timing clock are controlled so that they are close to the peak position of the output waveform from the envelope detector 5. Then, in the second stage, the analog gate 10.
11 was used to adjust the timing accurately. As described above, it is necessary to configure a complicated control circuit in two stages, and there is a drawback that it takes time to pull in synchronization. Furthermore, the degree of spreading was limited because it was difficult to manufacture high-speed analog gates that could pass direct current, which is required when increasing the speed of pseudorandom codes and spreading the spectrum over a wide band.

(Objective of the Invention) An object of the present invention is to provide a spread spectrum signal receiving device equipped with a synchronization circuit that has accurate and stable synchronization pull-in operation with a simple circuit configuration and can cope with increased speed of spread signals. It's about doing.

(Structure of the invention) The present invention will be explained in detail below with reference to the drawings.

FIG. 5 shows an example of the circuit configuration of the phase difference detection circuit 6 in the timing synchronization circuit 27 implementing the present invention. In the figure, 1
5 and 16 are analog delay lines having the same delay time t,
17 is a comparator that compares the voltage between the output p of the delay line 16 and the input voltage from the envelope detector 5; 18 is a comparator that compares the output voltage n of the first stage delay line 15 with a preset threshold voltage; Comparator, 19 is both comparator 17.18
20 is a counter that repeats counting at the cycle of input 24 from clock generation circuit 9, 25 is a counting clock whose frequency is an integral multiple of input 24, and has a spreading code speed. The clock is preferably several times or more, and is generated by the clock generating circuit 9. 21 is a ROM that converts the code of the output of the counter 20; 22 is a ROM 21;
23 is a D/A converter, 26 is D
This is the output of the /A converter, that is, the output of the phase difference detection circuit 6.

FIG. 6 shows an example of waveforms of each part of the phase difference detection circuit 6 of FIG. 5 according to the present invention, where h is the input from the envelope detector 5, n is the output of the first stage delay line 15, and p is the second stage delay line 15. q is the output of the comparator 17, r is the output of the comparator 18,
S represents the output of the AND gate 19, and U represents the voltage represented by the output code of the ROM 21.

The operation of the phase difference detection circuit 6 used in the present invention will be explained below with reference to FIGS. 5 and 6. The input from the envelope detector 5 is delayed by 2t through delay lines 15 and 16, each having an equal delay time t, and the output p is sent to the comparator 1.
7 is input. The delay time t is a value smaller than about 1/2 of the width A of the correlation peak that appears every period of the pseudorandom code and larger than O, and is a value that is smaller than about 1/2 of the width A of the correlation peak that appears in each period of the pseudorandom code, and is larger than O, and is a value that is equal to or smaller than the noise included in the input from the envelope detector and the accuracy of the comparator 17. etc. (1/2
) A~(1/4) A is appropriate. The comparator 17 compares the level of this delayed output p and the other input, and is set to output an output q which is "1" if the former is large, and "0" if the latter is large. Therefore, this output q becomes “O” at a position that is quite delayed from the position of the input correlation peak.
” to “1”.

On the other hand, in the comparator 18, when the output n, which is obtained by delaying the input by t in the negative stage delay line 15, is greater than a preset threshold voltage V, an output r that becomes "!" is obtained. The output q of the comparator 17 shows many changes from "O" to "1" due to the waveform W having a small level other than the correlation peak, but the output r of the comparator 18 shows the set threshold voltage V and It does not appear in the output because it is compared.

The threshold voltage V of the comparator 18 is the correlation waveform W of a small signal other than the correlation peak of the output of the matched filter 1.
It is set to a value that prevents the output of the comparator 18 from becoming "1" due to noise input together with the signal, and is set to a value that can sufficiently extract the correlation peak output that appears in each period of the pseudorandom code.

By ANDing the outputs q and r of both comparators 17 and 18, an output S is obtained. On the other hand, the counter 2o is counted up by the counting clock 25 from the clock generation circuit 9, and is reset by the clock 24 having a repetition frequency equal to the repetition frequency of the spreading pseudorandom code. The counting clock 25 is the clock 24
Since the value is an integral multiple of , the output of the counter 20 has a sawtooth waveform in which the stepwise rise of the clock 25 is reset by the clock 24, and when expressed in terms of voltage, it has a waveform like U. The waveform U in Fig. 6 is a ROM for code conversion.
This is an example where the output of counter 21 is the same as the input (that is, no ROM is used), and both the output of counter 20 and the output of ROM 21 have a waveform U when expressed in terms of voltage. This is sampled by the pulse S obtained from the received data in the register 22, and D/
An output 26 is obtained via an A converter 23. This output 26 is
As shown in Figure 6, when the timing of the input and the clock match, it is almost OV, but if the timing of the input and the clock is different, the deviation (
It becomes a DC voltage with a polarity corresponding to the direction of the phase difference) and a voltage proportional to the magnitude of the shift. If the voltage controlled oscillator 8 is controlled by this output 26 via the LPF 7, a synchronous circuit is constructed.

The phase difference detection circuit 6 having a phase difference detection characteristic like the waveform U in FIG. There is no need for complex synchronous pull-in processing. Furthermore, since circuit elements such as analog switches are not used, a circuit suitable for high-speed operation can be constructed.

FIGS. 7 and 8 show output waveforms u' and u'' when the output of the counter 20 is converted into another form by the code conversion ROM 21.

The waveform U' in Figure 7 is sign-converted so that it is proportional to the phase difference in the range where the phase difference between the input signal and the clock is close to 0, and becomes a constant positive or negative voltage in the range where the phase difference is sufficiently larger than 0. This is the output voltage waveform of the ROM 21 in the case of FIG. In this case, compared to the characteristics of waveform U in Fig. 6, the detection output is large when the phase difference is large, so the pull-in time is fast, and the slope near 0 phase difference is large, so the pull-in can be performed with higher precision. be.

The waveform U'' in Figure 8 shows that the detected output is obtained only in the range where the phase difference between the input clock and the clock is close to O, and the sign is converted so that the output becomes O in the range where the phase difference is sufficiently larger than O. This is the output voltage waveform of the ROM 21. In the case of the above-mentioned waveforms U and U', if the peak detection output S appears at the wrong position due to noise etc., a large abnormal voltage is generated at the output 26 and the oscillation frequency of VCOS is changed. Although there is a risk that the synchronization state will become unstable, such a risk can be prevented if detection characteristics such as waveform 11' in FIG. 8 are used.

However, with the detection characteristics of the waveform U'' in Figure 8, if the phase difference is large, it is not possible to pull in the waveform. It is effective to perform processing such as switching to the detection characteristic of waveform U''.

Furthermore, if any detection characteristics other than the detection characteristics such as waveforms u, u', and U'' are effective, an effective phase difference detection circuit can be realized by changing the contents of the ROM 21.

(Effects of the Invention) As explained in detail above, according to the present invention, a simple synchronization circuit can be configured without using a conventional complicated control circuit, and a stable and accurate synchronization state can be achieved. In addition, it is possible to achieve optimal synchronization characteristics depending on the situation. Furthermore, it can be used as a stable synchronization circuit even in the case of high-speed spread signals.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the demodulator circuit side of a receiving device to which the present invention is applied, FIG. 2 is a diagram showing transmission waveforms of a transmission system to which the present invention is applied, and waveform examples of each part of the circuit in FIG. 1, and FIG. 3 4 is a block diagram showing an example of a phase difference detection circuit used in a conventional receiver, FIG. 4 is a waveform example of each part of the circuit in FIG. 3, and FIG. 5 is a block diagram showing an example of a phase difference detection circuit used in a receiver of the present invention. A block diagram showing a configuration example of a detection circuit, FIG. 6 is a waveform example diagram of each part of the configuration example in FIG. 5, and FIGS. 7 and 8 are waveform side diagrams resulting from code conversion other than that shown in FIG. . 1...Matched filter, 2...Synchronized detector, 3.
... Sampling judgment circuit, 4... Carrier wave regeneration circuit,
5... Envelope detector, 6... Phase difference detection circuit, 7.
...LPF, 8...VCO19...Clock generation circuit, 10, 11...C, ATE, 12...S U
B, 13.14...Gate input terminal, 15.16.
...Delay line, 17.18...Comparator, 19...A
ND, 20...Counter, 21...ROM. 22...Register, 23...D/A converter, 24.
25...Clock input, 26...Output, 27...
timing synchronization circuit. η ] Figure duck 20 1 = 1 roe: Nol-long, -1 ( g -ji 31211 5?14 Figure 6 Octopus 7 mesh Figure 8

Claims (1)

[Claims] The position of the correlation peak of the envelope detection output obtained by envelope detection of the output of a matched filter that receives a spread spectrum signal as input, and the voltage at a frequency equal to the repetition frequency of the pseudorandom code for the spread spectrum signal. A phase difference detection circuit detects the phase difference with the demodulation timing clock pulse generated from the controlled oscillator, controls the voltage controlled oscillator using the phase difference to create the demodulation timing clock pulse, and generates the demodulation timing clock pulse of the matched filter. In a spread spectrum signal receiving device configured to obtain a demodulated output by sampling the output, the phase difference detection circuit sequentially delays the envelope detection output by a delay time smaller than about 1/2 of the width of its correlation peak. A first delay line and a second delay line are connected in cascade, and voltages between the second delay line output and the envelope detector output are compared to determine whether the second delay line output is large. a first comparator that outputs an output when the
a second comparator that provides an output when the delay line output of the first,
an AND gate that ANDs each output of the second comparator;
a counter that resets a count in synchronization with the demodulation timing clock pulse; a ROM that converts the output of the counter into a preset waveform; and a register that samples the output of the ROM with the output pulse of the AND gate. , and a D/A converter which D/A converts the output of the register to obtain a DC output.