JPH01310467A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To simplify an instruction ROM to store the program of a processor by providing a single instruction ROM shared with N pieces of processors, and setting delay circuits between a single instruction ROM and the respective processors. CONSTITUTION:When digital filter is constituted by cascade-connecting the N pieces of generally applicable processors 11, 12...1N, for the instruction executed by the respective processors, the executing timings are different, while the execution contents are made the same. Instructions are successively read from a shared ROM 21 to have stored a series of instruction group executed by the processors, and they are supplied through delay circuits 31, 32,...3N, whose delay quantities t1, t2,...tN conform to the executing time lags of the respective cascade-connected processors 11, 12,...1N, to the respective processors 11, 12,...1N.

Description

[Detailed Description of the Invention] (Summary of the Invention) Regarding a digital signal processing circuit using a plurality of processors, the purpose of this invention is to simplify an instruction ROM that stores a processor program. In a digital signal processing circuit that allows each processor to perform processing with different execution timing but the same execution content, a common instruction ROM is provided that stores a series of instructions that define the processing that the processors execute, and the instructions are sequentially executed from the instruction ROM. The read instructions are configured to be input to each processor via delay circuits having respective delay times.

[Industrial application field]

The present invention relates to a digital signal processing circuit using a plurality of processors.

When constructing a digital filter using general-purpose signal processing processors, if the tap length of the filter is long and the amount of signal processing is large, it is common to connect a plurality of the above-mentioned processors in cascade.

[Prior Art] FIG. 3 shows an example of a digital signal processing circuit in which a plurality of processors are connected in cascade. 11,12°...IN is N
The first processor 11 receives and processes input, passes the processing result to the next processor 12, the next processor 12 receives and processes it, and passes the processing result to the next processor. Then, in the same manner, the processing result of the last processor IN becomes the output of this circuit. Each processor has an instruction ROM 21, 22 . ...2N is attached, and a program that defines the processing contents of each processor is stored in IROM (read-only memory).

ing.

If the required tap length of the digital filter is L and the number of taps that can be accommodated in one processor is M, then the required number of processors (N above) is L/M.

[Problem to be solved by the invention]

When using N processors, general-purpose processors usually use external instruction ROMs, so the number of instruction ROMs is also N.
, resulting in an increase in hardware scale and power consumption.

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned problems and to simplify the instruction ROM that stores the program program of the processor.

[Means to solve the problem]

As shown in FIG. 1, in the present invention, one instruction ROM is common to N processors 11 to IN, and a delay circuit is provided between this one instruction ROM 21 and each processor 11, 12, . . . IN. 31, 32. ...Place 3N. Further, a clock 41 is commonly given to each processor.

[Effect]

When cascading N general-purpose processors to configure a digital filter, each processor executes the fourth instruction.
As shown in the figure, although the execution timing is different, the execution contents are the same. That is, the basic operation of a digital filter is a product-sum operation, in which each processor performs its own calculation, adds it to the data from the preceding processor, passes the result to the subsequent processor, and repeats this operation. The deviation in the operation of each processor is only a deviation of one instruction.

Therefore, as shown in FIG. 1, instructions are sequentially read out from a common ROM 21 storing a series of instructions to be executed by the processor, and are sent to delay circuits 31, 32, . . . 3N to each processor 11, 12, . . . IN, the same processing as in FIG. 3 can be performed. This is the delay circuit 31, 3
2. The delay amounts t, tz, . . . t8 of 3N are adjusted to the difference in execution time of each processor due to the cascade connection.

This configuration ensures that each processor has hardware (
This makes it possible to standardize the instruction ROM (instruction ROM), thereby reducing power consumption and hardware scale.

〔Example〕

FIG. 2 shows an embodiment of the present invention. In this case, the delay circuit 31
~3N is constituted by a shift register 51. A series of instructions to be executed by the processor are sequentially read from the instruction ROM 21, and each stage of the shift register 51 is clocked by a clock 41.
It will be shifted by Processor 11.12.・・・
. . . IN receives and executes this sequentially, but the processors 11, 12, and IN are connected to the output terminals of the stages successively subsequent to the shift register 51, and the processors 11, 12, and IN are connected to the output terminals of the stages successively subsequent to the shift register 51, and the processors 11 and 12 are connected to the output terminals of the stages successively subsequent to the shift register 51, and the processors 11 and 12 are connected to the output terminals of the stages successively subsequent to the shift register 51, and the processors 11 and 12 are connected to the output terminals of the stages sequentially subsequent to the shift register 51, and the processors 11 and 12 are connected to the output terminals of the stages successively subsequent to the shift register 51. ……
Delayed by tN (Determine the connection destination stage like this)
Since it receives instructions, the third one has a separate instruction ROM.
Processing similar to that shown in the figure can be performed.

Each stage of the shift register 51 has a bit width that covers the instruction word length. For example, if one instruction has a maximum of 32 bits, the bit width of the shift register 51 is set to 32.

Each processor 1112. ...If the IN operation is sequentially delayed by one instruction word, the instruction ROM is
21, the shift register 51 is shifted using the clock, and the processors 11, 12 . . . . IN is the first .IN of the shift register 51. Second. . . . It is sufficient to sequentially take in each instruction from the output end of the Nth stage.

Of course, there is no delay for the first processor 11,
The readout output of the instruction ROM is directly supplied to the processors 12 to IN from the first to N-th shift registers 51.
The output of one stage may be provided.

In addition, if the operation delays of each processor are uneven, the connection destination to the shift register 51 may be selected or the delay time of the delay circuits 31 to 3N may be determined so as to obtain a desired delay.

[Effects of the Invention] As explained above, in the present invention, by sharing hardware, multiple processors can be driven with the instruction ROM required for one processor, resulting in smaller hardware and lower power consumption. can do.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is an explanatory diagram showing an embodiment of the invention, Fig. 3 is an explanatory diagram showing a conventional example, and Fig. 4 is a time chart for explaining the operation of Fig. 3. It is. In FIG. 1, 21 is an instruction ROM, 11 to IN are a plurality of processors, 31 to 3N are delay circuits, and 41 is a clock.

Claims (1)

[Claims] 1. In a digital signal processing circuit in which a plurality of processors (11, 12, ... 1N) are connected in cascade and each processor performs processing with different execution timing but the same execution content, the processor A common instruction ROM (21) is provided that stores a series of instructions that define the processing to be executed by the processors, and a delay circuit (31, 32, . . . ...3N).