JPH01308979A - Ic tester - Google Patents

Abstract

PURPOSE:To facilitate the generation of a test pattern adapted to a device by selecting two signals from among signals outputted from three data generation circuits to perform a scrambling of a data with the outputting of the signals to a logic gate. CONSTITUTION:A data made by an algorismic data generation circuit (which outputs a fixed pattern by an address signal) 1, a ROM data generation circuit (which generates a pattern programmed) 2 and a data word circuit (which outputs 0 or 1 fixed) 3 are applied to a data selection circuit 5a to select two signals, which are outputted to logic gates 5b-5d. Signals from data generation circuits 1-3 are outputted with the selection circuit 5a to a data selection circuit 6. The two signals outputted to the logic gates 5b-5d are outputted to the selection circuit 6 from the gates. A signal produced with a data scrambling circuit 5 is selected by the selection circuit 6 to be outputted as test pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a test pattern generation circuit in an IC testing device.

[Conventional technology]

Conventional test equipment generates test patterns for testing semiconductor memory elements (hereinafter referred to as memory) by generating independent data for each circuit function: algorithmic data generator circuit, ROM data generator circuit, and data word circuit. The circuit configuration was such that the second
The figure shows its block diagram.

That is, the conventional test pattern generation method uses an algorithmic data generator circuit (1) that generates a fixed pattern from an address signal, and a ROM data generator circuit (2) that stores a pattern to be output in advance.
) and data word circuit (8) with 1 data
The data selection circuit (4) selects one of the three output signals and outputs it as a test pattern.

[Problem to be solved by the invention]

Since test pattern generation in conventional IC test equipment has the above configuration, each generation circuit must be used independently, so it is necessary to use an algorithmic data generator circuit, which is the main data generation method for memory tests. The data generation used is limited and depends on the hardware of the IC test equipment, and as a result, there are problems in that test patterns cannot be generated that are optimal for the device.

This invention was made in order to solve the above-mentioned problems, and it is possible to generate conventional patterns as well as to perform data scrambling between an algorithmic data generator circuit, a ROM data generator circuit, and a data word circuit. The purpose is to obtain test equipment.

[Means to solve the problem]

The IC testing device according to the present invention is a conventional test pattern generation circuit provided with a data selection circuit and a logic circuit as a data scrambling circuit.

[Effect]

The test pattern generation circuit in this invention selects two signals from the signals output from each of the three data generation circuits by the data select circuit (8a) of the data scrambling circuit, outputs the signals to the logic gate, and outputs the data. This scrambled output is selected as a test pattern by a data selection circuit.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is an algorithmic data generator circuit which outputs a fixed pattern in response to an address signal. (2) is a ROM data generator circuit that generates a programmed pattern. (8) is a data word circuit which outputs a fixed value of 0' or 1'. (6) is a data scrambling circuit, which is composed of an AND circuit of logic gates of the data select circuit (5b) of (5a), an OR circuit (b), and an EXOR circuit (5d). (6) is a data selection circuit that ultimately selects a test pattern.

A data select circuit (5a) selects two signals from the data generated by each of the data generation circuits (1) to (8) and outputs them to each logic game (5b) to (5d).

Further, the data select circuit (5a) outputs the signals from each data generation circuit (1) to (8) to the data select circuit (6). The two signals output from the data select circuit (5a) to the logic gates (5b) to (5d) are output from each gate to the data select circuit (6). The data select circuit (6) selects the data scramble circuit (6).
) is selected and output as a test pattern.

〔Effect of the invention〕

As described above, according to the present invention, since the test pattern generation circuit is configured to perform data scrambling, it is possible to easily generate a test pattern suitable for a device, and the programming efficiency is increased.
Optimal evaluation of devices becomes easier.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a test pattern generation circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional test pattern generation circuit. In the figure, (6) is a data scrambling circuit, (5a
) (6) shows a data select circuit, (5b) shows an AND circuit, (5c) shows an OR circuit, and (5i) shows an EXOR circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] In the test pattern generation used in testing semiconductor memory elements in IC test equipment, there is an algorithmic data generator circuit that automatically generates a pattern from an address signal, a ROM data generator circuit that generates a preprogrammed pattern, and a Hi or Low control circuit. An IC testing device comprising a data scrambling circuit that synthesizes two signals out of the signals output from a uniquely output data word circuit to form a test pattern.