JPH01307245A - Manufacture of thin-film transistor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent disconnection at the place where interconnections are applied without increasing a number of processes, by forming a hole in an interlayer insulating film, the hole extending to the connecting place in the lower layer, and then by forming an upper interconnection metallic film by vapor deposition for reinforcing the connecting place of the lower interconnection. CONSTITUTION:Following the formation of a polyimide film 5 as an interlayer insulating film, a hole is formed in the polyimide film 5, at the connecting place where an interconnection pattern 4 is connected with a load resistance pattern 3. Then an interconnection metallic film is vapor deposited on the polyimide film 5. This metallic film is also deposited on the connecting place where the lower layer interconnection pattern 4 is connected with the upper layer as well as on the place where it is connected with the load resistance pattern 3, through the interlayer connecting hole 7 formed in the polyimide film 5. The metallic film is then removed selectively. Finally, an uppermost interconnection pattern 6 and a connection reinforcing metallic film pattern 8 are formed simultaneously. In this manner, it is possible to prevent disconnection due to burrs of the load resistance pattern 3.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a thin film transistor integrated circuit, and more particularly to an improvement in a method for manufacturing a thin film transistor integrated circuit to prevent wire breakage.

BACKGROUND OF THE INVENTION Steps directly related to the object of the present invention in a conventional method for manufacturing a thin film transistor integrated circuit will be explained with reference to FIGS. 3 to 6.

As shown in FIG. 3, after forming a semiconductor thin film (not shown) and a gate insulating film 2 on a glass substrate 1, a lift-off resist pattern is formed on the gate insulating film 2 by photolithography, and a Cr Sio film ( 250
By depositing a resist film (0A thick) by a sputtering method and removing the resist with acetone, a load resistor pattern 3 constituting an inverter circuit is formed.

Next, after forming a resist pattern for lift-off, a metal film for wiring (1000A thick) was deposited, and the resist was removed with acetone to form a wiring pattern connected to the load resistance pattern 3 as shown in FIG. form 4.

Next, as shown in FIG. 5, it is covered with a polyimide film 5 (2 μm thick) as an interlayer insulating film.

Next, after forming holes for interlayer wiring connection in the polyimide film 5 as necessary, a metal film for the uppermost wiring (for example, 5000
Then, a top wiring pattern 6 as shown in FIG. 6 is formed by photolithography. The connection between the wiring pattern 6 and the underlying wiring pattern 4 is also made at the same time.

Problems to be Solved by the Invention However, the above-described conventional method has a problem in that wiring breaks occur at a fairly high rate.

Specifically, as shown in FIG. 3, "paris" occur in the periphery (the part surrounded by the broken line) of the load resistance pattern 3 formed by the lift-off method. Due to this gap caused by Paris, the metal film is likely to be cut in the next metal film deposition process. As a result, as shown in FIG.
The probability of wire breakage is high, and this has been a factor in reducing the manufacturing yield of thin film transistor integrated circuits.

In order to prevent such disconnection of the wiring, it is conceivable to make the metal film for forming the wiring pattern 4 sufficiently thick to cover the difference between the edges of the load resistor pattern 3. However, since the wiring pattern 4 is also formed by the lift-off method, palls are generated in the periphery, and the difference due to the palls increases as the metal film thickness increases. This is not a good idea as short-circuits are likely to occur at grade-separated intersections.

Incidentally, if the load resistance pattern and the wiring pattern are formed by an etching method, it is possible to prevent the occurrence of paris, but this method cannot be used because the previously formed semiconductor thin film is also etched at the same time.

The present invention has been made in view of the above-mentioned problems, and is intended to reduce the probability of disconnection at wiring connection points without complicating the manufacturing process and without increasing the incidence of short circuits between upper and lower layer wiring. An object of the present invention is to provide a method for manufacturing a thin film transistor integrated circuit that enables the following.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention forms a hole in the interlayer insulating film, in addition to the hole for connecting the wiring between the eyebrows, through which the wiring connection point in the lower layer passes. It has a structure in which metal for wiring is vapor-deposited on top.

At the same time as the metal for the upper layer wiring is deposited, a metal film is deposited to cover the lower layer wiring connection points through the holes formed in the glabella insulating film that lead to the lower layer wiring connection points. Since the wire is reinforced, the probability of wire breakage occurring is greatly reduced.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIGS. 1 and 2.

The present embodiment relates to the manufacture of a thin film transistor integrated circuit similar to the conventional example described above, and the steps illustrated in FIGS. 3 to 5 are the same as the conventional example. Further, in FIGS. 1 and 2, the same reference numerals as in FIGS. 3 to 6 indicate the same parts.

After forming the polyimide film 5 as the glabellar insulating film shown in FIG. 5, conventionally only holes for connecting the glabella wiring are formed, but according to the present invention, as shown in FIG. A hole 7 corresponding to a connection point between the wiring pattern 4 and the load resistance pattern 3 is also formed in the polyimide film 5.

Thereafter, as in the past, a metal film for wiring is deposited on the polyimide film 5 to a thickness of, for example, 5000 A, but at the same time, this metal film is deposited through the glabellar wiring connection hole and the hole 7 formed in the polyimide film 5. It is also deposited on the connection points of the lower layer wiring pattern 4 with the upper layer and the connection points with the load resistance pattern 3.

Next, the metal film is selectively removed by photolithography, and as shown in FIG. 2, the uppermost wiring pattern 6 and the connection reinforcing metal film pattern 8 are simultaneously formed.

This connection reinforcing metal pattern 8 allows the wiring pattern 4
Since the connection point with load resistance pattern 3 is reinforced,
Breakage of the load resistance pattern 3 due to cracks can be prevented.

In this embodiment, the connection between the load resistance pattern 3 and the wiring pattern 4 was reinforced, but in terms of numbers, the connection between the wiring pattern in the lower layer of the interlayer insulating film is similar. Connection reinforcement can be performed. Moreover, even if the connection points are similar, the above-mentioned connection reinforcement may be selectively applied only to the connection points with a high probability of disconnection. Furthermore, the overall manufacturing process of the thin film transistor integrated circuit and the type and thickness of the metal film are not limited to the above-mentioned examples.

Effects of the Invention As is clear from the above description, the present invention is capable of reinforcing the lower layer wiring connection points by forming holes in the interlayer insulating film through which the lower layer wiring connection points pass, and then depositing a metal film for the upper layer wiring. This method does not increase the number of steps and still
This has the effect of reducing disconnections at wiring connection points and improving the manufacturing yield of thin film transistor integrated circuits without causing an increase in the incidence of short circuits between upper and lower wiring layers.

[Brief explanation of the drawing]

1 and 2 are a schematic sectional view and a schematic plan view, respectively, for explaining the characteristic steps of a manufacturing method according to an embodiment of the present invention, and FIGS. 3 to 6 are a schematic sectional view and a schematic plan view, respectively, of a conventional manufacturing method. FIG. 2 is a schematic cross-sectional view and a schematic plan view for explaining each step. l...Glass substrate, 2...Gate insulating film, 3...
Load resistance pattern, 4... Wiring pattern, 5... Polyimide film (interlayer insulation film), 6... Wiring pattern, 7
...Hole corresponding to wiring connection point, 8...Metal film pattern for connection reinforcement. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure (C1) (b) 3rd L (a) (b) 20th (Q) 84445! hJ@4dk / f'l -n (b) Figure 4 (Q) Figure 5 (a) Figure 6 (Q) (b)

Claims (1)

[Claims] 1. A method for manufacturing a thin film transistor integrated circuit, comprising forming a hole through an interlayer insulating film to a lower layer wiring connection point, and then depositing a metal film for an upper layer wiring.