JPH01307215A - Manufacture of semiconductor - Google Patents

Manufacture of semiconductor

Info

Publication number
JPH01307215A
JPH01307215A JP13801988A JP13801988A JPH01307215A JP H01307215 A JPH01307215 A JP H01307215A JP 13801988 A JP13801988 A JP 13801988A JP 13801988 A JP13801988 A JP 13801988A JP H01307215 A JPH01307215 A JP H01307215A
Authority
JP
Japan
Prior art keywords
wafer
diffusion
boron glass
layer
defects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13801988A
Other languages
Japanese (ja)
Inventor
Kazuyuki Horiuchi
堀内 和志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP13801988A priority Critical patent/JPH01307215A/en
Publication of JPH01307215A publication Critical patent/JPH01307215A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To restrain the generation of crystal defects after spread diffusion and epitaxial growth by a method wherein boron glass left on or attaching to an Si wafer surface is dissolved or removed, by turning it into a hydrophilic Si wafer surface, with sulfuric acid-hydrogen peroxide system etchant (mixed acid). CONSTITUTION:After boron glass is made to attach to the Si wafer 2 side on which an SiO2 mask 3 is formed, the Si wafer 1 surface, on which the SiO2 mask 3 is not formed, is subjected to roughened surface treatment. After the Si wafer 2 is treated sequentially with hydrofluoric acid system etchant, pure water, mixed solution of sulfuric acid-hydrogen peroxide, and pure water, the Si wafer 2 is subjected to spread diffusion. Thereby, the generation of defects after the spread diffusion can be prevented, and impurity on the Si wafer 2 surface is eliminated, so that the generation of defects on the diffusion layer at the time of epitaxial growth can be restrained.

Description

【発明の詳細な説明】 0)産業上の利用分野 本発明はSi半導体デバイスの不純物拡散工程における
固体拡散源窒化ホウ素(BN )からのB拡散に関する
DETAILED DESCRIPTION OF THE INVENTION 0) Industrial Application Field The present invention relates to B diffusion from a solid diffusion source boron nitride (BN) in an impurity diffusion process for Si semiconductor devices.

(0)  従来の技術 従来から拡散工程には種々の方法が知られて°いる。2
ステツプ拡散、メルトスルー拡散、固相−固相拡散など
の内、2ステツプ拡散はデポクシ1ン(プレデポジシ曽
ンとも言う)、ガラス除去、ドライブの3段階より構成
されている(前田著、最新L8Iプロセス技術、198
4年)。
(0) Prior Art Various methods have been known for the diffusion process. 2
Among step diffusion, melt-through diffusion, and solid phase-solid phase diffusion, two-step diffusion consists of three stages: deposition (also called pre-deposition), glass removal, and drive (written by Maeda, the latest L8I). process technology, 198
4 years).

固体拡散源としてBNNウニへ使ってSiウェハにB拡
散をする場合、プレデボジシ■ン後のボロンガラス除去
工程をフッ酸系エッチャントでのみ行い、水洗後、引き
伸とし拡散をして、不純物の拡散工程は終了する方法が
あ、た。
When using BNN as a solid diffusion source to diffuse B into Si wafers, the boron glass removal process after predeposition is performed only with a hydrofluoric acid etchant, and after washing with water, stretching and diffusion are performed to diffuse impurities. There was a way to finish the process.

しかし、この方法ではウニへ表面からボロンガラスが十
分に除去できない場合があり、引き伸ばし拡散後、ウニ
八表面で異常拡散による欠陥が認められた。
However, this method may not be able to sufficiently remove boron glass from the surface of the sea urchin, and defects due to abnormal diffusion were observed on the surface of the sea urchin after stretching and diffusion.

グレデポジシ曹ン後のボロンガラスを多工程によシ除去
する方法もあった。例えばSiウェハにおいて、7ツ酸
系によるエツチングに続いて純水で洗浄し、イソプロピ
ルアルコール(IPA)O噴霧後、硫酸−過酸化水素系
によるエツチングに続いて純水で洗浄し、硝酸−塩酸系
によるエッチングと純水洗浄、さらにフッ酸系エツチン
グをした後、純水で洗浄してから引き伸ばし拡散を行う
方法である。この方法中で、IPAと硫酸−過酸化水素
系は有機物除去に有効である。同じく、硫酸−過酸化水
素系と硝酸−塩酸系は金属除去に効果がある。
There was also a method of removing boron glass after Gredepositing using multiple steps. For example, in the case of a Si wafer, etching with a heptonic acid system is followed by cleaning with pure water, spraying with isopropyl alcohol (IPA) O, etching with a sulfuric acid-hydrogen peroxide system, followed by cleaning with pure water, and then cleaning with a nitric acid-hydrochloric acid system. This method involves performing etching with water, cleaning with pure water, then hydrofluoric acid etching, cleaning with pure water, and then stretching and diffusing. In this method, IPA and sulfuric acid-hydrogen peroxide system are effective in removing organic matter. Similarly, sulfuric acid-hydrogen peroxide systems and nitric acid-hydrochloric acid systems are effective in removing metals.

しかし、上記の方法は工程数が多くプレデボジシ暫ンか
ら引き伸ばし拡散までにかなシ時間がかかる点とフッ酸
と硝酸が混合すると、Siウェハが溶解する点の2つの
欠点かあ、た。
However, the above method has two drawbacks: it requires a large number of steps, and it takes a long time from pre-deposition to stretching and diffusion, and the Si wafer dissolves when hydrofluoric acid and nitric acid are mixed.

ところで、引き伸はし拡散後のエピタキシャル成長に生
成する積層欠陥は高濃度不純物拡散の場合、顕著に現れ
る。拡散後のエピタキシャル成長で現れる結晶欠陥をト
リミングしたり(特開昭59−210650号公報)、
結晶欠陥への選択拡散をしたり(特開昭62−2086
26号公報)する方法が考えられている。
Incidentally, stacking faults generated in epitaxial growth after stretch diffusion appear prominently in the case of high concentration impurity diffusion. Trimming crystal defects that appear during epitaxial growth after diffusion (Japanese Unexamined Patent Publication No. 59-210650),
Selective diffusion to crystal defects (Japanese Patent Application Laid-Open No. 62-2086)
26)) is being considered.

上述した従来の方法では、エピタキシャル成長後に半導
体基板の選択的エツチングまた紘拡散工程を新たに必要
としており、露光機ヒレシストを′用いたフォトリソグ
ラフィー技術を利用しなければならない。
The above-mentioned conventional method requires selective etching of the semiconductor substrate or a diffusion process after epitaxial growth, and requires the use of photolithography technology using a photolithography device.

前記の結晶欠陥はエピタキシャル成長に伴う積層欠陥が
主であるが、この他にもSiウェハにはドーパントのミ
スフィツトによる転移が生成することがある。
The crystal defects mentioned above are mainly stacking faults accompanying epitaxial growth, but in addition to these, dislocations may also occur in Si wafers due to dopant misfit.

(ハ)発明が解決しようとする課題 従来の技術には、ボロンガラス除去が不十分であるか、
またはボロンガラス除去工程数が多く手間がかかる問題
点と拡散後のエピタキシャル成長時に発生する積層欠陥
を修正する手間がかかる問題点かあル、本発明はこの点
を解決し、少ない工程で半導体素子の動作部における結
晶欠陥の発生を抑えることを目的とするものである。
(c) Problems to be solved by the invention Does the conventional technology have insufficient ability to remove boron glass?
Alternatively, there is the problem that the number of boron glass removal steps is large and time consuming, and the problem that it takes time and effort to correct stacking faults that occur during epitaxial growth after diffusion. The purpose is to suppress the occurrence of crystal defects in the operating parts.

に)課題を解決するための手段 この発明の製造方法はブリデボジシ冒ン後の半導体の処
理に関するものであ、て、SiO2マスクを設けたSi
ウェハ側にボロンガラスを付着させた後、Sin、マス
クのない側のSiウェハ表面を粗面加工し、それからS
iウェハを順次、7ツ酸系エツチヤント、純水、硫酸−
過酸化水素混合液、純水で処理した後、81ウエーの引
き伸ばし拡散することを特徴とする。
B) Means for Solving the Problems The manufacturing method of the present invention relates to the processing of semiconductors after debossing.
After attaching boron glass to the wafer side, the Si wafer surface on the side without a mask is roughened, and then S
The i-wafer was sequentially treated with a heptonic acid etchant, pure water, and sulfuric acid.
It is characterized by 81-way stretching and diffusion after treatment with a hydrogen peroxide mixture and pure water.

に)作 用 本発明の製造方法は、グレデポジシ冒ン後のフッ酸系エ
ッチャントで疎水性とな、たSiウェハ表面に残存また
は付着しているボロンガラスを。
(2) Function The manufacturing method of the present invention makes the boron glass remaining or attached to the surface of the Si wafer hydrophobic with the hydrofluoric acid etchant after Gredeposis cleaning.

硫酸−過酸化水素系エッチャント(混酸)で親水性のS
iウェハ表面に変えることによシ溶解また社離脱させ二
引き伸ばし拡散後及びエピタキシャル成長後の結晶欠陥
の発生を抑制するものである。
Hydrophilic S with sulfuric acid-hydrogen peroxide etchant (mixed acid)
By changing the surface of the i-wafer, it is possible to suppress the occurrence of crystal defects after two-stretching diffusion and epitaxial growth by dissolving or separating the wafer.

混酸紘通常の処理〜をした8iウ工ハ表面を親水性にさ
せ、フッ酸系エツチング状態では生じ得ない発熱と発泡
による洗浄兼溶解作用があり、そのためSiウェハ表面
のボロンガラスは完全に除去され、異常拡散による欠陥
が排除される。
The surface of the 8I wafer that has been subjected to the usual treatment is made hydrophilic, and has a cleaning and dissolving effect due to heat generation and foaming that cannot occur in the hydrofluoric acid etching state.Therefore, the boron glass on the Si wafer surface is completely removed. This eliminates defects caused by abnormal diffusion.

(へ)実施例 第1図に本発明の製造工程の断面図を示す。(f) Example FIG. 1 shows a cross-sectional view of the manufacturing process of the present invention.

第1図(a)はプレデボクシ1ン後の81ク工/’6D
断面図である。抵抗率10Ω・信の3インチ(100)
8i基板のN+オーミック層層上上、抵抗率70〜13
0Ω・1ON−ドレイン層2をエピタキシャル成長させ
、このN′″ドレイン層2層表0表面10.0拡散マス
ク3を介してボロンガラス4をグレデポジシ冒ンした後
、N オーミック層1を約0.2 p m OS i 
Ox  微粉末の衝突によシ粗面加工する。
Figure 1 (a) shows 81 k/'6D after pre-deboxing.
FIG. Resistivity 10Ω/3 inches (100)
On the N+ ohmic layer of the 8i substrate, resistivity 70-13
After epitaxially growing a 0Ω·1ON-drain layer 2 and depositing a grade of boron glass 4 through a diffusion mask 3, the N′″ drain layer 2 was deposited at a rate of about 0.2Ω. p m OS i
Ox: Roughens the surface by collision with fine powder.

プレデポジシ冒ンはN、雰囲気中で固体拡散源Siウェ
ハを使い1050℃で60分間の条件で行うと、N−ド
レイン層2の表層に、拡散層のP+ゲート層5が、N 
オーミック層1の粗面側に、10〜10 個・1 の結
晶欠陥が、夫々生成する。
When pre-depositing is carried out at 1050°C for 60 minutes using a Si wafer as a solid diffusion source in an N atmosphere, a P+ gate layer 5 as a diffusion layer is formed on the surface layer of the N- drain layer 2.
On the rough surface side of the ohmic layer 1, 10 to 10 crystal defects are generated.

第11/(b)は、7ツ酸エツチング後のSiウェハの
断面図である。Siウェハ上のボロンガラス4と8 i
 0.の拡散マスク3をフッ酸系エラチャン) (HF
 : NH4F : HI3 = 180清/:500
jFニア501?1j)で1分間エツチングしてから水
洗する。フッ酸系エラテントは、Siウェハ表面を疎水
性にするので水洗後もN−ドレイン層2の表面にはボロ
ンガラス4が残っている。尚、N+オーミック層1の粗
面側はPMMA系レジストで覆ってエツチングさせない
で、ボロンガラス粉末の+ N オーミック層1への付着を防止する。ここで、拡散
層P ゲート層5の表面のシート抵抗値は8〜9Ω/口
である。
No. 11/(b) is a cross-sectional view of the Si wafer after etching with hepatic acid. Boron glass 4 and 8 i on Si wafer
0. Diffusion mask 3 of HF
: NH4F : HI3 = 180 clear/: 500
Etch with JF Nia 501-1j) for 1 minute and then wash with water. Since the hydrofluoric acid-based elatent makes the surface of the Si wafer hydrophobic, boron glass 4 remains on the surface of the N-drain layer 2 even after washing with water. Note that the rough side of the N+ ohmic layer 1 is covered with a PMMA resist so as not to be etched, thereby preventing the boron glass powder from adhering to the +N ohmic layer 1. Here, the sheet resistance value of the surface of the diffusion layer P and the gate layer 5 is 8 to 9 Ω/portion.

第1図(C)は、混酸エツチング後のSiウェハの断面
図である。フッ酸系エツチングの後、N オーミック層
1の粗面上のレジストをモノクロルベンゼンとメチルイ
ソブチルケトンの混合液で剥離してから、N−ドレイン
層2及びP+ゲート層5の表面に付着しているボロンガ
ラス4を混酸(H!804 :HtO,−400Wrl
 : 400 tnl )で20分間エツチングした後
、充分に水洗する。混酸はSiウェハ表面親水性にし、
かつ発熱と発泡を伴ったエツチングを行うのでSiウヱ
ハ上のボロンガラス4は完全に除去される。
FIG. 1(C) is a cross-sectional view of the Si wafer after mixed acid etching. After hydrofluoric acid etching, the resist on the rough surface of the N-ohmic layer 1 is peeled off with a mixture of monochlorobenzene and methyl isobutyl ketone, and then the resist adheres to the surfaces of the N- drain layer 2 and the P+ gate layer 5. Mixed acid (H!804: HtO, -400Wrl) with boron glass 4
: 400 tnl) for 20 minutes, and then thoroughly washed with water. The mixed acid makes the Si wafer surface hydrophilic,
Since etching is performed with heat generation and foaming, the boron glass 4 on the Si wafer is completely removed.

Siウェハを水洗して、グレデボジシ1ンの時より高温
で引き伸ばし拡散(ドライブ)を行う。
The Si wafer is washed with water and stretched and diffused (drive) at a higher temperature than in the graded body 1 process.

第1図(d)は、引き仲はし拡散後のSiウェハの断面
図である。0.− H,0雰囲気中で1150℃で18
0分間の条件でN−ドレイン層2上の拡散層のP ゲー
ト層5の引き伸はし拡散を行う。
FIG. 1(d) is a cross-sectional view of the Si wafer after diffusion with a puller. 0. - 18 at 1150 °C in H,0 atmosphere
The P gate layer 5 of the diffusion layer on the N- drain layer 2 is stretched and diffused for 0 minutes.

その結果、異常拡散による欠陥は認められなか+ うた。N オーミック層1の粗面側の結晶欠陥密度は1
0”−10@個−cm−”K保たれティ、(。
As a result, no defects due to abnormal diffusion were observed. The crystal defect density on the rough side of N ohmic layer 1 is 1
0"-10@pcs-cm-"K kept tee, (.

本発明を適用した素子として静電誘導サイリスタ(BI
T)の断面図を第2図に示す。N−ドレイン層2上にN
ソース層6とN コンタクト層7を設け、ソース、ゲー
ト、ドレインにMoの電極8を被着させた後に、ガラス
粉末の電着により保護膜9をゲートノース間に形成する
A static induction thyristor (BI) is an element to which the present invention is applied.
A cross-sectional view of T) is shown in FIG. N on drain layer 2
After providing a source layer 6 and an N contact layer 7 and depositing Mo electrodes 8 on the source, gate, and drain, a protective film 9 is formed between the gate north by electrodeposition of glass powder.

混酸による洗浄によシエピタキシャル成長し九Nソース
層6の結晶欠陥が4096減少したpまた、+ N オーミック層1の結晶欠陥は従来のようにゲッタリ
ング効果を示した。
By cleaning with a mixed acid, the crystal defects in the 9N source layer 6 were reduced by 4096 by epitaxial growth, and the crystal defects in the +N ohmic layer 1 exhibited a gettering effect as in the conventional case.

(ト)発明の効果 以上のように本発明の製造方法はSiウェハにB拡散す
る場合、引き伸ばし拡散後の欠陥発生が防止できるたけ
でなく、S1ウ工八表9面の不純物を除去できることに
より、拡散層上のエピタキシャル成長時の欠陥発生を抑
制しうるものである。
(G) Effects of the Invention As described above, when B is diffused into a Si wafer, the manufacturing method of the present invention not only prevents the occurrence of defects after stretching and diffusion, but also removes impurities on the 9th surface of the S1 U8 surface. , it is possible to suppress the occurrence of defects during epitaxial growth on the diffusion layer.

又、ボロンガラス以外でSiウェ八裏表面上ある微粒子
や無機汚染膜の除去もできるため、従来方法と比較して
良好な拡散及び成長状態が再現性良く得られる。
Furthermore, since fine particles and inorganic contamination films other than boron glass on the back surface of the Si wafer can be removed, better diffusion and growth conditions can be obtained with better reproducibility than in conventional methods.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の製造工程を説明する為の素子断面図で
ある。 第2図は本発明を適用しうるSITの素子断面図である
。 1・・・N+オーミック層、2・・・N−ドレイン層、
3・・・拡散マスク、4・・・ボロンガラス、5・・・
P ゲ−)Am、6・・・Nソース層、7・・・N コ
ンタクト層、8・・・電極、9・・・保護膜。
FIG. 1 is a cross-sectional view of an element for explaining the manufacturing process of the present invention. FIG. 2 is a sectional view of an SIT element to which the present invention can be applied. 1...N+ ohmic layer, 2...N- drain layer,
3... Diffusion mask, 4... Boron glass, 5...
P Ge-)Am, 6...N source layer, 7...N contact layer, 8...electrode, 9...protective film.

Claims (1)

【特許請求の範囲】[Claims]  Siウェハに固体拡散源BNウェハからB拡散をする
場合において、SiO_2マスクを設けたSiウェハ側
にボロンガラスを形成する第1工程と、SiO_2マス
クのない側のSiウェハ表面を粗面加工する第2工程と
、Siウェハ表面のボロンガラスをフッ酸系エッチャン
トで処理する第3工程と、Siウェハを硫酸と過酸化水
素の混合溶液で処理する第4工程と、Siウェハの引き
伸ばし拡散する第5工程とからなる半導体の製造方法。
When B is diffused into a Si wafer from a solid diffusion source BN wafer, the first step is to form boron glass on the side of the Si wafer provided with the SiO_2 mask, and the second step is to roughen the surface of the Si wafer on the side without the SiO_2 mask. a third step in which the boron glass on the surface of the Si wafer is treated with a hydrofluoric acid etchant; a fourth step in which the Si wafer is treated with a mixed solution of sulfuric acid and hydrogen peroxide; and a fifth step in which the Si wafer is stretched and diffused. A semiconductor manufacturing method consisting of steps.
JP13801988A 1988-06-03 1988-06-03 Manufacture of semiconductor Pending JPH01307215A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13801988A JPH01307215A (en) 1988-06-03 1988-06-03 Manufacture of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13801988A JPH01307215A (en) 1988-06-03 1988-06-03 Manufacture of semiconductor

Publications (1)

Publication Number Publication Date
JPH01307215A true JPH01307215A (en) 1989-12-12

Family

ID=15212155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13801988A Pending JPH01307215A (en) 1988-06-03 1988-06-03 Manufacture of semiconductor

Country Status (1)

Country Link
JP (1) JPH01307215A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013069729A1 (en) * 2011-11-09 2013-05-16 株式会社タムラ製作所 Semiconductor element and method for manufacturing same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013069729A1 (en) * 2011-11-09 2013-05-16 株式会社タムラ製作所 Semiconductor element and method for manufacturing same
JPWO2013069729A1 (en) * 2011-11-09 2015-04-02 株式会社タムラ製作所 Semiconductor device and manufacturing method thereof

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