JPH01306952A - Inter-processor communication system - Google Patents

Abstract

PURPOSE:To improve the processing efficiency of the title system by providing a register which actuates a timer when information is set from one processor and another register which stops the timer when information corresponding to the set information is set and designating the communicating state between processors. CONSTITUTION:When a register (REG) (A') becomes '1' a start signal '1' is outputted to a timer TM for actuation and, in the meantime, a slave MPU 2 analyzes a received code and, when it is confirmed that the code is to be accepted by the MPU 2, notices a host MPU 1 of the confirmation. The notice is made by setting a code, for example, a reception acknowledging code in a REG (B). When the code is set in the REG (B), a specific bit of a REG (B') becomes '1'. Upon deteceting the '1' of the specific bit by poling, the host MPU 1 sets the REG (B') to '0' and receives the code of the REG (B). The signal 0' of the REG (B') when the REG (B') is set to '0' stops the operation of the timer TM. Thus timer control can be made simpler and a high-speed and high-efficient process can be realized.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figures 4 and 5) Means for solving the problem to be solved by the invention (Figure 1) Working examples (Figs. 2 and 3) Effects of the invention [Summary] Regarding the communication method between processors, by linking register access and timer control Il, it is possible to automatically access registers for monitoring the processing time of lower processors. The purpose of this communication method is to improve processing efficiency using hardware by starting and stopping timers automatically. A register that starts a timer when information is set by the processor and a register that stops the timer when information corresponding to the information is sent are provided to instruct the communication state between the processors.

[Industrial application field]

The present invention relates to a communication system between microprocessors, and more specifically, for example, between a magnetic disk device used as an external storage device of a computer system and a magnetic disk control device, or between a plurality of communication systems provided in various control systems. When communicating various commands, etc. between microprocessors, all operations related to starting and stopping timers are implemented in hardware, simplifying the configuration and improving processing efficiency. Regarding communication methods.

[Conventional technology]

2. Description of the Related Art In recent years, office automation and the systemization of information processing devices called workstations have progressed, and there has been a great desire for faster and more diverse processing.

For example, magnetic disk devices widely used as large-capacity external storage devices are also required to have high-speed processing and multifunctionality.

For this reason, a magnetic disk control device that is interposed between a magnetic disk device and a host device (postcomputer) and controls the magnetic disk device is also required to have faster processing speed and multifunctionality.

To deal with this, magnetic disk control units are equipped with at least two MPUs, one dedicated to processing with the host device and the other dedicated to processing with the magnetic disk device, to speed up processing and increase the number of Prepared for functionalization.

FIG. 4 is a diagram for explaining a communication method between microprocessors used when executing instructions using two MPUs, an upper MPU and a lower MPU, in such a conventional magnetic disk control device. FIG. 5 is a flowchart of the operation.

In FIG. 4, 50 is the upper M of the magnetic disk control device.
PU (microprocessor) 51 is a lower MPU of the magnetic disk device, and 52 is an integrated circuit LSI. This L
The S I 52 is normally provided in a magnetic disk control device or the like together with the host MPU 50.

In the LSI 52, there is a register REC; (A>
, REG (A'), REG (B), REG (
B') and timer TM are set.

REG (A) is a register for setting the instruction code etc. issued from the host MPU 50, and REG (
When an instruction code etc. is sent to A), REG(A')
A predetermined bit of is 1''.

In addition, REG (B) is controlled by the lower MPU 51.
G After receiving the instruction code, etc. in (A), if you analyze it and confirm receipt, receive If as response information G
This is a register for separating the V-certification code, etc., and this RE
G(B') is a register whose predetermined bit automatically becomes 1'' when the code is set to REG(B).

Furthermore, the timer TM is controlled to start, stop, etc. by a microprogram within the host MPU 50.

Next, a description will be given based on the operation flowchart shown in FIG.

First, while the lower MPU 51 is polling REG (A'), the higher MPU 50 polls REG (A').
) and set some code, for example, an information read instruction code, in REG (A)'.

As a result, a bit indicating that some code is set in REG (A) and that it is valid is set in REG (A'), for example, the bit becomes "1".

At this time, the lower MPU 51 is waiting while polling, so when REG (A') becomes "1", it detects this and receives the code in REG (A).

On the other hand, after setting the instruction code etc. in REG (A), the upper MPU 50 starts a timer TM for monitoring the operating time of the lower MPU 51 and starts monitoring the time.

During this time, the lower MPU 51 analyzes the received instruction code, etc., and sends the result to the upper MPU 5 via REG (B).
Notify 0.

That is, when the lower MPU 51 confirms that the received code is the code to be received, for example, a code indicating receipt confirmation is set in REG (B).

After starting the timer, the host MPU 50 checks whether the time is within the preset time, and if it is within the set time, the host MPU 50 starts the timer.
Polling is performed to EG (B').

This polling accesses REG (B') and
Wait until some code is sent to G (B) and a bit indicating that it is valid is set to, for example, '1'.

At this time, if the time set in the timer TM has elapsed, it is determined that there is some kind of abnormality in the lower Ml) U51 or that the code cannot be received. Take action.

When some code is sent to REG (B),
Since "1" is automatically set in REG (B'),
The upper MPU50 that was waiting for polling is REG (
B), reads the code from the lower MPU 51, for example, the receipt confirmation code, receives the receipt, and sets the timer T.
Stop M.

[Problem to be solved by the invention]

The above-mentioned conventional devices had the following drawbacks.

(In order to start and stop the timer using the 11 upper MPU, a microprogram with a huge number of steps was required, so it took time to create it, and the processing time was also long. It was inefficient.

(2) Using a microprogram for timer control complicates processing.

The present invention has been made to solve these conventional drawbacks, and by realizing timer control using hardware, it is possible to perform high-speed and highly efficient processing, and it also improves the overall micro The purpose is to simplify program processing.

[Means to solve the problem]

In order to achieve the above object, the present invention is as follows.

FIG. 1 is a diagram illustrating the principle of a communication system between microprograms according to the present invention, and the present invention will be described in detail below based on this diagram.

Assume that while the lower MPU (microprocessor) 2 is monitoring the register REG (A') in the LSI 5 by polling, the upper MPUI has sent an instruction code or the like to the register REG (A).

When some code is sent to REG (A), R
When the MPU 2 detects this because a predetermined bit of EG (A') becomes 1', it accesses REG (A) and receives the instruction code and the like.

At the same time, when the REG(A') force becomes <1°, a start signal "1'" is sent to the timer TM and the timer TM is activated.
Activate.

During this time, the lower MPU 2 analyzes the received code,
As a result, when it is confirmed that the code is the one that should be received, the upper MPUI is notified to that effect.

This notification is performed, for example, by setting a code such as an acceptance w4.11n authorization code in register REG (B).

When the coat is set in REG (B),
Since the predetermined value of 'REG(B') is "]", the upper MPUI detects this by polling REG(B') and sets REG(B') to "O".

Then, take the coat of REG (B) and take Lj.

The operation of the timer TM is stopped by the ``0'' signal of RBG(B') at this time.

Note that if the set time of the timer TM is exceeded during polling of REG (B') by the MPUI, the upper MPU
I detects it and performs predetermined processing.

[Effect]

With the above configuration, starting and stopping of the timer TM is controlled in a heart-like manner by signals from REG (A') and REG (B').

Therefore, timer control can be easily implemented using hardware without the need for a microprogram for starting and stopping the timer.

〔Example〕

Embodiments of the present invention will be described below based on the drawings. Second
The figure is an explanatory diagram of a communication system between microprocessors which is an embodiment of the present invention, and FIG. 3 is an operation flowchart thereof.

1 is the upper MPU (microprocessor), 2 is the lower M
PU and 3 are integrated circuit LSIs, which are provided in, for example, magnetic disk control devices and various control systems, like conventional ones.

For example, it is used to read predetermined information from a magnetic disk or write information to a magnetic disk in response to a command from a host computer.

Inside the LSIa, there is a request register REQ/R(A).
, REQ-R(A'), status register 5TS
-R(B), 5TS-R(B'), random access memory RAM, timer TM, timer register TM-R
EG is provided.

RIEQ-R(A) is the upper MPUI to the lower MPU2.
This is a register that sets codes such as instruction codes to be transmitted to the lower MPU 2, and cannot be written to even if accessed by the lower MPU 2, but can only be read.

When some code is set in this REQ-R(A), a bit for polling monitoring is automatically set to "'1" in REQ-R(A').

REQ-R(A') can only be read from the binary MPUI, so that if the lower MPU2 reads it and it is set to 1, it can be reset to 0 for the next process. It is possible to read and write from the lower MPU 2.

5TS-R (B) is a register that has the same function as RBQ・R (A), in which the lower MPU2 sends the code to be transmitted to the upper MPUI, and the upper MPUI can only read it even if it accesses it. It is.

STS-R(B') has the same function as REQ-R(A'), and a valid code is set in STS-R(B) for the upper MPUI where the lower MPU2 is waiting by polling. This is a register that has a bit that indicates that the

In addition, the 5TS-R (B') can only be read from the lower MPU 2, and when the upper MPUI reads it and detects that a predetermined bit becomes "1", it becomes "0" for the next processing. This is a writable register so that it can be reset to ``.

TM is a countdown timer provided by the upper MPUI to monitor the time of the lower MPU 2.

This timer TM starts when REQ・R(A') becomes "Pa1", and 5TS-R(B') changes from "1" to "0".
It will automatically stop working when it reaches .

TM-REG is a timer register in which the initial value of the timer TM is set, and the timer TM always operates by automatically reading the set value of TM-REG when starting its operation.

The RAM is, for example, a 256-byte random access memory RAM built into the LSI3, and is used by the upper MPUI.
, is accessible from both lower MPU2, and REQ-R
The code set from (A) to STS・R (B) is used when transmitting detailed information to the other party.

This detailed information includes, for example, the trunk position, sector number, and number of sectors of the magnetic disk.

Next, the process will be explained based on the flowchart shown in FIG.

While the lower MPU 2 is polling REQ-R(A'), the upper MPUI sets a timer initial value in TM-REG and sets detailed information such as an instruction code in RAM.

Then, REQ-R(A) is accessed and some code such as an instruction code is sent.

When a code is sent to REQ-R(A), REQ-
R(A') becomes "1", and as a result, "1" is input to the timer TM and activated.

At the same time, the lower MPU 2 detects "1°" of REQ-R(A') by polling, and
While receiving the coat set in R(A),
Receive detailed information in RAM.

After that, the received code is analyzed and the result is s'
Notify the upper MPUI via rs・R(B).

That is, if the lower MPU 2 recognizes that the received code is the one that should be received as a result of the above analysis, it sets a code for receipt confirmation in 5TS-R(B).

When a code is sent to 5TS-R(B), 5TS-
R(B') becomes 1, and the upper MPUI detects this by polling.

When the upper MPUI detects “1” of 5TS-R (B’), the upper MPU1 detects “’1” of STS-R (B’).
is reset to "o" to stop the timer TM, and the code of 5TS-R(B) is received.

Note that when the set time of the timer TM is exceeded during polling of 5TS-R(B') by the higher-level MPUI, this information is notified to the higher-level MPUI, and predetermined processing is performed.

The present invention is not limited to the embodiments described above, but can also be implemented as follows.

The number of CllMPUs is not limited to two, and even if there are more than two, implementation can be made in the same manner as in the above embodiment.

(2) Application is not limited to magnetic disk control devices, but can also be applied to similar devices such as magnetic tape devices, optical disk devices, etc.

〔Effect of the invention〕

As explained above, the present invention has the following effects.

(1) When an upper MPU causes a lower MPU to execute some command, it is necessary for the upper MPU to start or stop a timer for monitoring the time of the lower MPU.

Since such timer control is performed by hardware in the present invention, a conventional microprogram is not required.

Therefore, it is not necessary to create a large amount of complicated microprograms, and the processing time is also reduced, making the overall processing faster and more efficient.

(2) Microprogram processing will be simplified, and the processing capacity of magnetic disk control devices will be significantly improved.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is a configuration diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of the operation of the present invention, Fig. 4 is an explanatory diagram of a conventional example, and Fig. 5 is a diagram of the conventional example. It is an operation explanatory diagram. 1-Upper MPU (microprocessor) 2-Lower MPU 3-=-Integrated circuit (LSI) RE G-m-Register TM-Timer REQ-R-
Request register 5TS-R--Status register TM RE G-Timer register RAM-Random access memory

Claims (1)

[Claims] (1) In a communication method in which registers and timers are arranged between processors to transmit information in a system having multiple processors, a register (A') that starts the timer when information is set from one processor; A communication system between processors, characterized in that a register (B') is provided to stop the timer when information corresponding to the information is set, and to indicate a communication state between the processors.