JPH01305536A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve breakdown strength of cross-under wiring by forming cross-under wiring as a layer in the same process as an isolation layer or a collector wall layer reaching a buried layer through an epitaxial layer. CONSTITUTION:A p<+> layer 11 or a n<+> layer 12 is formed at the same time as impurity diffusion process for an isolation layer or a collector wall layer so that it may reach an n<+> buried layer 3 provided between a p type substrate and an n<-> epitaxial layer 2 laminated thereon. A p<+> layer 13 or an n<+> layer 14 to bring an electrode 7 into contact with the formed cross-under wiring 11 or 12 can be formed at the same time as source and drain regions. When an oxide film 5 is formed by the LOCOS method on the surface after providing the isolation layer and the collector wall layer, the upper sides of the cross- under wirings 11 and 12 formed in the same process are covered with LOCOS oxide films 5 about 1mum thick except the electrode parts 7, and breakdown strength with respect to a cross wiring 9 which is further provided thereon by an Al film with an insulating film is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device in which one of the wirings provided on a semiconductor substrate is crossed under an impurity diffusion layer in the substrate in order to cross the wirings. .

[Conventional technology]

In a semiconductor integrated circuit device, when one of the power supply wirings on the low potential side and the high potential side is formed by an impurity diffusion layer in the substrate in order to cross each other, the source wiring in Bi-CMO3IC is
A diffusion layer formed at the same time as the drain region was used.

FIG. 2 shows the cross-under wiring of such an IC.

That is, an n-epitaxial layer 2 laminated on a p-type substrate 1 has an n1 buried layer 3 between it and the substrate, and is laterally separated by 4 p'isolated layers.

In the isolation region of this n-epitaxial layer 2, a p-channel M
When forming an O3 FET, a p3 source/drain region is provided, and when forming an n channel MO3 FET, a p well is first formed in the n- layer 2 isolation region, and then a p well is formed in the n- layer 2 isolation region.
N'' source/drain regions are provided in the surface layer.

Similar to such source/drain regions, there is a LOC on the surface.
The 91 layer 21 or the N4 layer 22 is formed by diffusion of impurities from the opening of the oxide film 5 formed by the O3 method. This diffusion can be performed in the same step as the diffusion for the p' source/drain region or the n' source/drain region. The surface is then covered with a gate oxide film 6 for forming CMO3, and an electrode 7 is brought into contact with the opening. By connecting the surface wiring to this electrode 7, the p layer 21
Alternatively, the n' layer 22 is used as a cross-under wiring for the wiring 9 made of an M film provided on the insulating film 8 thereon. In addition, in a bipolar IC, as shown in FIG. 3, a p''' paste layer is diffused in a region separated by the p' isolation layer 4 of the n-epitaxial layer 2, and an 01 emitter layer is further diffused therein. Using this diffusion process to form a transistor, a P' layer 23 is formed simultaneously with the P' base layer, or an N+ layer 24 is formed simultaneously with the N1 base layer, in the isolation region of the N- layer 2. This is used as a cross-under wiring. That is, an oxide film 6 is formed on the p+ layer 23 or the n" layer 24.
By bringing the electrode 7 into contact with the surface wiring through the opening of 1.62, the metal wiring 9 on the oxide film 61 thereon is connected.
The wiring will pass under the.

[Problem to be solved by the invention]

In the case of FIG. 2, the oxide film 6 on the 21st layer 21 or the N1 layer 22 of the cross-under wiring is in the CMO3 part,
If defects occur in the semiconductor crystal during the process, or if the properties of the oxide film change, the withstand voltage drops to several tens of cubic meters. Even if an insulating film 8 is laminated on this oxide film 6, its insulating properties are easily influenced by the underlying oxide film 6, and when the withstand voltage of the oxide film 6 decreases, the withstand voltage of the insulating film disappears. If the power supply voltage applied between the cross wirings exceeds the breakdown voltage of the oxide film 6,
There are decisions that result in a serious situation where the power supply is short-circuited.

Even in bipolar ICs, after the base layer and emitter layer are formed, the oxide film covering the surface is thin, so the same p layer 23 is used.
．． The oxide film 61 on the n' layer 24 is also thin and has a similar drawback.

An object of the present invention is to increase the withstand voltage between the cross-under wiring made of an impurity diffusion layer in the substrate and the cross-wire existing on the substrate via an oxide film, and to lower the resistance of the cross-under wiring diffusion layer. An object of the present invention is to provide a semiconductor integrated circuit device.

[Means to solve the problem]

In order to solve the above-mentioned problems, the present invention provides a substrate with a high impurity concentration of a second conductivity type between a substrate of a low impurity concentration epitaxial layer of a second conductivity type laminated on a substrate of a first conductivity type. In a semiconductor integrated circuit device in which semiconductor elements are integrated in a region separated by an isolation layer of the first conductivity type that reaches from the surface of the epitaxial layer to the substrate, the buried layer is reached from the surface in a region other than the element formation region. A high impurity concentration layer of the first or second conductivity type is provided, and a cross-under wiring is formed by contacting two electrodes at a distance on the surface of the layer, and a cross-under wiring is formed between the two electrodes. It is assumed that a wiring that intersects with is provided through an oxide film.

[Effect]

In integrated circuit devices, high impurity concentration layers penetrating the epitaxial layer on the substrate and reaching the buried layer include collector all layers and isolation layers. Since these layers are formed before the step of forming elements in the isolation region, the oxide film thereon is thicker than the gate oxide film on the source/drain region or the oxide film on the base layer and emitter layer. Therefore, if the high impurity concentration layer formed at the same time as the collector all layer or isolation layer is used as a cross-under wiring, no special process is required to thicken the oxide film between it and the overlying cross wiring. . Further, even if the impurity concentration of the collector all layer and the isolation layer is increased, the device characteristics are not affected, so that the resistance of the cross-under wiring formed at the same time can be lowered.

〔Example〕

FIG. 1 shows an embodiment of the Bi-CMO3 IC of the present invention, and parts common to those in FIG. 2 are given the same reference numerals. In this semiconductor integrated circuit device, due to the mask layout, the wiring on the high potential side connected to the VDD terminal is
If the wiring on the low potential side connected to the VB5 terminal intersects, in order to make the wiring on the low potential side a cross under, use p''1ill, which can be formed at the same time as isolation N4, and connect the wiring on the high potential side. In order to form a cross-under, an n layer 12 is used which can be formed simultaneously with the collector all layer of the NPN transistor in the bipolar section.In other words, a p-type substrate and an n-epitaxial N layer laminated thereon are used.
91 so as to reach n embedding N3 provided between 2 and 2.
Layer 11 or n'' layer 12 is formed at the same time as the impurity diffusion process for isolation layer or collector all layer. Electrode 7 to cross-under wiring 11 and 12
The P layer 13 or the N4 layer 14 for contact can be formed simultaneously with the source/drain regions. Bi-0M
In the manufacturing process of the O3 IC, an isolation layer 5 and a collector all layer are provided, and then an oxide film 5 is formed on the surface by the LOCO3 method, and then a p source/drain region N+ source/drain region is provided. Since the channel region is below the middle part of the transistor drain region, the LOGO
It is an isolation layer that is formed in areas where there is no trioxide film and only a thin gate oxide film.

The collector all layer can be covered with a LOGO3 oxide film, and therefore the LOGO3 oxide film, except for the electrode portion 7, is formed on the cross under wiring 11 and 12 formed in the same process.
It can be covered with an oxide film 5. I.

The thickness of the ocos oxide film 5 is approximately 1 p, and 0.1 tn
This is about 10 times the thickness of the oxide film of n. The breakdown voltage between this and the cross wiring 9 provided by the A7 film via an insulating film is about 1000 V, and because the film is thick, it is less susceptible to the effects of process variations. I can always guarantee that. Since the N1 buried layer 13 is provided under the N4 layer 12 formed at the same time as the collector all layer, there is an advantage that wiring resistance is reduced. Furthermore, since the n+ buried layer 3 is provided under the p layer 11 formed at the same time as the isolation layer, the substrate 1 having the same conductivity type
There is an advantage that the potentials of the cross-under wiring 11 and the cross-under wiring 11 can be insulated. Furthermore, as shown in FIG. 2, a p layer 21 is formed simultaneously with the source and drain regions. If the diffusion concentration is increased to lower the sheet resistance value of the n'' layer 22, defects due to ion implantation will increase and the yield will drop sharply.Since the diffusion depth in the source/drain region is shallow, the heat treatment temperature is low and the time is short. Also, the heat treatment has little effect on removing defects.

Therefore, the p+ layer 21. The impurity concentration of the n'' layer 22 cannot be made high.On the other hand, the p'' layer 11 and the n' layer 12, which can be formed simultaneously with the isolation layer and the collector all layer, have a sufficiently deep diffusion depth, so the heat treatment temperature is high and the time is short. The longer it is, the more effective it is to remove defects due to high concentration implantation of impurities.
Moreover, making the isolation layer highly doped reduces interference between the isolation regions of the epitaxial layer 2, and making the collector all layer highly doped has the effect of lowering the collector resistance of the NPN transistor. Therefore, p' layer 11. n”
The diffusion concentration of the layer 12 can be increased more easily than that of the p'' layer 211n'' layer 22, and the resistance value can be lowered.

FIG. 4 shows another embodiment in which the present invention is applied to a bipolar IC, and parts common to those in the previous figures are given the same reference numerals. In this example as well, Bi-0MO3I
Similarly to C, when the wiring on the low potential side is used as a cross-under, the p layer 11 which can be formed at the same time as the isolation layer is used.
When the high-potential side wiring is used as a cross-under, the n layer 12, which can be formed at the same time as the collector all layer, is used. In the electrode portion 7 of the 94 layer 11, a p4 contact layer 13 which can be formed at the same time as the base layer is provided, and in the electrode 7 of the n1 layer 12, an n1 contact layer 14 which can be formed simultaneously with the emitter layer is provided to increase the surface concentration. Bipolar IC
In the oxide film process, the oxide film at the location where diffusion is performed is etched, so the thickness of the oxide film on the diffusion layer in the subsequent process becomes thinner. In particular, the oxide film thickness on the emitter layer is 0.1
~0.2I1m is not enough.

M cross wiring 9 and cross under wiring diffusion layer 11゜12
In order to increase the withstand voltage of the p+ layer 11., the isolation layer and collector all layer, which are diffused before the emitter layer and the base layer, must be added at the same time. Forming the n' layer 12 is advantageous because the oxide film 61 between it and the cross wiring 9 becomes thicker. As explained with reference to FIG.
Similar advantages can be obtained by the presence of the n1 buried layer 3 under the + layer 12.

Diffusion concentration and depth of emitter layer and base layer are NPN
hFE+ is an important parameter for the breakdown voltage of a transistor, and the concentration cannot be easily increased due to the problem of residual defects. On the other hand, the collector-all layer,
The isolation layer can increase the diffusion concentration as appropriate, and in this embodiment as well, the cross under wiring 11.12
resistance value can be lowered.

〔Effect of the invention〕

According to the present invention, a cross under of a semiconductor integrated circuit device
Since the wiring is formed using a layer that can be formed in the same process as the isolation layer or the collector all layer, which penetrates the epitaxial layer and reaches the buried layer, cross-under
The oxide film on the wiring can be made thicker, and the breakdown voltage with the intersecting wiring passing over it is improved. In addition, to form a re-diffusion layer as a cross-under interconnect, long-term high-temperature heat treatment is possible, and high concentration does not deteriorate device characteristics, so it is easy to increase the concentration and reduce interconnect resistance. Can be lowered. Note that the present invention is not limited to those manufactured by the process described in the embodiments, but also includes semiconductor integrated circuit devices in which similar deep cross-under interconnections are formed in different processes.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a wiring intersection of a Bi-CMO3 IC which is an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a Bi-CMO3
FIG. 3 is a sectional view of a wiring intersection in an IC; FIG. 3 is a sectional view of a conventional bipolar IC; FIG. 4 is a sectional view of a bipolar IC according to another embodiment of the present invention. . 1: p-substrate, 2: n-epitaxial layer, 3: n-buried layer, 4: separation layer, 5: LOGO3 oxide film, 6: oxide film, 7: electrode, 9: cross wiring, 11, 12: cross Under wiring, 13, 14: contact layer.

Claims (1)

[Claims] (1) A buried layer with a high impurity concentration of the second conductivity type is provided between the substrate of the low impurity concentration epitaxial layer of the second conductivity type laminated on the substrate of the first conductivity type; In devices where semiconductor elements are integrated in a region separated by an isolation layer of the first conductivity type that reaches from the surface to the substrate, high impurities of the first or second conductivity type that reach the buried layer from the surface in areas other than the element formation region A concentration layer is provided, and a cross-under wiring formed by contacting two electrodes at a distance is provided on the surface of the layer, and a wiring intersecting the cross-under wiring is provided between the two electrodes via an oxide film. A semiconductor integrated circuit device characterized by: