JPH01305374A - Method for testing propagation delay in logic circuit - Google Patents

Abstract

PURPOSE:To test a propagation delay by designating an input terminal FF and an output terminal FF in this order with a first means, changing the state of the input terminal FF with a second means, and receiving the system data of the output terminal FF with a third means. CONSTITUTION:FFs 101, 102 and 103 are sequentially specified with an address coder 111. The FFs are initialized at '0,' '1' and '0.' Then, the FF 101 is specified with the coder 111 in order to change the state of the FF 101. As a scan data, '1' is inputted. When a clock pulse is applied to a first-phase scanning lock pin 17, a changing signal is inputted into a path under test 100. The FF 103 is specified with an address coder 112. A clock pulse is applied to a second phase scanning lock 18 so that system data are received after the elapse of the maximum propagation delay time allowed for the path 100 from the change in signal in the FF 101. When there is no defective propagation delay in the path 100, '1' is taken-in into the FF 103. When there is a defect, '0' is inputted therein. Finally, the state of the FF 103 is observed and judged.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to acceptance testing of logic circuits, and particularly to a circuit structure and testing method suitable for testing propagation delay defects.

[Conventional technology]

Conventionally, regarding propagation delay testing methods for logic circuits, IEtiH, Proceedings of the 14th Fault Tolerant Computing Study Group, pages 146 to 149 (IEtiH, Proc, ofl 4th
FTC3, PP, 146-149).

The above method is particularly provided for propagation delay testing of paths from input pins to flip-flops, from flip-flops to output pins, and from flip-flops to flip-flops. In this,
A propagation delay testing method for paths from flip-flops to flip-flops will be explained using FIGS. 2 to 4.

FIG. 2 shows part of a logic circuit having flip-flops. Flip-flops inside the circuit form a scan structure (in particular, a shift scan structure here) that can easily exchange signals with the outside. When you want to initialize a flip-flop to a specific value, give a value to the scan-in data edge pin 24, turn on and off the two scan clock edge pins 25 and 26 alternately, and store the value in the predetermined flip-flop. . for example.

Flip-flops 211, 212, 213, respectively'
``0'''' 111 II, l (Q The procedure for initializing to 11 will be explained using the time chart of FIG. 3. First, input ``0'' to the scan-in data edge pin 24. ), by turning on and off the first phase scan clock 25 (301-1), '0''' is stored in the flip-flop 211 (311-1).
1). Next, the second phase scanning lock 26 is turned on and off (302-1), and the flip-flop 221 is also turned on.
I Ojl is stored (321-1). Next, input 111" to the scan-in data edge pin 24.
-2), by turning on and off the first phase scan clock 25 (301-2), the flip-flop 211 has #171 (311-2), the flip-flop 212
It OII (312-1) is stored in each.

Turn on and off the second phase scanning lock 26 again (
302-2), the flip-flop 221 has “1” (3
21-2), “O” (32
2-1) respectively. Finally, input 10'' to the scan data edge pin 24 (303-3), and
By turning on and off the phase scan clock 25 (
301-3), the flip-flop 211 has “0” (
311-3), flip-flop 212 has 11” (
312-2), “O” in the flip-flop 213
(313-1) and complete the initialization.

Also, when you want to observe the state of a flip-flop.

The two scan clocks are turned on and off alternately to shift the state of each flip-flop, which is observed from the scan out pin 29. The procedure for shifting the states of the flip-flops is the same as the procedure for initialization described above (however, it is not necessary to take scan data into account), so it will be omitted.

Now, in this circuit, from the output of the flip-flop 211 to the AND gate 203, the output of the flip-flop 211 is
Consider a propagation delay test on the path (hereinafter referred to as the test path) leading to the data input pin of .

Outline the test method. Flip-flop 2 at time to
11 is changed, and the changing signal is sent to flip-flop 2.
13 data input pins (for example, the second input of AND gate 203 to II I I
After the maximum allowable delay time of the test route (this is calculated in advance) has elapsed from the time to, the change in the data input pin of the flip-flop 213 is observed.

Next, the test method will be explained in detail using the time chart shown in FIG. In the test, the first flip-flop 211
, 212, and 213 respectively as “Q II.

Initialize to HI II, 11 Q II. The initialization method is as described above.

When the initialization is completed, the output of the flip-flop 211 is changed using the system clock.

That is, the output of the gate 201 becomes II I II (4
By setting the external input value in advance as shown in 01) and applying the system clock 22 (402),
At time to, the output of the flip-flop 221 is changed from O to 1 (403).

Since the output of the flip-flop 212 is #I II,
The signal change propagates through the path under test and flip-flop 21
3 data input pin (404-1).

404-2).

Therefore, when the system clock 21 is applied so as to store the signal at the data input pin of the flip-flop 213 after the maximum delay time allowed for the path under test has elapsed from the time to (
405), 1'1'' (406-1) is stored in the flip-flop 213 when there is no delay defect in the path under test, and It_OIt (406-2) is stored when there is a delay defect.

Finally, by applying the second phase scan block 26 and writing the state of the flip-flop 213 to the flip-flop 223, the state of the flip-flop 213 is scanned out to the scan-out pin 29 and observed. Determine whether or not there is a defect.

[Problem to be solved by the invention]

The above conventional method has the following two problems.

The first problem is that correct test results cannot be guaranteed in a circuit designed so that the flip-flops before and after the two combinational circuits operate with the same clock (referred to as in-phase transfer). The above example will be illustrated using FIGS. 5 and 6.

FIG. 5 shows flip-flops 501, 502, 503 and AND gates 511, 51 that can scan in/out.
This circuit consists of 2 parts. Among these, flip-flops 50'l and 502 are in-phase transfer.

In this circuit, a propagation delay test of the path from flip-flop 502 to flip-flop 503 will be considered using the time chart shown in FIG. Here, it is assumed that there is no delay defect on the test route.

First, using a scan circuit, the flip-flop 501
, 502 and 503 are each 1”.

# Q IF, initialize to '0''.

Next, in order to input a change signal to the path under test, a clock pulse is applied to the system clock edge pin 51 (6
01). However, if It_OIt appears at the data input pin of the flip-flop 501, the output of the flip-flop 501 changes from "1" to "0" by the above clock pulse (602). When this signal change propagates to the data input pin of flip-flop 502 (603), the system clock edge pin 5
1 has not yet been turned off, the output of the flip-flop 502, which has changed from -at Ou to 111 It, changes again to it On (604-2). Therefore, when applying a clock pulse to the system clock edge pin 52 (605), the flip-flop 503
The data input pin of “1” (606-1)
0” (606-2) appears, stores “0′” and stores (606-2).
07-2) It is determined that there is a delay failure.

Note that during actual operation, a narrower clock pulse is used than during testing, so there is no problem.

The second problem is that generating test patterns takes a lot of effort. The reason for this is that in order to set the data input value of the flip-flop that creates the changing signal and the input value of the flip-flop whose state (output) is to be kept constant, the test pattern is designed in consideration of the combinational circuit parts that do not include the path under test. This is because it generates.

[Means to solve the problem]

The above two problems are the first means of specifying an ordered pair of flip-flops within one circuit, and the system clock and system data for the first flip-flop specified by the first means. A second means for independently changing the state of the flip-flop, and a third means for fetching system data independently from the system clock to the second flip-flop designated by the first means. In the circuit that has been tested, when both the input end and the output end of the path to be tested are flip-flops, specify the input end flip-flop and the output end flip-flop in that order using the first means above. , by changing the state of the input end flip-flop using the second means and propagating the change signal on the path under test, and by taking in the system data of the output end flip-flop using the third means. This is achieved by examining the propagation timing and testing the propagation delay.

[Effect]

In a propagation delay test for a path where the input and output terminals are flip-flops, the flip-flop that creates the changing signal is
Since the first means uniquely specifies the change signal and the second means creates the change signal independently of the system clock, even if there is an in-phase transfer, the states of other flip-flops do not change.

On the other hand, the flip-flop that examines the propagation timing of the change signal is uniquely designated by the first means, and the third means takes in system data regardless of the system clock, so even if there is in-phase transfer, other flip-flops does not cause a change in state.

In addition, when generating a test pattern, the flip-flop that creates the change signal uses the second means to create the change signal regardless of the system data, so the combinational circuit part with the actual operation that does not include the test path is considered. There's no need.

Create a changing signal at the input end for the path under test.

Propagation delay tests can be performed by propagating changes along the path and measuring the timing of the changes at the output end.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1, 7, 8, and 9. The flip-flop used in the circuit of FIG. 1 is an extended flip-flop to which a simple circuit is added as shown in FIG. As shown in FIG. 8, this flip-flop operates in the same manner as the conventional flip-flop (70 in FIG. 7) during actual operation when both scan locks 76 and 77 are in the OFF state (81.degree. 82). However, during a test using a scan clock, when the first phase scan clock 76 or the second phase scan clock 77 is on, the address decode signal 7
If 4 is on, import scan data (83, 84)
, if the address decode signal 75 is on, it has a function of reading system data (85°86). In FIG. 1, in order to utilize the above flip-flop, two address decoders 111 and 112 are installed, and decoded signal lines are connected to address decode signal lines 74 and 75 of each flip-flop, respectively. Further, two scan clocks 17 and 18 are connected to the first phase scan clock signal line (76 in FIG. 7) and the second phase scan clock signal line (77 in FIG. 7) of each flip-flop, respectively. The scan data edge bin 14 is connected to the scan data signal line (73 in FIG. 7) of each flip-flop.

Now, a method for testing the propagation delay of the path 100 from the flip-flop 101 in FIG. 1 to the flip-flop 103 which is in phase with the flip-flop 101 will be described. first,
Flip-flops 101, 102, and 103 are sequentially designated by the address decoder 111, and set to "0" using the scan data edge bin 14 and the first phase scan clock signal 7.

411 II, initialize to IJQj+. next,
In order to change the state of the flip-flop 101, the address decoder 111 specifies this flip-flop 111 (903 in FIG. 9) and reads If 1 as scan data.
904 in FIG. 9) and apply a clock pulse to the first phase scanning block bin 17 (904 in FIG. 9).
1), a change signal is input to the test route 100 (905 in FIG. 9). At this time, the flip-flop 103
A pulse also appears on the first phase scanned clock signal line (
906) in FIG. 9 is not specified by the address decoder 111, so scan data is not taken in. On the other hand, the address decoder 112 specifies the flip-flop 103 (908 in FIG. 9), and the second address decoder 112 designates the flip-flop 103 so that the system data is taken in after the signal changes in the flip-flop 101 and after the maximum allowable propagation delay time of the path under test 100 has elapsed. A clock pulse is applied to the phase scanning block 18 (907 in FIG. 9). If there is no propagation delay defect in the test path 100 (909-1 in FIG. 9), the flip-flop 103 becomes “1”.
” (910-1 in Figure 9), and if there is a defect (910-1),
909-2) The flip-flop 103 takes in 10'' (910-2 in FIG. 9). At this time, a pulse also appears on the second phase scanning clock signal line of the flip-flop 101 (902 in FIG. 9). , address decoder 112
Since it is not specified, system data will not be imported. Finally, by scanning out and observing the state of the flip-flop 103, it is determined whether there is a propagation delay defect.

In the above example, two scan clocks are provided, but if the circuit is designed to reduce the clock skew of the scan clock, the number of external pins can be reduced by using one scan clock. The test method at this time is the above-mentioned first phase scan clock or second phase scan clock.
This method is the same as the above method except that the phase scan clock is operated by one scan clock.

Also, instead of using two address decoders, the 10th
As shown in the figure, the test can also be performed by using one address decoder 1001, a register group 1002 that takes in each signal decoded by this address decoder using a timing signal from a register write enable line 1012, and a register write enable line 1012. It can be carried out. The address decode signal line decoded by the address decoder 1001 is connected to the address decode signal line 74 of each flip-flop shown in FIG.
(or its converse counterpart). The test method is to use address decoder 1001 to initialize the flip-flop.
Alternatively, the information of the address decoder 1001 can be specified by the register group 1002 that stores the information, the flip-flop that changes the signal can be specified by the address decoder 1001, and the flip-flop that takes in the signal can be specified by the address information specified in advance by the address decoder 1001. The method is similar to the above method except that the specification is made using the stored register group 1002 by turning on the register write enable line 1012.6 [Effects of the Invention] According to the present invention, the input terminal of the path on which the propagation delay test is performed is a flip-flop, when changing the state of the flip-flop at the input end of the test path in order to input a change signal to the test path, and when the output end of the test path is a flip-flop, at the output end of the test path. When a change signal is taken into a flip-flop, the states of other flip-flops are not changed, so even if there is in-phase transfer, there is no malfunction.

In addition, when the input end of the test path is a flip-flop, system data is not used to change the state of the flip-flop, which is the input end of the test path, so when determining the test pattern, the stage before the flip-flop that is the input end of the test path No need to consider logic.

Furthermore, since no circuit is added to the system clock system logic, no extra delay occurs during actual operation.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of the present invention, FIGS. 2 and 5 are conventional circuit diagrams, and FIGS. 3 and 4 show the procedure for a conventional propagation delay test of the path in the circuit of FIG. 6 is a time chart showing the procedure of a conventional propagation delay test for the circuit shown in FIG. FIG. 9 is a time chart showing the procedure of the propagation delay test according to the present invention for the circuit shown in FIG. 1, and FIG. 10 is used for a modification of one embodiment of the present invention. It is a circuit diagram. 1...Logic circuit, 11.12...System clock edge pin, 13...System data edge pin, 1
4...Scan data edge pin, 15.16...
Addressing edge pin, 17... 1st phase scan lock edge pin, 18... 2nd phase scan lock edge pin, 19... scan out edge pin, 1
00...Test route, 101-103...Flip-flop, 111, 112...Address decoder, 11
3...Multiplexer. Fig. 1 Fig. 2 Fig. 3 Fig. 7 Rizua 7'h1'223Φout f7
: 323-1 Fig. 4 Stum 70-Noah 22 Fig. 5 Fig. 6 "37 Fig. 9

Claims (1)

[Claims] 1. A first means for specifying an ordered pair of arbitrary flip-flops in the circuit, and a state of the first flip-flop specified by the first means independently of the system clock and system data. A method for testing a propagation delay of a logic circuit, comprising a second means for changing the second flip-flop designated by the first means, and a third means for inputting system data independently of the system clock. and when the input end and the output end of the path to be tested are both flip-flops, specify the input end flip-flop and the output end flip-flop in that order by the first means, and 2
By changing the state of the input end flip-flop using the third means, propagating the change signal on the path, and taking in the system data of the output end flip-flop by the third means, the change signal is changed. 1. A propagation delay testing method for a logic circuit, characterized in that the propagation delay is tested by examining the propagation timing of the logic circuit.