JPH01302979A - Data decoding device - Google Patents

Abstract

PURPOSE:To efficiently decode data by providing a filter to obtain interpolated data by operating only sampled data and a means to output alternately the interpolated data and data before being interpolated. CONSTITUTION:Picture data a-d which were sampled and compressed are inputted from a terminal 11. It is summed with the data having been delayed by one data by a latch 12 by an adder 13, and is multiplied by 1/2 by a coefficient multiplier 14, and the interpolated data (a+b)/2... are obtained. On the other hand, original data not having been operated a-d are supplied to the terminal 16, and the interpolated data (a+b)/2 is supplied to the terminal 15, and they are switched by a switch 17, and by outputting them in the order of (a+b)/2 and (b), interpolated reproduced picture data is obtained. By this constitution, the operation processing speed of an interpolation filter can be the processing speed of 1/2D Hz against the sampling frequency 1/D Hz of the picture data, and the data can be decoded more efficiently without necessitating high speed processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data decoding device that decodes subsampled data.

[Prior Art] Conventionally, when transmitting a large amount of data such as digital image data, in order to reduce the amount of data, subsampling such as a field offset subsampling link or a line offset Sarasampling link is used, as shown in FIG. As shown in (a) and (b), the x image data is thinned out. In order to reproduce the image data that has been reduced between data by subsampling, as shown in Figure 4,
After inserting 0 data between each sample in a 0 data insertion circuit 51, the compressed data is interpolated by passing it through an interpolation filter 52 (post filter) to obtain reproduced data. 53 is a D/A converter for returning this to the original analog signal. As a typical example of a conventional interpolation filter of this kind, a configuration example is shown in FIG. 5 in the case of obtaining interpolated data using a three-tap configuration. In the configuration example shown in FIG. 5, the switch 61 is set to the frequency '/D H7, (D is the time corresponding to the original sampler interval) at the location corresponding to the thinned out data of X in FIG. By switching, the 0 data from the 0 data generation circuit 62 is inserted, and q, 1. Interpolated data is obtained by multiplying and calculating the coefficients of the values.

In the figure, 63.64 is a circuit that delays D data for a time corresponding to the transmission interval between each data from the switch 61 including 0 data, 65, 66.67 are coefficient units, and 68 is an adder.

[Problems to be Solved by the Invention] In the conventional example described above, after inserting 0 data between the sample-printed data, an interpolation filter is applied to generate data with the same sample link period as the data before the sample link. There is a problem in that high-speed arithmetic processing must be performed, which makes it difficult to implement using a heart configuration.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a more efficient data decoding device by configuring a circuit that can obtain interpolated data without requiring high-speed processing.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides an interpolation filter that obtains interpolated data by operating only sample-linked data, and an interpolation filter that alternates between the interpolated data and the data before interpolation. It has a configuration including an output means for switching and outputting.

[Operation] The present invention calculates only sample-linked data through an interpolation filter to obtain interpolated data.
This realizes an interpolation filter configuration that does not require high-speed processing.

[Example] The present invention will be explained below using examples.

FIG. 1(A) is a diagram showing a configuration example of an interpolation filter according to an embodiment of the present invention, and FIG. 1(B) is a time chart schematically showing the operation of FIG. 1(A).

In FIG. 1, 11 is a data input terminal, and 12 is a terminal for delaying the sampled data by one data period of the sampled data, that is, twice the one data period before the sample (2D). 13 is an adder, 14 is a coefficient multiplier, 17 is a switch that changes according to the frequency % DHZ, 15
．． 16 is an input terminal of the switch 17, and 18 is an output terminal.

Further, FIG. 2(a) is a diagram showing sample-linked image data, and FIG. 2(b) is a diagram showing interpolated reproduced image data.

The image data that has been printed and compressed ((i) in FIG. 1 (b)) is input from the terminal 11, and the latch 12
The l data is added to the delayed data ((ii) in the same figure) in the adder 13 ((iii) in the same figure), and is expanded or multiplied by the coefficient unit 14 to obtain interpolated data ((iV) in the same figure). .

On the other hand, the raw data (the first
(i) in Figure 2 (B) is supplied, and interpolated data (for example, a' = (a + b) in Figure 2 (B)) is supplied to the terminal 15.
/2) is output, so by switching the switch 17 and outputting in the order of a' and b in Fig. 2 (b),
Obtain interpolated playback image data.

As described above, by configuring the interpolation filter, the calculation processing speed of the interpolation filter is 1/2 Hz relative to the image data sampler frequency '/DHZ, and high-speed processing is not required. The hardware configuration is also simpler.

FIG. 3 is a diagram showing an example of the configuration of a 3×3 tap interpolation filter according to the present invention.

401 is a data input terminal, 402 and 403 are delay lines that delay by a period of lH±D, 404, 407 and 409 are adders respectively, 405, 408 and 410 are each coefficient units, and 406 is one data of sampled data. A latch that delays for a period (2D) corresponding to , 413 is a switch for switching between raw data and interpolated data that are not subjected to calculations, 411
and 412 are the input terminals of the switch 413, and 41
4 is an output terminal.

When data is input from the input terminal 401 (d in Figure 2 (b)), data delayed by 2H by the delay lines 402 and 403 (c in Figure 2 (b)) is input.
are added in an adder 404, and multiplied by a factor in a coefficient unit 405 to obtain vertical interpolation data a''.On the other hand, the delay line 40
The data delayed by the IH-D period (b in FIG. 2 (b)) by the latch 406 and the data delayed by the period 2d (a in FIG. 2 (b)) by the latch 406 are added to the adder 407. The vertical interpolation data a'' and the horizontal interpolation data a'' are added together by an adder 409 and multiplied by a coefficient multiplier of 408 to obtain horizontal interpolation data a''. 41
0 is multiplied by 0 to obtain interpolated data (Fig. 2 (a')).The switch input terminal 412 receives the raw data (Fig. 2 (b) b) is output, and the interpolated data (a' in Fig. 2 (b)) is output to the switch input terminal 411.
By switching and outputting a' and b in this order, interpolated reproduced image data can be obtained.

In the case of a 3.times.3 tap interpolation filter, which requires high-speed processing using the above-mentioned configuration, it is also possible to simplify the heart configuration by using a hit shift in the coefficient unit.

The configuration of the interpolation filter in the above embodiment is to sequentialize color difference lines,
Furthermore, it can be applied to TCI image data, and it is an embodiment of the present invention to add a delay element for 2H to the configuration shown in FIG. 3 and to switch and process the luminance signal and color difference signal. .

Furthermore, this interpolation filter can also be used for data with 0 data inserted.

[Effects of the Invention] As explained above, the configuration of the interpolation filter of the present invention allows the calculation processing speed of the interpolation filter to be increased by performing calculations only on the sample-linked data and outputting it in chronological order along with data that is not subjected to calculations. simplification of the heart configuration.

This has great effects in terms of performance and economy due to the complexity of arithmetic processing.

[Brief explanation of the drawing]

FIG. 1(A) is a diagram showing a configuration example of an interpolation filter according to an embodiment of the present invention, FIG. 1(B) is a time chart of FIG. 1(A), and FIG. FIG. 3 is a diagram showing the configuration of a 3×3 tap interpolation filter embodying the present invention. FIG. FIG. 5 is a block diagram showing the structure of an interpolation filter, and is a diagram showing an example of the structure of a conventional 3-tap interpolation filter. In the figure. 11.401 Data input terminal 12.406: 1 data delay element 402.403
: IH delay element 13.404, 407, 409 Adder 17.61,
413: Selector switch 14.405, 408, 410 Coefficient unit 18.414
: Output terminal agent Patent attorney 1) Haru Kitatake

Claims (1)

[Claims] An interpolation filter that obtains interpolated data by calculating only the subsampled data in a device that receives and decodes subsampled digital data;
A data decoding device characterized by comprising an output means for alternately switching and outputting the interpolated data and the data before interpolation.