JPH05268575A - Inter-field interpolation picture element generating method and circuit - Google Patents

Abstract

PURPOSE:To improve the resolution in the vertical direction with simple configu ration with respect to the inter-field interpolation picture element generating method and its circuit in which an inter-field interpolation picture element is generated from a still picture luminance signal subjected to inter-frame interpo lation and a signal resulting from delaying the still picture luminance signal by one field in the still picture luminance signal reproduction processing in a MUSE decoder. CONSTITUTION:A 2nd still picture luminance signal SB resulting from delaying a 1st still picture luminance signal SA subjected to inter-frame interpolation by one line is delayed by one line and an average value between the 2nd still picture luminance signal SB and a signal delaying the signal SB by one line is calculated by an arithmetic operation circuit 35, a difference between the 1st still picture luminance signal and the average value is calculated to eliminate the high frequency component included in the difference and the sum of the average value and the difference with the high frequency component eliminated therefrom is calculated by an adder circuit 39 to generate an inter-field interpolation picture element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inter-field interpolated pixel from a still picture luminance signal interpolated between frames and a signal obtained by delaying this signal by one field in a still picture luminance signal reproduction process in a MUSE decoder. The invention relates to an interfield interpolation pixel generation method and a circuit thereof.

[0002]

2. Description of the Related Art In a still picture luminance signal reproduction process in a MUSE decoder, an interfield interpolation pixel generation circuit (two-dimensional filter) as shown in FIG. 6 is used.

The still picture luminance signal SA is a signal of the current field obtained by an inter-frame interpolation circuit (not shown),
Among the still image luminance signals of four fields forming the reproduced image, the still image luminance signal of the current field and the still image luminance signal of one frame before (two fields before) are interpolated. On the other hand, the still image brightness signal SB is a signal obtained by delaying the still image brightness signal SA with a 1-field delay circuit.

The still image brightness signal SA is supplied to the adder 10 as a still image brightness signal SA3 via the 1-line delay circuit 11 and the filter 12, and is supplied to the 1-line delay circuits 11 and 13.
And is supplied to the adder 10 as the still image luminance signal SA2 via the filter 14 and the 1-line delay circuits 11, 13, 1
It is supplied to the adder 10 as a still image luminance signal SA1 via the filter 5 and the filter 16.

The still image brightness signal SB is supplied to the adder 10 as a still image brightness signal SB4 via the filter 20,
It is supplied to the adder 10 as a still image brightness signal SB3 via the 1-line delay circuit 21 and the filter 22, and is supplied to the adder 10 as a still image brightness signal SB2 via the 1-line delay circuits 21 and 23 and the filter 24 to be supplied to 1 line. It is supplied to the adder 10 as a still image brightness signal SB1 via the delay circuits 21, 23, 25 and the filter 26.

The adder 10 receives the still picture luminance signal SA.
1 to SA3 and SB1 to SB4 are added and output as a still image luminance signal of the interpolated pixel PM shown in FIG. In the figure, pixels PA11 to PA16 are pixels of the still image brightness signal SA1, and pixels PB11 to PB16 are still image brightness signals SB1.
Pixels. The straight line in the figure indicates that the still image brightness signal of the interpolated pixel PM is created by multiplying the brightness signal value of the pixel on this line by a constant and adding the result.
The constants are the filters 12, 14, 16, 20, 22,
Multiplied by 24 and 26.

However, the circuit shown in FIG. 6 is large in scale and needs to be processed at high speed with a clock frequency of 48.6 MHz, resulting in high cost and high power consumption.

In order to solve such a problem, an inter-field interpolation circuit as shown in FIG. 8 is used.

The still image luminance signal SA of 32.4 MHz is
It is supplied to the 32/48 MHz clock rate conversion circuit 30 and converted into a still image luminance signal of 48.6 Hz, and then supplied to the synthesis circuit 31. On the other hand, the still image brightness signal SB obtained by delaying the still image brightness signal SA by one field is 32/48.
48. MHz supplied to the MHz clock rate conversion circuit 32.
After being converted into a still image brightness signal SB of 6 Hz, it is supplied to the vertical filter 33.

The vertical filter 33 is an inter-field interpolation pixel generation circuit which is a simplified circuit of the circuit of FIG. 6, and comprises a 1-line delay circuit 34 and an average value calculation circuit 35. The average value calculation circuit 35 calculates the average value of the still image brightness signal from the 32/48 MHz clock rate conversion circuit 32 and the still image brightness signal obtained by delaying the still image brightness signal by 1 line by the 1 line delay circuit 34, and the result is obtained. Is supplied to the synthesis circuit 31.

The synthesizing circuit 31 synthesizes the output of the 32/48 MHz clock rate converting circuit 30 and the output of the average value calculating circuit 35 in synchronization with the luminance sampling phase signal SS and interpolates a still picture luminance signal SC. Is output.

In the above structure, the vertical filter 33 is
As shown in FIG. 9, the pixel PB11 of the still image brightness signal SB1
Signal value (SB11) and the still image brightness signal S one line before
The average value with the signal value (SB21) of the pixel PB21 of B2 is calculated, and this is output as the signal value of the interpolation pixel PC11. The synthesizing circuit 31 uses the pixel PA1 of the still image luminance signal SA
The signal value of 1 is output, and then the signal value of the interpolation pixel PC11 is output. Next, the vertical filter 33 calculates the average value of the signal value of the pixel PB12 of the still image luminance signal SB1 and the signal value of the pixel PB22 of the still image luminance signal SB2 one line before, and calculates this as the signal of the interpolation pixel PC12. Output as a value.
The synthesizing circuit 31 outputs the signal value of the pixel PA12 of the still image luminance signal SA, and then outputs the signal value of the interpolated pixel PC12. The same processing is performed thereafter.

However, since the still picture luminance signal SB passed through the vertical filter 33 is simply interpolated into the still picture luminance signal SA, the vertical resolution deteriorates.

[0014]

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide an inter-field interpolated pixel generation method and circuit capable of improving the vertical resolution with a simple structure. Especially.

[0015]

Means for Solving the Problem and Its Action The interfield interpolated pixel generating method and its circuit according to the present invention will be described with reference to the reference numerals of the corresponding constituent elements in the embodiments.

In this interfield interpolation pixel generation method, a field is generated from a first still picture luminance signal SA interpolated between frames and a second still picture luminance signal SB obtained by delaying the first still picture luminance signal SA by one field. For generating interpolated pixels, delaying the second still image luminance signal SB by one line,
The second still image brightness signal SB and the second still image brightness signal SB are set to 1
The average value with the line-delayed one is calculated, the difference between the first still image luminance signal SA and the average value is calculated, the high frequency component of the difference is removed, and the average value and the high frequency component of the difference are calculated. The interpolated pixel is generated by calculating the sum with the removed one.

The interfield interpolated pixel generation circuit according to the present invention is for implementing the above method, for example, as shown in FIG.
As shown in FIG. 1, a 1-line delay circuit 34 that delays the second still image brightness signal SB by 1 line, and an average value calculation circuit 3 that calculates an average value of the input value and the output value of the 1-line delay circuit 34.
5, a subtraction circuit 37 for calculating a difference between the first still image luminance signal SA and the average value, a high frequency component reducing means 38 for restricting passage of a high frequency component of the difference, and an output of the average value calculation circuit. An adding circuit 39 for calculating the sum with the output of the high frequency component reducing means 38 is provided.

1-line delay circuit 34 and average value calculation circuit 3
The vertical filter 33 composed of 5 is supplied with the second still image luminance signal SB having a frequency spectrum as shown in FIG. The frequency spectrum of the output of the vertical filter 33 is as shown in FIG. 4B, and the resolution in the vertical direction is deteriorated as compared with that of the second still image luminance signal SB. Since the frequency spectrum of the first still image luminance signal SA is almost the same as that of FIG. 4A, the frequency spectrum of the output of the subtraction circuit 37 is the frequency spectrum of FIG. 4A as shown in FIG. 4C. From which the frequency spectrum of FIG. 4 (B) is subtracted. That is, the signal of the vertical resolution deterioration portion which is not included in the output of the vertical filter 33 is obtained from the subtraction circuit 37. When the output of the subtraction circuit 37 passes through the high frequency component reducing means 38, the result is as shown in FIG. 4 (D), and the folded portion in FIG. 4 (C) that causes the image quality deterioration is removed. As shown in FIG. 4E, the output of the adder circuit 39 becomes a frequency spectrum obtained by combining FIG. 4B and FIG. 4D.

In this way, the portion having good vertical resolution contained in the frequency spectrum of the first still picture luminance signal SA is placed in the resolution deterioration portion not included in the frequency spectrum of the output of the vertical filter 33. The obtained signal is obtained from the adding circuit 39, and the resolution in the vertical direction can be improved with a simple configuration.

In the first aspect of the interfield interpolation pixel generation method according to the present invention, the high frequency component is removed by passing the difference through a low pass filter.

In the second aspect of the interfield interpolation pixel generation method according to the present invention, the high frequency component is removed by reducing the difference in accordance with the value of the non-linear edge signal SN.

The non-linear edge signal SN is a signal indicating the degree of non-linear emphasis. The larger this value is, the higher the frequency of the signal at that time is, and the S / N is higher than that of other parts. It's getting worse. Therefore, for example, when the value of the non-linear edge signal SN is equal to or larger than a predetermined value, the input signal is reduced by multiplying the difference by a constant smaller than 1 or a value proportional to the reciprocal of the non-linear edge signal SN. When the difference is equal to or less than the predetermined value, the high frequency component can be removed by keeping the difference as it is.

In the first aspect of the inter-field interpolation pixel generation circuit according to the present invention, the high frequency component reducing means is a low pass filter 38 for limiting the passage of the high frequency component of the difference.

In this case, the structure is simple.

In the second aspect of the inter-field interpolation pixel generating circuit according to the present invention, the high frequency component reducing means reduces the difference according to the value of the non-linear edge signal SN to pass the high frequency component of the difference. It is a high frequency band reduction circuit 40 for limiting.

In the third aspect of the inter-field interpolation pixel generating circuit according to the present invention, the high frequency component reducing means includes the low pass filter 38 and the high frequency region reducing circuit 40.

In the case of this configuration, even if the high frequency portion which is the folded portion cannot be sufficiently removed due to the poor characteristics of the low pass filter 38, this can be removed by the high frequency reduction circuit 40. ..

[0028]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows a schematic structure of a still picture luminance signal reproducing circuit. In addition, FIG.
The pixel array of each field of the image divided into fields is shown.

The still image luminance signal SX of 16.2 MHz is 1
The still image luminance signal SY is supplied to the frame delay circuit 1 and the still image luminance signals SX and SY are supplied to the inter-frame interpolation circuit 2 and inter-frame interpolated 32.4 MHz.
A still image luminance signal SA of z is created. For example, if the still image luminance signal SX is the signal of the pixel of the first field in FIG. 3, the still image luminance signal SY is the signal of the pixel of the third field, and the still image luminance signal SA is the pixel of the first field and the pixel of the first field. This is a signal in which pixels of three fields are arranged in this order.

In FIG. 2, the still image luminance signal SA is supplied to the 1-field delay circuit 3 to be a still image luminance signal SB, and the still image luminance signals SA and SB are supplied to the inter-field interpolation circuit 4 to generate a field. The interpolated still image luminance signal SC is created. The still image brightness signal SB is shown in FIG.
3 is a signal in which the pixels of the third field and the pixels of the fourth field are arranged in this order, and the still image luminance signal SC is a still image luminance signal SA and a still image luminance signal SB in FIG.
This is a 48.6 MHz signal in which the pixels with missing marks are interpolated.

[First Embodiment] In the first embodiment of the present invention,
The inter-field interpolation circuit 4 of FIG. 2 is constructed as shown in FIG. The same components as those in FIG. 8 are designated by the same reference numerals and the description thereof will be omitted.

In this inter-field interpolation pixel generation circuit,
The 32/48 MHz clock rate conversion circuit 32 and the vertical filter 33 of FIG. 8 are connected in reverse order, and the 32/48
MHz clock rate conversion circuit 32 and vertical filter 33
A pseudo two-dimensional filter 36 is connected between the
The still image luminance signal SA is supplied to the dimensional filter 36. The other points are the same as in FIG.

The pseudo two-dimensional filter 36 includes a subtraction circuit 37 for calculating the difference between the still image luminance signal SA and the output of the vertical filter 33, a low-pass filter 38 to which the output of the subtraction circuit 37 is supplied, and a low-pass filter 38. The addition circuit 39 is configured to calculate the sum of the output and the output of the vertical filter 33. The output of the addition circuit 39 is supplied to the synthesis circuit 31 via the 32/48 MHz clock rate conversion circuit 32.

Next, the operation of the first embodiment constructed as described above will be explained based on the frequency spectrum shown in FIGS. 4 (A) to 4 (E). In FIG. 4, the horizontal axis represents the horizontal frequency (MHz), and the vertical axis represents the vertical frequency in units of TV lines. This frequency spectrum is
The transmittable area of the luminance signal and the folded spectrum are shown.

The vertical filter 33 is supplied with a still picture luminance signal SB having a frequency spectrum as shown in FIG. The frequency spectrum of the output of the vertical filter 33 is
As shown in FIG. 4B, the resolution in the vertical direction deteriorates as compared with that of the still image luminance signal SB. Still image brightness signal S
Since the frequency spectrum of A is almost the same as that of FIG. 4A, the frequency spectrum of the output of the subtraction circuit 37 is as shown in FIG.
As shown in FIG. 4C, the frequency spectrum shown in FIG. 4A is obtained by subtracting the frequency spectrum shown in FIG. That is, the signal of the vertical resolution deterioration portion which is not included in the output of the vertical filter 33 is obtained from the subtraction circuit 37. The output of the subtraction circuit 37 is the low-pass filter 38.
As shown in FIG. 4 (D), the folded portion in FIG. 4 (C), which causes image quality deterioration, is removed. The output of the adder circuit 39 is, as shown in FIG.
The frequency spectrum is a combination of (B) and FIG. 4 (D).

In this way, a signal in which the portion with good vertical resolution contained in the frequency spectrum of the still image luminance signal SA is placed in the resolution-degraded portion not included in the frequency spectrum of the output of the vertical filter 33. Is pseudo 2
Obtained from the dimensional filter 36.

The still picture luminance signal SA and the output of the pseudo two-dimensional filter 36 are supplied to the 32/48 MHz clock rate conversion circuits 30 and 32, respectively, and converted into a still picture luminance signal of 48.6 Hz. Each of the 32/48 MHz clock rate conversion circuits 30 and 32 is a sampling frequency conversion circuit, and outputs a signal that has been passed through a low-pass filter and sampled at 48.6 Hz.
32/48 MHz clock rate conversion circuits 30 and 32
The output of is supplied to the synthesizing circuit 31, and the still image luminance signal SC interpolated between fields and having a vertical resolution higher than that of the conventional one is obtained.

[Second Embodiment] In the second embodiment of the present invention,
The inter-field interpolation circuit 4 of FIG. 2 is constructed as shown in FIG. The same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In this inter-field interpolation pixel generation circuit,
A pseudo two-dimensional filter 36A is used instead of the pseudo two-dimensional filter 36 of FIG. Pseudo two-dimensional filter 36A
Connects a high-frequency band reduction circuit 40 between the low-pass filter 38 and the adder circuit 39, and controls the output of the low-pass filter 38 with a non-linear edge signal SN as described later. That is, the low-pass filter 38 and the high-frequency region reduction circuit 40 connected in cascade are used as the high-frequency component reducing means. Then, the adder circuit 39 calculates the sum of the output of the high frequency band reduction circuit 40 and the output of the vertical filter 33. The other points are the same as in FIG.

Here, in the MUSE encoder, pre-emphasis processing is performed in order to improve the SN ratio of the high frequency components of the signal. This pre-emphasis processing causes overshoot and undershoot (whiskers) at the edge portion of the signal. In order to prevent the whiskers from exceeding the RF bandwidth of the transmission line, non-linear emphasis processing is performed to compress the height of the whiskers exceeding the RF bandwidth. The MUSE decoder performs the reverse process, that is, the process of expanding the beard portion subjected to the non-linear emphasis process. For this reason, the noise on the beard part will be expanded. The non-linear edge signal SN is a signal indicating the degree of this non-linear emphasis. The larger this value is, the higher the frequency of the signal at that time is, and the S / N becomes worse than the other parts. ing.

Therefore, when the value of the non-linear edge signal SN is equal to or larger than a predetermined value, the high frequency band reduction circuit 40 uses a constant smaller than 1 or the non-linear edge signal S for the input signal, for example.
The input signal is reduced by multiplying it by a value proportional to the reciprocal of N. If the value of the non-linear edge signal SN is less than the predetermined value, the input signal is output as it is.

As a result, even if the high-frequency portion, which is the folded portion, cannot be sufficiently removed due to the poor characteristics of the low-pass filter 38, this can be removed by the high-frequency reduction circuit 40.

The other points are the same as those of the first embodiment.

[0045]

As described above, in the interfield interpolation pixel generation method and the circuit according to the present invention, the second still image luminance signal SB is delayed by one line to generate the second still image luminance signal SB and the second still image luminance signal SB. An average value of the image luminance signal SB delayed by one line is calculated, a difference between the first still image luminance signal SA and the average value is calculated, a high frequency component of the difference is removed, and the average value is calculated. Since the interpolated pixel is generated by calculating the sum of the difference and the high-frequency component removed, the still image luminance signal is included in the vertical resolution deterioration portion not included in the average value frequency spectrum. A signal with a good vertical resolution included in the SA frequency spectrum can be obtained, which has the excellent effect that the vertical resolution can be improved with a simple configuration, and the cost of HDTV can be reduced. And low consumption Which greatly contributes to Chikaraka.

In the first aspect of the inter-field interpolation pixel generation circuit according to the present invention, the high frequency component reducing means is constituted by a low pass filter for limiting the passage of the high frequency component of the difference, so that the configuration is simplified. Has the effect.

In the third aspect of the inter-field interpolation pixel generation circuit according to the present invention, the high frequency component reducing means is configured to reduce the output value of the low pass filter according to the value of this low pass filter and the nonlinear edge signal SN. Since it is composed of a reduction circuit, even if the high frequency part that is the folded part cannot be sufficiently removed due to the poor characteristics of the low-pass filter, it can be removed by the high frequency reduction circuit. Has the effect.

[Brief description of drawings]

FIG. 1 is an inter-field interpolation pixel generation circuit diagram of a first embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a still image luminance signal reproduction circuit.

FIG. 3 is a pixel array diagram of each field of an image divided into four fields by a MUSE encoder.

FIG. 4 is a frequency spectrum diagram showing a signal processing process of the circuit of FIG.

FIG. 5 is an inter-field interpolation pixel generation circuit diagram of a second embodiment of the present invention.

FIG. 6 is a conventional inter-field interpolation pixel generation circuit diagram.

7 is an explanatory diagram of inter-field interpolation pixel generation processing by the circuit of FIG.

FIG. 8 is a conventional inter-field interpolation circuit diagram.

9 is an explanatory diagram of inter-field interpolation processing by the circuit of FIG.

[Explanation of symbols]

30, 32 32/48 MHz clock rate conversion circuit 31 synthesis circuit 33 vertical filter 34 1 line delay circuit 35 average value calculation circuit 36, 36A pseudo two-dimensional filter 37 subtraction circuit 38 low-pass filter 39 addition circuit 40 high frequency region reduction circuit SX, SY , SA, SB, SA1-SA3, SB1-S
B4 still image luminance signal SN non-linear edge signal SS luminance sampling phase signal PM, PC11, PC12 interpolation pixel PA11, PA12, PB11, PB12, PB21,
PB22 pixel

Claims (7)

[Claims] 1. An inter-field interpolation pixel from a first still image luminance signal (SA) interpolated between frames and a second still image luminance signal (SB) obtained by delaying the first still image luminance signal by one frame. In the inter-field interpolation pixel generation method for generating, the second still image luminance signal is delayed by one line, and the average of the second still image luminance signal and the second still image luminance signal delayed by one line. A value is calculated, a difference between the first still image luminance signal and the average value is calculated, a high frequency component of the difference is removed, and a sum of the average value and the high frequency component of the difference removed is calculated. Then, the interfield interpolation pixel generation method is characterized by generating the interfield interpolation pixel. 2. The interfield interpolated pixel generation method according to claim 1, wherein the high frequency component is removed by passing the difference through a low pass filter (38). 3. The interfield interpolated pixel generation method according to claim 1, wherein the removal of the high frequency component is performed by reducing the difference according to the value of the non-linear edge signal (SN). 4. An inter-field interpolated pixel based on a first still image luminance signal (SA) interpolated between frames and a second still image luminance signal (SB) obtained by delaying the first still image luminance signal by one field. In the inter-field interpolated pixel generation circuit for generating a 1-line delay circuit (34) that delays the second still image luminance signal by 1 line, and calculate an average value of the input value and the output value of the 1-line delay circuit. An average value calculation circuit (35), a subtraction circuit (37) that calculates a difference between the first still image luminance signal and the average value, and a high frequency component reduction means (38) that restricts passage of a high frequency component of the difference. , 40) and an adder circuit (39) for calculating the sum of the output of the average value calculation circuit and the output of the high-frequency component reducing means, and an interfield interpolation pixel generation circuit. 5. The inter-field interpolated pixel generation circuit according to claim 4, wherein the high-frequency component reducing means is a low-pass filter (38) for restricting passage of the high-frequency component of the difference. 6. The high frequency component reducing means is a high frequency band reduction circuit (40) for limiting the passage of the high frequency component of the difference by reducing the difference according to the value of the non-linear edge signal (SN). The inter-field interpolation pixel generation circuit according to claim 4, wherein 7. The high-frequency component reducing means limits the passage of the high-frequency component of the difference by a low-pass filter (38).
And a high frequency band reduction circuit (4) that reduces the output value of the low-pass filter according to the value of the nonlinear edge signal (SN).
0) and are included, The interfield interpolation pixel generation circuit according to claim 4 characterized by the above.