JPH04207670A - Edge emphasis circuit - Google Patents

Abstract

PURPOSE:To correct the contour of both a horizontal component and a vertical component and to improve the picture quality by implementing deficient sharpness of a picture of the NTSC system converted from the MUSE system by a converter by means of digital signal processing. CONSTITUTION:A horizontal edge correction section 3 and a vertical edge correction section 2 of a converter converting a digital signal of the MUSE system into a digital signal of the non-interlace NTSC system act like so-called second-order differentiating, the horizontal edge correction section 3 of the edge emphasis circuit detects an edge in the horizontal component and outputs an emphasis component and the vertical edge correction section 2 detects an edge in the vertical component and outputs an emphasis component. Both the outputs are added by adders 5,7, the output is given to a coring/gain adjustment section 6, in which coring and gain adjustment are implemented and the result is converted into an original luminance signal. Thus, the contour correction is applied to a digital luminance signal by the digital signal processing to improve the picture quality.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is a converter that converts the MUSE system (high-definition) to the non-interlaced NTSC system by interpolating the MUSE signal and converting it to the non-interlaced NTSC system.
Digital luminance signal or MU after conversion to C format
The present invention relates to an edge enhancement circuit that detects edge portions in the horizontal and vertical components of a digital luminance signal after interpolating an SE signal, and performs so-called contour correction to enhance the edge portions through digital signal processing to improve image quality.

[Conventional technology]

Conventionally, converters that convert MUSE format to NTSC format convert clear images from MUSE format to NTSC format, so even after conversion, there is no need to perform contour correction because the band is wider than normal NTSC format. It was considered.

[Problem to be solved by the invention]

However, when an image is actually reproduced using the converter, it is undeniable that the image is insufficiently clear despite the wide band as described above.

SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks, it is an object of the present invention to provide an edge emphasis circuit that improves image quality by correcting the contour of a digital luminance signal through digital signal processing.

[Means to solve the problem]

The present invention provides a converter for converting a MUSE digital signal into a non-interlaced NTSC digital signal, which converts the MUSE digital signal into a digital luminance signal or a MUSE digital signal after the MUSE digital signal is interpolated and converted into the non-interlaced NTSC digital signal. Detects the edge part in the vertical component of the digital luminance signal after interpolation, and outputs the emphasized component and outputs the digital luminance signal to the horizontal edge correction section which delays the digital luminance signal by one horizontal period (1H). A correction unit detects an edge part in the horizontal component of the luminance signal from the vertical edge correction unit and outputs the emphasized component and outputs the luminance signal from the vertical edge correction unit for a time twice the clock signal period (2D
); a first delay circuit that delays the signal from the vertical edge correction section to optimize the phase with the original luminance signal; a first adder that adds the signal from the first delay circuit and each emphasis component from the horizontal edge correction section; and a coring that reduces noise and adjusts the gain of the signal from the first adder and outputs the signal. The present invention provides an edge enhancement circuit comprising a gain adjustment section and a second adder that adds the signal from the coring/gain adjustment section and the luminance signal from the horizontal edge correction section and outputs the result. .

[Effect]

The horizontal edge correction section detects an edge portion in the horizontal component of the luminance signal and outputs an emphasis component of the portion, and the vertical edge correction portion detects an edge portion in the vertical component of the signal and outputs an emphasis component of the portion. Output the components. Both outputs are added by an adder, and the resulting output is cored and gain adjusted and added to the original luminance signal. Note that the horizontal edge correction section and the vertical edge correction section perform a so-called second-order differential action.

〔Example〕

Hereinafter, an edge enhancement circuit according to the present invention will be explained based on the drawings. FIG. 1 is a block diagram of a main part of an embodiment of an edge enhancement circuit according to the present invention.

In the figure, 1 is a digital luminance signal input terminal after interpolating a MUSE digital signal and converting it into a non-interlace NTSC format, or a digital luminance signal input terminal after interpolating the MUSE digital signal, and 2 is the input terminal I. a vertical edge correction section that detects an edge part in a vertical component in a digital luminance signal of the digital luminance signal and outputs an emphasized component and an output to a horizontal edge correction section that delays the digital luminance signal by one horizontal period (1H); detects the edge part in the horizontal component of the luminance signal from the vertical edge correction section 2, and outputs the emphasized component and the luminance signal from the vertical edge correction section for a time twice the clock signal period (
2D), a horizontal edge correction section that outputs the output to the second adder delayed by 2D); 4 is a first delay circuit that delays the signal from the vertical edge correction section 2 and optimizes the phase with the original luminance signal; 5 is a first adder that adds the signal from the first delay circuit 4 and each emphasized component from the horizontal edge correction section 3;
A coring/gain adjustment eye 6 outputs the signal from the first adder 5 by reducing noise and adjusting the gain.A coring/gain adjustment eye 7 outputs the signal from the coring/gain adjustment section 6 and the luminance signal from the horizontal edge correction section 3. 8 is an output terminal for an edge-emphasized signal, and 9 is a second adder for outputting the digital luminance signal from the input terminal 1 with a delay of one horizontal period (1H). 10 is a signal output terminal from the second delay circuit 9 which is connected to the input signal of the horizontal edge correction section 3;
11 is a third delay circuit that further delays the signal from the second delay circuit 9 by 1H time and outputs the signal; 12 is a third delay circuit that outputs the digital luminance signal from the input terminal 1 by multiplying it by -1/4; 1 is a constant multiplier circuit, 13 is a second constant multiplier circuit that multiplies the signal from the second delay circuit 9 by +1/2, and 14 multiplies the signal from the third delay circuit 11 by -1. 15 is the output signal from the first constant multiplier circuit 12 and the second constant multiplier circuit 13.
A third adder adds and outputs the output signal from the output terminal 10 and the output signal from the third constant multiplier circuit 4. )
17 is a signal output terminal from the fourth delay circuit 16 which outputs the signal delayed by the second adder 7; 18 is a signal output terminal from the fourth delay circuit which outputs the signal after delaying it by 2
19 is a fourth constant multiplier circuit that outputs the signal from the output terminal 10 by multiplying it by -1/4; 20 is the signal from the fourth delay circuit; 5th constant multiplier circuit that multiplies the signal by plus 1/2 and outputs the signal, 21
22 is a sixth constant multiplier circuit that multiplies the signal from the fifth delay circuit by minus 1/4 and outputs the signal, and 22 is a fourth constant multiplier circuit 1.
9, the output signal from the fifth constant multiplier circuit 20, and the output signal from the sixth constant multiplier circuit 21, and outputs the result.

Next, the process of horizontal edge enhancement based on the above configuration will be explained as an example. FIG. 2(A) is a correlation diagram showing the correlation between each point (Hl to Hl) shown in the horizontal edge correction unit 3 of FIG. 1, the signal, and the level when the input signal is a rectangular wave. Figure (B) is a correlation diagram illustrating the correlation between the input original signal and the edge-enhanced signal based on the results of the second Ik (A) in terms of waveforms.

Figure 2 (A) Smell τ square wave human power (point)) 11)
It is assumed that the level changes from "0" to "A" at each temporal position of (2) to (2), where ID is one interval. Also H2
is delayed by 2D from H1 by the fourth delay circuit 16, and H3
becomes a signal delayed by 2D from H2 by the fifth delay circuit 18. Therefore, Hl, H2, and H3 become as shown in the figure.

The signal at H2 is also the original luminance signal to which the edge enhancement component described below is added. As shown in the figure, H1, H2, and H3 are multiplied by constants in respective constant multiplier circuits. Here, the reason why each constant of each constant multiplier circuit is set to the above value is to set the Hl signal to "0" in the part where there is no change in the luminance signal and edge enhancement is not necessary, and also because the discrete form of the second-order differential is set to "0". This is because when circuitized, it becomes the constant.

This constant is supplied to the first constant multiplier circuit 12 of the vertical edge correction section 2.
The same applies to the third constant multiplier circuit 14. As a result, H4, H5, and H6 become as shown in the figure, and when these are added, a signal output shown as Hl is obtained. Figure 2 (B) shows H2 for point HL, and edge emphasis component (H7).
) indicates the signal output (horizontal component only) at the output terminal 8 that is added to the H2 signal by the second adder 7. As shown in the signal output waveform, the edges of the rectangular wave are emphasized.

The edge enhancement effect for the vertical component is performed in the same way as for the horizontal component, but the principle is the same, so the explanation will be omitted. The actual signal output from the output terminal 8 is an output that includes edge enhancement for the vertical component as well as edge enhancement for the horizontal component described above. The purpose of the gain adjustment in coring/gain adjustment 6 is to obtain a visually appropriate correction amount for contour correction.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to correct the lack of sharpness of an image converted from MUSE format to NTSC format by a converter by correcting the contours of both horizontal and vertical components by digital signal processing, thereby improving image quality. It is effective and greatly contributes to improving the performance of the converter and the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a main part of an embodiment of an edge enhancement circuit according to the present invention, and FIGS. 2(A) and 20(B) are correlation diagrams showing the correlation between an input signal and an output signal. In the figure, l is a digital luminance signal input terminal, 2 is a vertical edge correction section, 3 is a horizontal edge correction section, 4 is a first delay circuit, 5 is a first adder, 6 is a coring/gain adjustment section, 7
is the second adder, 8.10.17 is the output terminal, and 9 is the second adder.
, 11 is a third delay circuit, 12 is a first constant multiplier, 13 is a second constant multiplier, 14 is a third constant multiplier, 15 is a third adder, and 16 is a third constant multiplier. 4 delay circuits, 1
8 is a fifth delay circuit, 19 is a fourth constant multiplier, 20 is a fifth constant multiplier, 21 is a sixth constant multiplier, and 22 is a fourth adder. Patent applicant: Fujitsu General Ltd.

Claims (3)

[Claims] (1) In a converter that converts a MUSE digital signal into a non-interlaced NTSC digital signal, the MUSE digital signal is interpolated and converted into the non-interlaced NTSC digital luminance signal or the MUSE digital signal. a vertical edge correction unit that detects an edge part in the vertical component of the interpolated digital luminance signal and outputs the emphasized component and the digital luminance signal to a horizontal edge correction unit that delays the digital luminance signal by one horizontal period; Detecting an edge portion in the horizontal component of the luminance signal from the vertical edge correction section, and delaying the output of the emphasized component and the luminance signal from the vertical edge correction section by a time twice the clock signal period and performing a second addition. a horizontal edge correction section that outputs the signal from the vertical edge correction section, a first delay circuit that delays the signal from the vertical edge correction section and optimizes the phase with respect to the original luminance signal; a first adder that adds each emphasized component from the horizontal edge correction section; a coring/gain adjustment section that reduces noise and adjusts the gain of the signal from the first adder and outputs the signal;
An edge enhancement circuit comprising a second adder that adds the signal from the coring/gain adjustment section and the luminance signal from the horizontal edge correction section and outputs the result. (2) In the vertical edge correction section, the second luminance signal is delayed by one horizontal period time as an input signal and outputted.
and the signal from the second delay circuit.
A third delay circuit delays the signal by a horizontal period and outputs the signal; a first constant multiplier circuit multiplies the luminance signal by minus 1/4 and outputs the signal; 2
A second constant multiplier circuit that multiplies and outputs the signal, a third constant multiplier circuit that multiplies the signal from the third delay circuit by minus 1/4 and outputs the signal, and an output signal from the first constant multiplier circuit. and a third adder that adds the output signal from the second constant multiplier circuit and the output signal from the third constant multiplier circuit and outputs the result. Edge enhancement circuit. (3) In the horizontal edge correction section, a fourth delay circuit that uses as an input signal a signal obtained by delaying the luminance signal by one horizontal period, and outputs the signal delayed by twice the clock signal period; A fifth delay circuit further delays the signal from the delay circuit by twice the clock signal period and outputs the signal, and a signal delayed by 1H time from the luminance signal is output by -1.
A fourth constant multiplier circuit that multiplies the signal by /4 and outputs the signal, a fifth constant multiplier circuit that multiplies the signal from the fourth delay circuit by plus 1/2 and outputs the signal, and Signal minus 1
Add the output signal from the fourth constant multiplier circuit, the output signal from the fifth constant multiplier circuit, and the output signal from the sixth constant multiplier circuit. and a fourth adder that outputs the
1) Edge enhancement circuit described.