JPH01296824A - A/d converter - Google Patents

Abstract

PURPOSE:To eliminate a conversion error and to improve a conversion accuracy by providing a means to hold a voltage corresponding to an input analog signal, execute a prescribed operation with the voltage and constant from a reference current source and obtain a digital signal. CONSTITUTION:When a third switch S3 is on, a capacitor C of an integrator 1 is shorted, the integrator 1 becomes a resetting condition and an output voltage Vout becomes 0V. Next, when a first circuit S1 is on for a constant time, an input voltage Vin is given to the integrator 1 and integrated. The output voltage Vout of the integrator 1 becomes larger at the inclination in proportion to the size of the input voltage Vin and after a constant time passes, becomes the prescribed voltage. Next, when a second circuit S2 is on, the integrator 1 is reverse-integrated by constant current I0 and i0 and the voltage Vout approaches to 0V. A high order counter CU1, when S2 is on, simultaneously starts the counting action of a clock. When the voltage Vout arrives at a prescribed voltage, the inverse of Vth, a comparator 4 is detected, a microprocessor 60 receives this, the S2 is off and the counting of the counter CU1 is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION (#, Field of Industrial Application) The present invention relates to a two-stage (cascade) integration type A/D converter, and more specifically, it first holds a voltage corresponding to an input voltage, Next, the discharge period (inverse integration period) of this integrated voltage is divided into two by a constant current from the reference current source, and the first half is rapidly inversely integrated, and the second half is smoothly integrated. The present invention relates to an A/D converter using the A/D converter method.

(Prior Art) FIG. 6 is a block diagram showing the configuration of a conventional A/D converter of this type. In the figure, 1 is an integrator consisting of an amplifier AP and an integrating capacitor C8H, SL is a switch for applying the input voltage VIN to be converted to the input terminal of the integrator 1 via an input resistor R1, and RS H is an It is a feedback resistance. 2 and 3 are constant currents IO,t of different values, respectively.
The constant current sources S2 and S3 that output the constant current source 2.3 are switches for applying the constant current IO and to from the constant current source 2.3 to the input end of the integrator 1, respectively.

4 and 5 are comparators that compare the output voltage V out of the integrator 1 with a predetermined voltage -vth and a common voltage, respectively; 6
is a digital circuit which inputs the signals from each comparator 4.5, and is internally provided with, for example, a 9-bit upper counter cui and a 7-bit lower counter CU2. This digital circuit 6 controls the switches 81 to S3 and obtains digital signals from each counter.

FIG. 7 is a timing chart showing the operation of this device. First, switch S1 is turned on (switches S2 and S3 are off) as shown in (b). As a result, the integrator 1 includes the feedback resistor R3H and constitutes an inverted sample-and-hold circuit, and the capacitor C8H of the integrator 1 receives the voltage obtained by dividing the input voltage VIN into two by the input resistor R1 and the feedback resistor RSH. It is held as shown in (a).

Next, turn off switch S1 and turn off switches S2 and S3 (c)
and turn on as shown in (d). At the same time, the upper counter CUI configured in the digital circuit starts counting as shown in (e). As shown in (a), the output voltage Vout of the integrator 1 is a constant current l011
0, it approaches the common voltage (0■) at a constant slope.

Here, when the output voltage V out of the integrator 1 reaches a predetermined voltage -vth, the comparator 4 detects this and the digital circuit 6 turns off the switch S2 as shown in (c). . At the same time, the upper counter CUI stops counting, and the lower counter CtJ2 configured in the digital circuit 6 starts counting, as shown in (f).

The integrator 1 is now discharged only by the constant current 10, and its output voltage Vout eventually crosses Ov. Comparator 5
detects this, and the digital circuit 6 stops counting by the lower counter CU2 at this point.

A certain relationship is established between the constant current source IO and the IO, for example, (I O + i 0 ) / i 0 = 2', and the upper counter CUI and lower counter CU2 are connected in series. By connecting to the 9-bit counter, one count of the 9-bit counter is weighted 27 times as much as one count of the 7-bit counter. Therefore, by connecting the upper counter C1J1 and the lower counter CU2 in series, it is possible to obtain 16-bit A/D conversion data.

(Problems to be Solved by the Invention) In the conventional device configured as described above, in order to sample and bold the input voltage VIN prior to the A/D conversion operation,
Switches S2 and S3 must be kept off between time tO and t1, and at time t1, switches S2 and S3 must be kept off at the same timing.
It is necessary to turn on two switches S2 and S3.

However, two independent switches S2 and S3,
It is not easy to turn them on at the same time, and there is also the problem that the leakage current of the switch S3 and the resistance when it is turned on interfere with the conversion error.

The present invention has been made in view of these problems, and its purpose is to eliminate the switch S3, solve the problems caused by the existence of the switch S3, and provide A with high conversion accuracy.
/D converter.

(Means for Solving the Problems) FIG. 1 is a basic block diagram of the present invention. In FIG. 2 is a reference voltage source, R1 is a first resistor, S2 is a first switch means for supplying a reference voltage -Vr from the reference voltage source 2 to the integrating means 1 through the first resistor R1; A second switch, R2, is a second resistor connected between the reference voltage source 2 and the input end of the integrating means 1; S3 is a third switch connected in parallel with the capacitor C forming the integrating means 1; 4 is a first unit that compares the output from the integrating means 1 with a predetermined voltage −Vth.
5 is a second comparative means for comparing the output from the integrating means 1 with the common voltage, 6 is a comparing means 4.5 for these.
input the signal from the first to third switches 81 to 81.
In addition to controlling the on/off of S3, the second switch S
2 is turned on until the output of the first comparator 4 is inverted, and the time from the time when the output of the first comparator 4 is inverted to the second
This is a digital circuit that counts the time until the output of the comparator 5 is inverted and performs predetermined calculations to obtain a digital signal.

(Function) By turning on the third switch S3, the integrator 1
By discharging the electric charge of the capacitor C and turning on the first switch S1, the input signal VIN to be converted is integrated, and by turning on the second switch S2, the integrator 1 is integrated with a steep slope. The output voltage Vout
By making the output voltage approach the common voltage and turning off the second switch S2, the output voltage is made to approach the common voltage with a gentle slope.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. In FIG. 0, the same parts as those in FIG. 1 are denoted by the same reference numerals.

In the figure, 60 is a microprocessor that inputs signals from each of the first and second comparators 4.5, which includes an upper counter CUI, a lower counter CU2, and control means for the first to third switches. CN 'l', a clock generating means CK for applying to each counter, and an arithmetic means CP for performing a predetermined operation using the count value of each counter to obtain a digital signal.

The operation of the apparatus configured in this way will be explained next.

FIG. 3 is a timing chart showing an example of the operation.

First, the third switch S3 is turned on as shown in (b). As a result, both ends of the capacitor C of the integrator 1 are short-circuited, the integrator 1 is placed in a reset state, and its output voltage Vout becomes 0■ as shown in (a).

Next, the first switch S1 is turned on for a certain period of time TS (the count value of the counter during this period is assumed to be N1) as shown in (c). As a result, the input voltage VIN is applied to the input terminal of the integrator 1 and is integrated. Output voltage Vo of integrator 1
ut increases with a slope proportional to the magnitude of the input voltage VIN, and the output voltage v1 after a certain period of time TS is (1)
Expressed by the formula.

(1) However, T is a constant value for one clock, and N1 is the count number between time tO and t1.Then, the second switch S2 is turned on as shown in (d). As a result, the integrator 1 is inversely integrated by the constant current IO and 10 as shown in (a), and its output voltage V
out approaches OV with a large slope. At this point, the second switch s2 is turned on, and at the same time, the upper counter CUI starts clock counting operation. Output voltage V of integrator 1
Out.

reaches a predetermined voltage -vth, the first comparator 4 detects this. In response to this, the microprocessor 6° turns off the second switch s2 and stops counting by the upper counter CUI.

At the same time, the counting operation of the lower counter CU2 is started as shown in (f).

At time t3 when the output voltage Vout of the integrator 1 reaches a predetermined voltage -vth, the output voltage v2 of the integrator 1 becomes (-2
) is expressed by the formula.

......(2) However, N2 is the count value at time t2 to t3. When the second switch S2 is turned off, the integrator 1 is set to the constant current 1.
Since it is inverse integrated only by 0, its output voltage V o
u t approaches 0■ with a gentle slope, and eventually Ov
Cut into a tank as shown in (a). The second ratio controller 2 detects this and stops the counting operation of the lower counter CU2 at this point.

Here, between the constant currents 10 and 10, (IO+i0
)/1o=2, and one count of the upper counter C1J1 is weighted twice as much as that of the lower counter CtJ2.

Time t4 when the output voltage Vout of integrator 1 crosses Ov
Then, the output voltage v3 of the integrator 1 is expressed by equation (3).

The integral value from time t1 to time t2 and the time t when the output voltage V out of integrator 1 crosses 0 from time t2
Since the integral values up to 4 have the same absolute value as shown in (a), equations (1), (2), and (3) to equation (4) hold true.

Here, 1o=Vr/R2, If RO=R1, Equation (4) is expressed by equation (5).

However, I O = V r / R1 (IO + i0) / 1o = 2' (n is an integer) The calculation means CP in the microprocessor 60 calculates the digital signal corresponding to the input signal VIN by performing the calculation of equation (5). I can get a signal.

FIG. 4 is a block diagram showing another embodiment of the present invention. The embodiment shown in FIG. 2 assumes that the input signal VIN is a positive voltage; however, in this embodiment, the input voltage VIN is a positive voltage.
In order to handle the case where IN is a negative voltage, the resistor R3 and the fourth
The positive reference voltage source 7 is connected to the input terminal of the integrator 1 via the switch S4.

FIG. 5 is a timing chart showing the operation of the embodiment shown in FIG. Before integrating the input signal VIN, as shown in (e), the fourth switch S4 is turned on for a certain period of time, and a period ° is provided during which the reference voltage Vr is integrated. The other operations are the same as in FIG. 3.

(Effects of the Invention) As explained in detail above, the present invention has a configuration that eliminates the switch that turns on and off the minute type 'aiO, which was present in the conventional device. It is possible to eliminate conversion errors caused by changes in leakage current and on-resistance, and the fact that two switches are not turned on at the same time, and it is possible to realize an A/D converter with high conversion accuracy.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration block diagram of the present invention, FIG. 2 is a configuration block diagram showing one embodiment of the present invention, FIG. 3 is a timing chart showing an example of operation, and FIG. 4 is a basic configuration block diagram of the present invention. FIG. 5 is a timing chart showing its operation. Reference numeral 6121 is a block diagram of the structure of a conventional device, and FIG. 7 is a timing chart of its operation. 1... Integrator 2... Reference voltage source 4... First comparator 5... Second comparator 6... Digital circuit

Claims (1)

[Claims] Integrating means; first switching means for supplying an input analog signal to be converted to the integrating means for a certain period of time; a reference voltage source; a second switch for applying a reference voltage to the integrating means; a second resistor connected between the reference voltage source and the input end of the integrating means; and a second resistor connected in parallel with the capacitor constituting the integrating means. a third switch connected to the integrator; a first comparator that compares the output from the integrator with a predetermined voltage; and a second comparator that compares the output from the integrator with a common voltage; A signal from a comparing means is inputted to control on/off of the first to third switches, and a time period from when the second switch is turned on until the output of the first comparator is inverted. and a digital signal that counts the time from when the output of the first comparator is inverted until the output of the second comparator is inverted, and performs a predetermined operation using these counted values to obtain a digital signal. An A/D converter with a circuit.