JPH01296663A - Optoelectronic integrated circuit - Google Patents

Abstract

PURPOSE:To contrive a flattening of the surface of an optoelectronic integrated circuit device by a method wherein a semi-insulative InP layer is selectively formed on an InP substrate in such a way as to bury an optical element formed on the substrate in the InP layer and an electronic element is formed on this semi-insulative InP layer. CONSTITUTION:A semiconductor layer 2, which uses an epitaxial layer 10 laminated with a dissimilar material as an operating layer, is formed on an InP substrate 1 and a semi-insulative InP layer 3 is selectively formed on the substrate 1 in such a way as to bury the layer 2 in its periphery. Moreover, the thickness of the layer 3 is formed in the same thickness as that of the layer 2 and a field-effect transistor 4 is formed on the surface of the layer 3. Moreover, the transistor 4 is one that uses an epitaxial layer 5 as an operating layer and a gate electrode 6 is formed on the layer 5. Thereby, the surface of the semi-insulative InP layer, on which an electronic element is formed, and the upper end part of the optical element are formed in the almost same height and the surface of an optoelectronic integrated circuit device is flattened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an optoelectronic integrated circuit (OEIC) in which semiconductor optical elements and electronic elements are integrated on one substrate.

[Conventional technology]

An optoelectronic integrated circuit is a circuit in which an electronic element such as a field effect transistor is placed adjacent to an optical element that performs photoelectric conversion, and the two are electrically connected. , July 11, 1986,'' its structure is disclosed.

[Problem to be solved by the invention]

Incidentally, an optical element performs optical functions such as generating and absorbing light, and for this purpose, it is necessary to have a heterojunction structure in which different materials are laminated.

This heterojunction structure is formed using epitaxial growth technology, and since it is a multilayer structure, it has a thickness of several μm.
It becomes thicker than that.

On the other hand, electronic devices such as field effect transistors require only a single material because electrons run through the surface layer, and are formed directly on the substrate surface by ion implantation, etc., or by using a single epitaxial layer. It is very thin, less than 1 μm.

As a result, a step is created on the surface between the optical element and the electronic element.
This step hinders microfabrication, and furthermore, there is a problem in that wiring breaks and the like occur at the step.

An object of the present invention is to solve these problems.

[Means to solve the problem]

In order to solve the above problems, the optoelectronic integrated circuit of the present invention has the following features:
An optical element is formed on an InP substrate, a semi-insulating InP layer is selectively formed on the InP substrate so as to embed the optical element, and an electronic element is formed on the semi-insulating InP layer. It is.

[Effect]

The surface of the semi-insulating InP layer on which the electronic element is formed and the upper end of the optical element are approximately at the same height, and the surface is flattened.

〔Example〕

FIG. 1 is a sectional view showing one embodiment of the present invention, and FIG. 2 is a sectional view showing the manufacturing process thereof.

As shown in FIG. 1, the optoelectronic integrated circuit of this embodiment has an I
A semiconductor laser 2 is formed on an nP substrate 1, and has an epitaxial layer 10 laminated with different materials as an operating layer.
A semi-insulating InP layer 3 is selectively formed on the InP substrate 1 around it so as to embed the semiconductor laser 2 therein. The thickness of the semi-insulating InP layer 3 is the same as that of the semiconductor laser 2, and a field effect transistor 4 is formed on its surface. The field effect transistor 4 uses an epitaxial layer 5 as an active layer, and a gate electrode 6 is formed on the epitaxial layer 5. Reference numerals 7 to 9 indicate wiring layers, in which the wiring 7 is connected to the lower electrode of the semiconductor laser 2, the wiring 8 is connected to the upper electrode of the semiconductor laser 2 at one end, and the field effect transistor 4 is connected at the other end. is connected to one ohmic electrode of the Further, the wiring 9 is connected to the other ohmic electrode of the field effect transistor 2. Note that the optoelectronic integrated circuit of this example uses semi-insulating In as a buried layer.
Since the P layer is used, the field effect transistor 4 formed on this layer can have good characteristics.

Next, the manufacturing process of the optoelectronic integrated circuit having such a configuration will be explained with reference to FIG.

An epitaxial layer 10 having a heterojunction structure and serving as an operating layer of a semiconductor laser 2 is formed on an InP substrate 1 . Then, a silicon nitride film 11 is formed thereon to be used later as an etching mask (see FIG. 2(A)).

Next, a resist 12 is applied onto the silicon nitride film 11, and this resist 12 is patterned using normal photolithography. Thereafter, the silicon nitride film 11 is etched using the patterned resist 12 as a mask (see FIG. 2(B)).

Next, unnecessary epitaxial layer 10 is removed by performing reactive ion etching or wet etching using patterned resist 12 and silicon nitride film 11 as masks (FIG. 2(C)).

Next, after removing the resist 12, a semi-insulating InP layer 3 is selectively formed only on the InP substrate 1 by, for example, metal organic vapor phase epitaxy using trimethylindium, phosphine (PH3), and ferrocene as raw materials. do(
Figure 2 (D)). Note that this growth method produces semi-insulating In
It is already known that the P layer 3 can be selectively formed on the InP substrate 1.

Next, an epitaxial layer 5 for a field effect transistor 4 is formed on the semi-insulating InP layer 3 (FIG. 2(E)).
.

Thereafter, the portions of the epitaxial layer 5 which are unnecessary for the field effect transistor 4 are etched, and furthermore, ordinary electrode forming techniques are applied to form the optoelectronic integrated circuit shown in FIG.

Note that the field effect transistor 4 of this embodiment may be a junction FET, a two-dimensional electronic transistor, etc., but is not limited thereto. Furthermore, electronic devices are not limited to field effect transistors, but include, for example, heterojunction bipolar transistors (HB T
) etc. can also be used.

Furthermore, in this embodiment, a semiconductor laser, which is a light emitting element, is used as an example of an optical element, but other light emitting elements such as a light emitting diode may be used. It can also be an optoelectronic integrated circuit.

〔Effect of the invention〕

As explained above, according to the optoelectronic integrated circuit of the present invention,
The surface of the semi-insulating InP layer on which the electronic device is formed and the top end of the optical device are approximately at the same height and the surface is flattened, making microfabrication possible and increasing the degree of integration and performance. I can do it. Furthermore, since there is no step between the optical element and the electronic element, disconnections between the two are eliminated, and the manufacturing yield rate can be significantly improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing one embodiment of the present invention, and FIG. 2 is a sectional view showing an embodiment of the present invention.
FIG. 2 is a sectional view showing the manufacturing process of the embodiment shown in FIG. 1; 1... InP substrate, 2... semiconductor laser, 3...
Semi-insulating InP layer, 4... field effect transistor, 7
~9...Wiring. Patent applicant: Sumitomo Electric Industries, Ltd. Representative patent attorney Yoshiki Hase
Salt 1) Cross-sectional structure of Tatsuya Example Fig. 2

Claims (1)

[Claims] 1. An optical element is formed on an InP substrate, a semi-insulating InP layer is selectively formed on the InP substrate so as to embed the optical element, and a semi-insulating InP layer is formed on the semi-insulating InP layer. An optoelectronic integrated circuit in which electronic elements are formed. 2. The optoelectronic integrated circuit according to claim 1, wherein the semi-insulating InP layer is selectively formed by metal organic vapor phase epitaxy.