JPH01296618A - Heat treatment of iii-v compound semiconductor substrate - Google Patents

Abstract

PURPOSE:To make it possible to conduct a highly uniform heat treatment having a few deformation and crystal defects in a short period by a method wherein a substrate is heat-treated in the state wherein the circumferential part of a III-V compound semiconductor substrate is continuously supported by a supporting means. CONSTITUTION:A 2-inch GaAs substrate 3 is continuously supported on the circumferential part only by the Si supporting member 4 provided in a quartz glass furnace core tube 2. The heating by a halogen lamp 1 is started in the above-mentioned state, and a heat treatment is conducted for a short period. To be more precise, as the contact between the substrate 3 and the supporting member 4 is limited to the circumferential part only of the substrate 3, and as it is continuously supported, the effect of the supporting member 4 in the center part of the substrate is removed, and at the same time, stress is dispersed by its own weight due to a continuous supporting. As a result, an active layer having excellent uniformity can be obtained while the generation of deformation and crystal defects of the substrate 3 is being suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for heat treating a ■-V group semiconductor substrate, and more particularly to a method for uniformly heat treating a ■-V group semiconductor substrate.

[Prior Art and its Problems] In recent years, as the development of high-speed digital integrated circuits using ■-v group semiconductors has progressed, the importance of short-time annealing methods has been increasing.

In other words, ion implantation is performed for the purpose of reducing contact resistance in the manufacturing process of heterojunction devices such as heterojunction bipolar transistors and heterojunction field effect transistors. A heat treatment method that does not cause significant crystal damage to dissimilar junctions is required. The currently most suitable method for this purpose is the short-time annealing method. The annealing method is also suitable for forming shallow, highly doped active layers, which are important for improving the performance of field-effect transistors. That is, it is known that by using this method, not only the redistribution of impurities in the active layer can be suppressed, but also a high electrical activation rate can be obtained.

Normally, as a method for short-time annealing of an ion-implanted ■-V group semiconductor substrate, as shown in FIG. A method of installing it on the pin 35 is known. In the figure, 31 is a lamp, and 32 is a quartz glass furnace tube. However, when the substrate supporting method shown in FIG. 3 is used, the stress due to the weight of the ■-V group semiconductor substrate 33 is concentrated on the portion of the substrate that contacts the quartz support pins 35. For that, e.g. 900'C
When heat treatment is performed for a short time at a high temperature exceeding It has the disadvantage that crystal defects are easily introduced.

[Means for Solving the Problems] The present invention provides a ■-V group semiconductor substrate, characterized in that heat treatment is performed on the ■-V group semiconductor substrate while the peripheral portion of the substrate is continuously supported by a support tool. This is a heat treatment method.

[Operation] In the present invention, for example, an ion-implanted -V group semiconductor substrate is heat-treated by continuously supporting only the peripheral portion using a support tool.

■-Contact between the group V semiconductor substrate and the support is limited to the periphery of the substrate, and the substrate is continuously supported. Unlike support, the influence of the support at the center of the board is eliminated, and the stress due to its own weight is dispersed by continuous support.

Therefore, an active layer with excellent uniformity can be obtained while suppressing deformation of the substrate and introduction of crystal defects.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

In this example, a sample in which 5 x 1012 cm-2 of 29Si+ is implanted at 100 keV and at room temperature into a semi-insulating 2-inch GaAs substrate with plane orientation <100> without any impurities will be described. InP, I
nGaAs.

AI! The present invention is similarly applicable to ■-v group semiconductor substrates such as GaAS, #InAS, and InGaASP. Further, the dimensions of the substrate will be explained using a 2-inch diameter substrate as an example in this embodiment, but the same principle can be applied to substrates of different diameters.

As shown in Figure 1, the 2-inch GaAs to be annealed
The substrate 3 is continuously supported only at its peripheral portion by a Si support 4 installed in the quartz glass furnace tube 2. In this state, heating from the halogen lamp 1 was started, and a short-time heat treatment was performed at 950'C for 15 seconds. After the heat treatment, the deformation of the substrate and the occurrence of crystal defects were examined using an optical microscope and X-ray topography, but no abnormality was observed in the sample. FIG. 2 shows the distribution of sheet resistance in the radial direction within the substrate surface in a sample obtained by short-time heat treatment according to the method of the above embodiment. As can be seen from the figure, in this example, a uniform sheet resistance force A5 was obtained, and the variation in the sheet resistance value in the radial direction was within 3%.

Therefore, by using the method of the present invention, the deformation of the substrate and the occurrence of crystal defects during short-time heat treatment can be suppressed to a minimum compared to conventional methods, and the variation in the activation rate of implanted ions within the substrate surface can be suppressed to a sufficiently small level. It was confirmed that

[Effects of the Invention] As explained above, according to the heat treatment method of the present invention, highly uniform short-time heat treatment with less substrate deformation and crystal defects due to heat treatment can be performed even on large-diameter m-v group semiconductor substrates. realizable.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram for explaining one embodiment of the present invention, FIG. 2 is a diagram showing the distribution of sheet resistance in the substrate surface inner radial direction in a sample obtained by the method of the present invention, and FIG. FIG. 3 is an explanatory diagram showing a short-time heat treatment method. 1... Halogen lamp 2.32... Quartz glass furnace tube 3... 2 inch GaAs substrate

Claims (1)

[Claims] (1) A method for heat treatment of a III-V group semiconductor substrate, characterized in that heat treatment is performed on the III-V group semiconductor substrate while the peripheral portion of the substrate is continuously supported by a support.