JP3001513B2 - Manufacturing method of semiconductor wafer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for diffusing impurities into a semiconductor wafer, and more particularly to a method for manufacturing a semiconductor wafer in an impurity diffusion step.

[0002]

2. Description of the Related Art In semiconductor devices such as semiconductor integrated circuits, many devices are formed on the surface of a semiconductor wafer in a wafer process, and are finished by repeating pattern formation and heat treatment. Such a semiconductor wafer is a single crystal and has a structure in which atoms are arranged in an orderly manner. However, when heat treatment is performed at a high temperature, slip occurs on a crystal surface due to a temperature difference or a surface state. When this slip occurs, the electrical characteristics become poor, or a low-quality semiconductor device with a large amount of leak current results. Various methods have been proposed to solve this phenomenon.
Related art will be described.

[0003] First, with reference to Japanese Patent Application Laid-Open No. 58-207642 (hereinafter referred to as "Document 1") with reference to FIG. The high-concentration carbon region 11 is formed by ion implantation or the like so that the concentration becomes 10% or more. As a result, a technique is described in which crystal defects formed in the high-concentration carbon region 11 on the outer peripheral portion of the silicon substrate 1 prevent propagation of slip extending from the outermost periphery of the silicon substrate 1.

In Japanese Patent Application Laid-Open No. 58-74044 (hereinafter referred to as "Document 2"), a slip from an outer peripheral portion, which is likely to be generated due to a temperature difference in a plane of a semiconductor wafer during a heat treatment, has a uniform width. By mechanically forming a strained layer or recess with a depth of and by dispersing or absorbing in that part even if stress is applied to a certain crystal plane orientation,
Techniques are described for preventing slip from extending into the interior.

In Japanese Patent Application Laid-Open No. Sho 62-143432 (hereinafter referred to as "Document 3"), only an outer peripheral portion of a semiconductor wafer which is most susceptible to thermal stress contains N atoms which increase the mechanical strength of Si. There is described a technique for suppressing slippage. In Japanese Patent Application Laid-Open No. 1-274420 (hereinafter referred to as "Document 4"), high-concentration impurities are introduced in the vicinity of the outer periphery of a substrate to form a layer having a high light absorptivity, thereby suppressing the generation of slip lines. The technology is described.

In Japanese Patent Application Laid-Open No. 1-274422 (hereinafter referred to as "Document 4"), a film (tungsten) made of a material having a high light absorptivity is deposited near the outer periphery of a substrate to suppress the generation of slip lines. The technology to do this is described. In Japanese Patent Application Laid-Open No. 3-66114 (hereinafter referred to as "Document 6"), the outer peripheral portion of a semiconductor wafer that is in contact with a quartz basket is matted to improve heat dissipation, and is accommodated in the quartz basket. A technique is described in which thermal distortion of a semiconductor wafer is prevented from occurring at the same time and slip is suppressed.

[0007]

However, when the above-mentioned prior art is used, the following problems remain. In Document 1, crystal defect nuclei are generated by doping with a high concentration of carbon, and the slips extend toward the center of the semiconductor wafer as a starting point, which may result in a low-quality semiconductor element. In Document 2, since the method of forming the processing strain layer or the concave portion is mechanically formed using a diamond pen or the like,
Conversely, in the processing step, the outer peripheral portion of the semiconductor wafer is weakened, and if heat treatment or the like is performed in that state, the semiconductor wafer may be broken in the furnace core tube during heat treatment, or chipping may occur, which may cause equipment trouble. .

Further, in Reference 3, a method of implanting N ions for increasing the mechanical strength of Si only into the outer peripheral portion of a semiconductor wafer which is most susceptible to the effect of thermal stress is disclosed in Reference 4.
The method of forming a layer having a high light absorption by introducing a high concentration of impurities into the outer periphery of a semiconductor wafer is disclosed in Reference 5, and a film (tungsten) made of a material having a high light absorption is deposited on the outer periphery of the semiconductor wafer. To be disclosed. The common point of these documents is that the outer periphery of the semiconductor wafer is
This means that some impurities are introduced or deposited to suppress the slip generated during the heat treatment.

For this purpose, it is necessary to add a photolithographic process to the current process. As a result, there is a concern that the construction period will be prolonged and the unit price of the semiconductor wafer will increase. In addition, by implanting N ions into the outer peripheral portion of the semiconductor wafer, introducing high-concentration impurities, and depositing a film (tungsten) made of a material having a high light absorption rate, if impurities enter the product area, The area becomes defective, and the product yield may be deteriorated. Reference 6
The same applies to the case where the satin-finished region reaches the product region. An object of the present invention is to provide a method for easily avoiding the occurrence of slip without introducing or depositing impurities or the like on the outer peripheral portion of a semiconductor wafer as described above, and to manufacture a semiconductor wafer for a high-performance semiconductor device. To make it possible.

[0010]

For this purpose, a method for manufacturing a semiconductor wafer according to the present invention comprises the steps of:
In the region where the impurity diffusion layer on the surface is formed.
To prevent slip during diffusion of impurities.
An oxide film having a sufficient thickness for the semiconductor wafer.
Diffusion mask, leaving in the area where the impurities on the outer periphery do not diffuse
A first step of forming the entire surface of the semiconductor wafer
Apply a coating solution containing impurities to the surface and perform heat treatment
As a result, the impurity is thermally spread to the region where the impurity is diffused.
To form an impurity diffusion layer,
Second step for forming a region in which impurities are not diffused in the outer peripheral portion
It consists of steps. Acid for forming the diffusion mask
The thickness of the passivation film must be 2000 Å or more
Is preferred.

An oxide film remains on the outer peripheral portion of the semiconductor wafer.
In the first step , the negative resist is dissolved at the time of development by irradiating only the outer peripheral portion of the wafer with ultraviolet light with a peripheral exposure device in a state where the negative resist is applied to the entire surface of the semiconductor wafer. Set not to.

Even if a coating solution containing impurities is applied to the semiconductor wafer manufactured by the above method and subjected to heat treatment to thermally diffuse the impurities, the impurities remain on the outer peripheral portion of the surface of the semiconductor wafer which is most susceptible to thermal stress. The oxide film serves as a diffusion mask, and it is possible to prevent a slip from occurring in a region not diffused.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the present invention will be described with reference to FIGS. First, FIG.
The outline of the present invention will be described based on the process flow of (1). FIG.
As shown in (1), an oxide film for pattern formation and diffusion mask is formed on the entire surface of the semiconductor wafer. Here, the oxide film thickness for the diffusion mask is determined by the following procedure.
Polyboron film (PBF) is used as a diffusion source for semiconductor wafer samples having several types of oxide film thickness.
Is applied, a heat treatment condition for forming an impurity diffusion layer, for example, when the treatment is performed under a target condition of a layer resistance of 6Ω / □ at a diffusion temperature of 1100 ° C. and a diffusion time of 1 hour, how much oxide film thickness is required. A description will be given with reference to FIG.

As shown in FIG. 2, the results of changes in the layer resistance when the semiconductor wafers having several types of oxide film thicknesses are treated under the above heat treatment conditions show that when the oxide film thickness is less than 2000 angstroms, Is diffused by indicating the layer resistance of the diffusion layer or the transition region, and thus has no effect as a diffusion mask. However, when the oxide film thickness is 2000 Å or more, the resistance value of the semiconductor wafer is equivalent to the layer resistance of the semiconductor wafer before diffusion, indicating that the oxide film is not diffused, indicating that it has an effect as a diffusion mask. .

Considering the above results and the heat history of the post-process,
The oxide film thickness for the diffusion mask should be 3000 to 50
A value of about 00 angstroms is appropriate. Next, an opening is formed in the oxide film formed on the entire surface of the semiconductor wafer by using a photolithography technique and an etching technique. Here, the oxide film is removed in the region where the diffusion layer is formed in the surface of the semiconductor wafer, and the oxide film is left in the region where the diffusion layer is not diffused.

Next, a polyboron film (PBF) coating solution containing boron impurities is spin-coated on the semiconductor wafer. Next, a heat treatment is performed on the semiconductor wafer in a diffusion furnace in a nitrogen atmosphere or a nitrogen atmosphere containing several% of oxygen to form a diffusion layer. In this heat treatment step, a desired concentration of boron impurities is diffused from the boron glass layer into the semiconductor wafer in the atmosphere. A more specific and detailed embodiment of the present invention will be specifically described below with reference to FIG.

[0017]

Embodiment 1 FIG. 3 is a cross-sectional view in the order of steps up to diffusion of boron impurities according to the present invention. As shown in FIG. 3A, the surface of the silicon substrate 1 having the N-type conductivity is 1000
The oxide film 2 is oxidized in a pyrogenic gas atmosphere at 3000 ° C. to form an oxide film 2 having a diffusion mask effect of 3000 to 5000 angstroms, for example, 4000 angstroms. Next, as shown in FIG.
A negative resist 3 is applied to the entire surface of the upper oxide film 2 by a spin coating method. Thereafter, as shown in FIG. 3C, in order to make the outer peripheral portion of the silicon substrate 1 a diffusion mask region, the peripheral exposure region 4 is exposed to ultraviolet rays by, for example, a peripheral exposure device. As another method, the outer periphery may be blank on the mask itself. Next, a negative developing process is performed to remove the negative resist 6 not exposed to ultraviolet rays. Further, the oxide film 7 is etched by an etching technique. As a result, only the peripheral exposure region 4 and the diffusion mask 5 remain on the silicon substrate 1.

Finally, by removing the resist from the silicon substrate 1, the peripheral exposure region 4 which is a resist is removed, and a diffusion mask 5 is formed only on the outer peripheral portion of the silicon substrate 1 as shown in FIG. Let it remain. Next, a polyboron film (PBF) is formed on the surface of the silicon substrate 1 and the oxide film (diffusion mask 5) left on the outer periphery by the spin coating method.
When the coating solution of No. 8 is dropped and applied at 3000 to 4000 revolutions / minute to apply a thickness of about 2700 angstroms, a semiconductor wafer as shown in FIG. 3E is formed.

Next, the semiconductor wafer formed as described above is heat-treated in a diffusion furnace in a nitrogen gas atmosphere containing 2% by volume of oxygen gas to form a diffusion layer. Specifically, 3m
A semiconductor wafer is loaded on a m-pitch quartz boat, and the furnace is allowed to enter a diffusion furnace at a temperature of 850 ° C.,
After the furnace temperature has been stabilized for 15 minutes, the temperature is increased by a ramping method. Thereafter, boron impurities are diffused at a diffusion temperature of 1100 ° C. for a predetermined time, for example, one hour. After spreading,
The temperature in the furnace is lowered to 850 ° C., which is the same as before entering, by a ramping method, and the furnace is taken out. When the quartz boat cools, the semiconductor wafer is taken out. Finally, the boron glass layer on the surface of the semiconductor wafer is removed by etching with a hydrofluoric acid aqueous solution or the like, and the diffusion layer 9 having a layer resistance of about 6 Ω / □ as shown in FIG.
To form

The evaluation of the semiconductor device manufactured by the above steps will be described with reference to Table 1 and FIG. Here, Table 1 shows that the peripheral exposure width for forming the peripheral exposure region 4 described with reference to FIG. , Total 5
The slip ratio on the silicon substrate 1 measured for 40 sections is shown.

[0021]

[Table 1]

A product having the widest diffusion region (about 62% in the plane of a semiconductor wafer) among actual products has a diffusion temperature of 1100.
Heat treatment was carried out at a temperature of 1 ° C. for a diffusion time of 1 hour, and the results of measuring the slip ratio for each 5 mm square width 10 as shown in FIG. 4 are shown in Table 1. From the results shown in Table 1, in the step of forming the peripheral exposure region 4, if the peripheral exposure width is 1.5 mm or more, the slip ratio becomes 0%. That is, if the peripheral exposure width is 1.5 mm or more, there is no slip at all. However, considering that the actual cut-off width of the outer peripheral portion of the product is 2 mm, the peripheral exposure width of about 1.9 mm is appropriate.

The phenomenon that the slip is suppressed by making the outermost peripheral portion of the semiconductor wafer a diffusion mask region is described below.
At this time, the theoretical interpretation has not been completely completed, but at this time, slippage is most likely to occur,
It is considered that by leaving an oxide film serving as a diffusion mask on the outer peripheral portion of the semiconductor wafer where stress is likely to be applied and making the region not to be diffused, the stress on the outer peripheral portion of the semiconductor wafer is relaxed and the slip is suppressed.

As described above, the object of the present invention is to largely reduce the slip of the semiconductor wafer by forming the pattern of the element portion or as a diffusion mask by the outer peripheral width of about 1.9 mm of the oxide film grown on the entire surface. It is very effective to perform peripheral exposure so as to remain. Also, in the above-described embodiment,
Although a polyboron film (PBF) is described as a diffusion source, in the present invention, a coating solution containing a diffusion source such as P or As, or PBr ₃ , POCl ₃ , BCl
Similarly, the diffusion method using ₃ or the like has the effect of reducing the slip ratio. Therefore, these techniques are also included in the scope of the present invention.

[0025]

As described above, in the method for diffusing boron into a semiconductor wafer according to the present invention, the outer peripheral portion of the semiconductor wafer which is most susceptible to the influence of thermal stress and which is liable to contact with the boat groove at the time of loading. 1.9 m of ultraviolet light was irradiated by a peripheral exposure device which is a facility in the diffusion manufacturing line.
Irradiation is performed with the width set to m, and the oxide film is left in that portion to function as a diffusion mask, thereby alleviating the stress and preventing the slip generated at the time of diffusion. As a result, characteristic fluctuations such as leak failure of the semiconductor wafer are greatly reduced, and the yield of non-defective products is improved, and at the same time, a high-performance semiconductor wafer can be manufactured.

[Brief description of the drawings]

FIG. 1 is a process flow chart for describing a method for manufacturing a semiconductor wafer shown as a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a film thickness serving as a diffusion mask of the present invention.

FIG. 3 is a cross-sectional view showing a process order for describing a specific example of the embodiment of the present invention.

FIG. 4 is a diagram for explaining a slip ratio when the method of manufacturing a semiconductor wafer according to the present invention is used.

FIG. 5 is a diagram for explaining a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Oxide film 3 Negative resist 4 Peripheral exposure area (negative resist) 5 Diffusion mask (oxide film) 6 Negative resist removal part 7 Oxide film removal part 8 Polyboron film (PBF) 9 Diffusion layer 10 5 mm □ width 11 High Concentration carbon region

Continuation of front page (56) References JP-A-50-138768 (JP, A) JP-A-58-103139 (JP, A) JP-A-52-55860 (JP, A) JP-A-53-29665 (JP) JP-A-53-83576 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/22-21/24

Claims (3)

(57) [Claims] 1. The method according to claim 1, further comprising:
Removal of oxide film in the region where the impurity diffusion layer on the surface is formed
Sufficient to prevent slippage during the diffusion of impurities
An oxide film having a thickness is applied to the outer peripheral portion of the semiconductor wafer.
Forming a diffusion mask while leaving the pure substance in the area that does not diffuse
A first step, expanding the impurities by subjecting the coating solution was applied heat treatment containing impurities on the entire surface of the semiconductor wafer surface
Thermal diffusion of impurities into the diffusion region to form an impurity diffusion layer.
And diffusing impurities into the outer peripheral portion of the semiconductor wafer.
Semiconductor formed by and a second step of forming a free area
Wafer manufacturing method. 2. A thickness of the oxide film for forming the diffusion mask, a method of manufacturing a semiconductor wafer according to claim 1, wherein the more than 2000 angstroms. 3. A first step of leaving an oxide film on an outer peripheral portion of the semiconductor wafer, by irradiating only the outer peripheral portion of the wafer with ultraviolet rays in a state where a negative resist is applied on the entire surface of the semiconductor wafer, 3. The method according to claim 1, wherein the negative resist is not dissolved during the development.
3. The method for manufacturing a semiconductor wafer according to item 1.