JPH01293795A - Line selection controller for digital signal exchange - Google Patents

Abstract

PURPOSE:To shorten a responding time from error generation to correspondent processing by executing a parity check for the control signal of a latch circuit for control signal and sending an error signal when the false signal of the latch circuit is detected. CONSTITUTION:A parity signal P is transmitted to parity check circuits PC1 and PC2 together with selecting signals A0 to A4 and the parity check is executed concerning the outputs of latch circuits L1n and L2n. When an error is generated, error signals PE1 and PE2 are sent to a host computer. By inputting a reading commanding signal READ and a reading switching signal RP, the outputs A0 to A4 and P of the circuit L1n or the outputs A0 to A4 and P of the circuit L2n are read and sent to an output bus RB. Then, since the outputs are led in the computer, the storing contents of the latch circuit can be monitored. Thus, the responding time from the error generation to the correspondent processing can be shortened.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a digital signal exchanger that connects a plurality of digital signal input lines to any one of a plurality of output lines, and particularly relates to Related to improvements to prevent incorrect connections during replacement.

(Prior Art) In general, a digital signal exchanger that exchanges high-speed and continuous digital signals such as image PCM signals used in broadcasting stations etc. has an input line that is connected to multiple input lines and an input line that is connected to multiple output lines. Arrange the connected output lines in a grid pattern,
It is constructed in a matrix type with switch elements arranged at cross points between each input line and output line, and by selectively switching and connecting each switch element, any input line can be connected to any output line. .

However, in the configuration described above in which the connection of each crosspoint is controlled by a switch element, the input digital signal passes through a large number of switch elements before being output from the exchanger, so as the speed of digital signals increases, Therefore, the delay when passing through the switch element cannot be ignored. In addition, an electronic switch using a semiconductor is used as the switch element, but
The signal passing characteristics of this type of switch are generally that the rise and fall delay times are not equal. For this reason, the input digital signal accumulates distortion each time it passes through a switch element, and is output with very large distortion, which may make code identification impossible.

In order to improve this, conventional methods have been considered to perform synchronization and waveform shaping using flip-flops each time the wave passes through a crosspoint switch element, but in a simple matrix configuration, the number of flip-flops required depends on the number of lines. This is not a realistic improvement measure because it requires a huge number of chips, consumes a lot of power, and is difficult to implement.

On the other hand, in conventional exchanges, the selection and switching of a large number of lines is performed in a time-division manner, and the switches are dynamically monitored to prevent erroneous connections. However, in such a time-division exchange system, when handling high-speed, continuous digital signals such as image PCM signals, the bit rate of the selected signal after multiplexing becomes extremely high, making it impractical. In addition, dynamic monitoring of switches requires handling after the switch is connected, which is undesirable in terms of use.

(Problems to be Solved by the Invention) As described above, in conventional digital signal exchangers, as the speed of digital signals to be transmitted increases and the number of lines increases, the delay time difference between lines increases, and distortion occurs during signal transmission. Therefore, it is no longer possible to improve the speed of digital signals and increase the number of lines. Furthermore, since line selection switching is performed using a time-sharing switching method, the selection signal bit rate becomes extremely high, making it impractical.Also, although dynamic monitoring of the switch is performed, it is necessary to take action after the switch is connected. This is not desirable for use.

This invention was made in consideration of the above circumstances, and the delay time between lines is uniform, and distortion occurring during signal transmission can be sufficiently suppressed, thereby increasing the speed of transmitted digital signals. An object of the present invention is to provide a line selection control device for a digital signal exchange that can easily and reliably protect against incorrect line connections when realizing a digital signal exchange that can increase the number of lines.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, a line selection control device for a digital signal exchanger according to the present invention provides a line selection control device for a digital signal exchanger according to a selection signal of n (n is a natural number) bits. It controls the line selection of a digital signal exchanger, which consists of multiple basic selection circuits that select any line from the main digital signal input lines and connect it to the output line, in response to line designation information from the outside. control signal generation means for generating the n-bit selection signal and a parity bit signal and outputting both signals as control signals; A control signal register that holds the selected control signal and sends the held selection signal to the corresponding basic selection circuit, and a control signal register that is provided corresponding to this control signal register and performs a parity check by inputting the control signal held in the register. The first feature of the present invention is that it is configured to include a parity calculation circuit that performs the following and sends out a parity error signal when an error occurs.

Furthermore, a buffer register provided in the preceding stage of the control signal register temporarily holds the control signal and sends it to the control signal register, and a buffer register provided corresponding to this buffer register to transfer the control signal held in the register. The second feature is that it is configured to include a second parity calculation circuit that receives input, performs a parity check, and sends out a parity error signal when an error occurs.

(Function) The line selection control device for a digital signal exchanger having the above configuration generates a parity bit signal together with an n-bit selection signal, inputs and holds both signals as control signals in a control signal register, and outputs the held selection signal. Only the selected basic selection circuit is sent to the corresponding basic selection circuit.

Thereby, by controlling the input/output timing of the control signal register, it is possible to simultaneously select and control a plurality of basic selection circuits. On the other hand, the control signal held in the control signal register is input to a parity calculation circuit, a parity check is performed, and a parity error signal is sent out when an error occurs. This makes it possible to detect that an erroneous signal is held in the control signal register, and to take immediate action.

Further, a buffer register is provided before the control signal register, and the control signal is temporarily held in the buffer register and sent to the control signal register at a predetermined timing, thereby simultaneously switching to the next line selection control. be able to.

In addition, this buffer register is also equipped with a parity calculation circuit, which performs a parity check on the control signal held in the buffer register and sends out a parity error signal when an error occurs. This allows the occurrence of an error to be detected and dealt with before controlling the exchange. Action can be taken.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

Figure 4 shows a 16X16 human power 16X1 to which this invention is applied.
This figure shows the overall configuration of a six-output digital signal exchanger. However, the control system is omitted here.

In FIG. 4, 81 to S2,6 are selector modules with 32 human power and 16 outputs (hereinafter referred to as 32×16) with 16 human power in the row direction and 16 human power in the column direction, and are arranged in 16 rows and 16 columns on the board a. IB, ~1B,, are each 16X16
The external input terminals (not shown) of the lines are divided into 16, and the digital signals input to the external input terminals of the divided 16 lines are arranged in the row direction via bus drivers BD, ~BD, 6. 16 selector modules S, ~S16
゜S17～S3□,...r 5241 "" S2
This is an internal input bus that transmits power to 16 people in the 56 row direction.

CB, ~CB 240 are the selector modules S arranged in the column direction (() is a natural number from 1 to 15).
,~S16. This is an internal common bus that transmits the 16 outputs of 1 to 16 outputs of the 1st selector module S,+, to 516 (□1) in the same column. Also, CB241~CB
256, the 16 outputs of the 16th selector module S arranged in the column direction, respectively, are sent to the selector modules 82 to S16.256 of the next column (CB 256 is the first column). This is an internal common bus that transmits power to 16 people in the S+ column direction. OB.

~0B16 are selector modules S arranged in the row direction
24, ~S2, 6's 16 outputs OB, ~OB, , are connected to one 16x16 line external output terminal (not shown), respectively.
This is an internal output bus that transmits data to external output terminals of 16 lines divided into six.

Although not shown here, the board a is provided with an interface for control signal input/output and a control bus that connects this interface with each selector module S, ~S2, 6, and connects the host computer and each selector module through the interface. 81 to S2, 6 are connected, thereby each selector module S, to S2, 6
The selection can be controlled by the host computer.

That is, in the digital signal exchanger with the above configuration, 1
6x16 line digital signal input 11 to I2, 6 to 16
The signals are divided and sent to internal input buses IB, .about.IB, 6 via buffer drivers BD, .about.BD16, respectively. Internal input buses IB, ~IB, 6 respectively input digital signals to each selector module S1~S, 6°S17~S3□, . . . +5241~S connected to the bus.
Transmit to 16 people in the row direction of 2 and 6.

Each selector module 81 to S2, 6 connects a row direction input line specified by a control signal input through a control bus to a specified output line, and connects a column direction input line of the same column to another output line. do. The digital signal transmitted to the line in the column direction by the switching control of the selector module is output to the outside via the internal output bus line of that column unless another selector is selected.

Figure 5 shows the above 32x16 selector module S, where 1 to 116 are internal input bus lines, 0
1 to CI6 are internal common path lines, 0 to 016 are internal output bus lines, and Ao-A4 are control path lines.

This selector module S has 16 gate arrays G shown in FIG. 6 arranged in parallel in the row direction as shown in FIG.
a connects the input ends of each gate array 61 to GI6 and internal input bus lines 11 to 116.

As shown in FIG. 6, the gate array G0 has a 16
, a 2×1 second gate g2 that selects one line from the output line of this first gate g, and an internal common path line C, and a gate array between each gate array GI-GI6. It is composed of a synchronization circuit g using a flip-flop (F/F) for matching the output timing.

Furthermore, the specific configuration of the gate array G is shown in FIG. 8 and explained. The 16×1 first gate g1
is constructed by arranging 2×1 games gor~gas on a tree: 8 in the first stage, 4 in the second, 2 in the 3rd, and 1 in the 4th. Gate of each stage go+ ~
g 08+ g oe ~ g 12
1 g 13 - g 14.

gls are the control path lines Ao, AI, and
A2.

The selection is controlled by the selection signal from A3.

In other words, the input bus lines II, ~II, 6 connected to this first gate g, are connected to the first stage gates go, ~gos.
8 lines are selected, and the second stage gate g. ,~g
4 lines are selected by 1□, and the third stage gate g13
Two lines are selected by ~g+4, and one line is further selected by the fourth stage gate gos, which is connected to the 2×1 second gate g2.

Here, each of the gates g01 to gas is configured to select the upper line when the selection signal is "0°," and select the lower line when the selection signal is "1°." As a result, the input bus line II can be selectively controlled by simply setting the selection signal of the control path lines A0 to A to (n-1)2. For example, II. When selecting 7, select the selection signal (
A3 A2AIAO)2 (0110) 2 (-(7
1) to). This relationship facilitates setting of the selection signal. Note that the second gate g2 is controlled by a selection signal from the control path line A4, and A4 is set to "1".
”, the output line of the first gate g+ is selected, and “
0'', the internal common path line C8 is selected.

The above 2×1 gate g. I-gr and rgz can be realized by the logic circuit shown in FIG. In Figure 9, A, B
is a digital signal input line, C is a control signal input line,
X is a digital signal output line. This logic circuit is
-(A*C)+(B*C) is realized. That is, C
By setting C to '0', the AND gate AND selects the A side, and by setting C to '1', the AND gate A
The B side can be selected with ND2 and connected to X via the OR gate OR.

If the gate array G is constructed using 2×1 gates as basic elements as described above, the number of times the input signal passes through the gates becomes equal, making synchronization easy and selection control also possible.

- This can be easily realized using the A4 5-bit selection signal.

FIG. 3 shows the configuration of the control system of the selector module S, and the control bus connected to this module S receives the 5-bit selection signal A. ~A4, 4-bit address data AD, chip select signal cs, and write command signal WRITE.

It is composed of each line of the load command signal LOAD.

On the other hand, the control system is provided with first and second latch circuits L lsl L 2m and AND gates g and fl for each gate array G, and further provided with an address decoder ADD for specifying the gate array to be controlled. It consists of

Address decoder ADD contains 4-bit address data A.
D and the pass line of the chip select signal CS are connected, and the AND gate gam is connected to the n-channel output AD of the address decoder ADD and the write command signal WRITE.
path lines are connected. In addition, the first latch circuit L
l. The 5-bit pass line of the selection signal Ao'' A4 and the output line of the AND gate g are connected to
The 5-bit output line of the first latch circuit L1° and the pass line of the load command signal LOAD are connected to the second latch circuit L2°, and the 5-bit output end thereof is connected to the control bus of each gate array G7. .

The above address decoder ADD is a chip select signal CS
It is activated by the input of 4-bit address data AD.
is input to determine which gate array G7 is specified, and the AND gate g a of the specified gate array G is input.
The designation signal AD is sent to m.

The AND gate g an inputting the designation signal AD sends the write command signal WRITE to the first latch circuit m. A first latch circuit receives a write command signal WRITE. takes in the selection signals A0 to A4 and holds them until the next write command signal WRITE is input. When the second latch circuit L2m inputs the load command signal LOAD, it takes in the latch output of the first latch circuit L1m, and the gate array G, until the next load command signal LOAD is input,
Send to. Thereby, the first latch circuit Lla can be freely rewritten and can hold the next selection signal for each gate array G7.

The selector module S can be realized with the above configuration, and the digital signal exchanger shown in FIG. 1 can be configured by combining the selector modules. is latched, the specified input line will be connected to the wrong output line.

That is, in the switch having the above configuration, once a certain connection state is set, the connection state is maintained for the entire time that the exchanged signal occupies the line. As a general method for monitoring this connection state, there is a scanning method in which the contents held in each control register (latch circuit L InnL2.) are sequentially read to confirm whether normal control information is stored. However, with this method, the number of control registers that store control information increases as the scale of the switch increases, so it takes time to read all the control registers that make up the switch. In the unlikely event that an abnormality occurs, it will take time to respond. Therefore, a check mechanism is required that can immediately determine whether or not the correct selection signal is latched in the latch circuit L1+L2s.

FIG. 1 shows the configuration of a check mechanism of a line selection control device according to the present invention, which was made in response to the above-mentioned request, and this check mechanism is provided for each gate array go. In FIG. 1, the same parts as in FIG. 3 are designated by the same reference numerals, and only the different parts will be described here.

First, in addition to the pass lines for the parity signal P1, even/odd designation signal EVEN10DD, read command signal READ, and read switching signal RR, the control bus has 6 lines of read output bus RB and write output bus WB (Ao-A4.P
control path lines) and parity error signals PE, , P
Add a pass line for E2. Read output bus RB, write output bus WB and parity error signals PE, PE
Each of the two path lines is connected to an external host computer through the interface. Note that since writing and reading are not performed simultaneously, the read output bus RB and the write output bus WB may be used in common.

A 6-bit register is used for the first and second latch circuits L++++L2a. First latch circuit L+
++ is a signal A that holds the parity signal P together with the selection signals A and -A4 by inputting the write command signal from the AND gate g7. -A4. P is 12 latch circuits L
2°, is led out to the first parity check circuit PC3 and the first read switch circuit SW1. Second latch circuit L2. is activated by the input of the load command signal LOAD to the first latch circuit L1. output signal A. -A4. hold P;
The held signal AO-A4. P is derived to the second parity check circuit PC2 and the second read switch circuit SW2, and the selection signal A is output. - Deliver only A4 to gate array g.

first and second parity check circuits pc,

Both PO2s have the same configuration, for example, as shown in FIG. In FIG. 2, gol""go3 is an exclusive OR gate (hereinafter referred to as EX-OR gate), and gor has an A. -A2 is supplied, gozl: is A
, ,A, ,P and EVENloDDf)<supplied,g
g in ov. Each output of ++go2 is supplied. In addition, in FIG. 9, EX-OR gate g 01+ go
x requires 3 and 4 people, respectively, but this is 2
This represents multi-stage connection of human-powered EX-OR gates.

The even/odd designation signal EVEN10DD determines whether the parity signal is even parity or odd parity, and the parity signal P is based on this even/odd designation signal EV.
Determined based on EN10DD. For example, A, -A
4 is "00101", even/odd number designation signal EVEN10
When DD is “1” (even number), parity signal P is “0”
becomes.

0X-OR gate g. , the output PE, (or (PE
2) becomes "1", it means that an error has been detected, and the error is sent to the host computer through the path lines (PE, PE2).

The read command signal READ and the read switching signal RR are supplied to the gate g. ~g, selects the first and second readout switch circuits SWI, SW2, and outputs their power to the readout output bus RB. For example, if the read command signal READ is “
1', if the readout switching signal RR "0" is input at the same time, the gate g l*+ g 2n+ g
The output of 3n is “1#” respectively.

1°, becomes “0” and the first readout switch circuit SW,
is in the on state, the second t-out switch circuit SW2 is in the off state, and the output A of the first latch circuit L+6. -A,,P
is read out and sent to the output bus RB.

Furthermore, when the read switching signal RR "1°" is input, the outputs of the gates g I (+ g 2 @ + g 3 * are respectively "0").

“0”, “1” and the first readout switch circuit SW
1 is in the off state, the second readout switch circuit SW2 is in the on state, and the output A of the second latch circuit L2s. -A4.
P to the read output bus RB.

That is, in the control system with the above configuration, the selection signals Ao-A,
The parity signal P is transmitted together with the latch circuit L1@+
A parity check is performed on each output of L 2fl, and if an error occurs, an error signal PEA is sent.
, PE2 to the host computer. Thereby, it is possible to identify whether or not a correct selection signal is held in each latch circuit L lsI L 2s, and it is possible to execute interrupt processing for maintenance on the host computer side. In addition, the read command signal READ
, by inputting the read switching signal RR, the first latch circuit outputs A0 to A4 . P or second latch circuit L2. Output A. -A4. Read P and output bus R
Since the data can be sent to B and derived to the host computer, it is also possible to sequentially monitor the storage contents of all latch circuits. This can significantly shorten the response time from error occurrence to countermeasures.

[Effects of the Invention] As described above, according to the present invention, the delay time between lines is uniform, and distortion occurring during signal transmission can be sufficiently suppressed, thereby increasing the speed of transmitted digital signals. , in realizing a digital signal exchanger that can increase the number of lines.
It is possible to provide a line selection control device for a digital signal exchanger that can easily and reliably protect against incorrect line connections.

[Brief explanation of the drawing]

The drawings show an embodiment of a line selection control device for a digital signal exchanger according to the present invention, and FIG. 1 is a block circuit diagram showing the configuration of the line selection control device according to the present invention, and FIG.
The figure is a logic circuit diagram showing the configuration of the parity check circuit used in the line selection control device, FIG. 3 is a block circuit diagram showing the configuration of the control system of the selector module of the digital signal exchanger shown in FIG. 4, and FIG. is the overall configuration of a digital signal exchanger to which this invention is applied (the control system is omitted here)
FIG. 5 is a block circuit diagram showing the selector module of the exchanger, FIG. 6 is a block circuit diagram showing the configuration of the gate array constituting the selector module, and FIG. is a block circuit diagram showing the internal configuration of the selector module, FIG. 8 is a logic circuit diagram showing the specific configuration of the gate array,
FIG. 9 is a logic circuit diagram showing the configuration of 2×1 gates used in the gate array. 81-5256... Selector module, a... Board, IB, ~IBMs... Internal input bus, BD, ~B
D, 6...Bus driver, CB, ~CB 256...
・Internal common bus, OB + ~OB lb- Internal output bus, II ~ II6... Internal input bus line, 01 ~ C
I6...Internal common path line, 0. ~016... Internal output bus line, A o' = A 4... Control path line, II, ~II, 6... Intra-module input bus line, GI'=G16... Gate array, gI
...16x1 first gate, g2...2x1 second gate, g3...synchronous circuit, gor~gI,...
・2×1 gate, AD...address data, CS...
・Chip select signal, WRITE...Write command signal, LOAD...Load command signal, L, 1°L2m・
...Latch circuit, ADD...address decoder, P.
...Parity signal, E V E N10 D D...
Even number/odd number designation signal, READ...read command signal,
RR: Read switching signal, RB: Read output bus, WB: Write output bus, PE, PE2: Parity error signal, pc, PO2: First and second parity check Circuits sw, sw2...first and second readout switch circuits, gor~gos...exclusive OR gates. Applicant's agent Patent attorney Takehiko Suzue No. 5th n n No. 6rXJ

Claims (2)

[Claims] (1) Digital signal exchange line consisting of multiple basic selection circuits that select any line from multiple digital signal input lines and connect it to the output line according to an n (n is a natural number) bit selection signal. control signal generating means for performing selection control, generating the n-bit selection signal according to line designation information from the outside, generating a parity bit signal, and outputting both signals as a control signal; a control signal register provided in each of the plurality of basic selection circuits to hold the control signal generated by the control signal generation means and send the held selection signal to the corresponding basic selection circuit; A line selection control device for a digital signal exchanger, comprising a correspondingly provided parity calculation circuit which inputs a control signal held in the register, performs a parity check, and sends out a parity error signal when an error occurs. (2) A buffer register provided before the control signal register to temporarily hold the control signal and send it to the control signal register, and a control signal provided corresponding to this buffer register and held in the register. 2. The line selection control device for a digital signal exchanger according to claim 1, further comprising a second parity arithmetic circuit that inputs a parity signal, performs a parity check, and sends out a parity error signal when an error occurs.