JPH01293700A - Automatic wiring apparatus - Google Patents
Automatic wiring apparatusInfo
- Publication number
- JPH01293700A JPH01293700A JP63125394A JP12539488A JPH01293700A JP H01293700 A JPH01293700 A JP H01293700A JP 63125394 A JP63125394 A JP 63125394A JP 12539488 A JP12539488 A JP 12539488A JP H01293700 A JPH01293700 A JP H01293700A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- bundled
- wires
- width
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 7
- 239000000284 extract Substances 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 230000026676 system process Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は情報処理装置に関し、特に、電子回路の自動配
線装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to an automatic wiring device for electronic circuits.
電子装置のプリント基板等を自動配線するために用いる
従来の配線方式は1回路部品のピン間の接続1本(単線
)を処理単位としていた。In conventional wiring methods used for automatic wiring of printed circuit boards and the like of electronic devices, one connection (single wire) between pins of one circuit component is treated as a unit of processing.
上述した従来の自動配線方式は1本の接続を処理単位と
しているので、束線の一部の配線経路が同一束線の他の
配線を妨害することが多かった。Since the above-described conventional automatic wiring system processes one connection as a unit of processing, the wiring route of a part of the bundled wires often interferes with other wirings of the same bundled wires.
従って、未配線が多くなるという欠点があった。Therefore, there was a drawback that there were many unwired lines.
これは第2図に示すように、表面実装部品を用いる場合
に顕著であった。As shown in FIG. 2, this was noticeable when surface mount components were used.
本発明の目的は前記課題を解決した自動配線装置を提供
することにある。An object of the present invention is to provide an automatic wiring device that solves the above problems.
上記目的を達成するため、本発明は、電子回路の回路素
子間を接続する自動配線装置において、回路素子上の連
続して並んだピンと他の回路素子上の連続して並んだピ
ンとの間の束線を検出する束線検出手段と、
前記束線検出手段によって検出された束線中の接続数か
ら束線の配線幅を求める配線幅算出手段と、
前記配線幅算出手段で求めた配線幅の配線領域を探索す
る配線領域探索手段と、
前記配線領域探索手段によって探索された配線領域が前
記配線幅算出手段によって求められた配線幅に満たない
ときに、束線を分割する束線分割手段とを有するもので
ある。In order to achieve the above object, the present invention provides an automatic wiring device that connects circuit elements of an electronic circuit, in which consecutively arranged pins on one circuit element and consecutively arranged pins on another circuit element are connected to each other. Wire bundle detection means for detecting wire bundles; Wire width calculation means for calculating the wiring width of the wire bundle from the number of connections in the wire bundle detected by the wire bundle detection means; Wire width calculated by the wire width calculation means. wiring area searching means for searching for a wiring area; and bundled line dividing means for dividing the bundled wires when the wiring area searched by the wiring area searching means is less than the wiring width calculated by the wiring width calculating means. It has the following.
以下、本発明の一実施例を図により説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.
本発明は束線検出手段1と、配線モデル作成手段2と、
配線幅算出手段3と、配線領域探索手段4と、束線分割
手段5と、経路決定手段6と、設計データベース7と、
束線テーブル8と1作業領域9とから構成される。The present invention includes a wire bundle detection means 1, a wiring model creation means 2,
Wiring width calculating means 3, wiring area searching means 4, wire bundle dividing means 5, route determining means 6, design database 7,
It consists of a wire bundle table 8 and one work area 9.
束線検出手段1は第6図に示すように、設計データベー
ス7から接続情報を取り出し、第4図に示すような回路
素子41〜45上の連続して並んだピンと、他の回路素
子41〜45上の連続して並んだピンとの間の束状の接
続(束線46及び束線47)を検出し、束線テーブル8
に格納する。As shown in FIG. 6, the wire bundle detection means 1 extracts connection information from the design database 7, and detects pins arranged in succession on circuit elements 41 to 45 as shown in FIG. A bundled connection (bundled wire 46 and bundled wire 47) between the pins arranged in succession on 45 is detected, and the bundled wire table 8
Store in.
接続情報から全ての束線が検出されたら、配線モデル作
成手段2が起動される。配線モデル作成手段2は第7図
に示すように設計データベース7から回路素子の配置情
報を取り出し、作業領域9に配線モデルを構築する0次
に、配線幅算出手段3が起動される。配線幅算出手段3
は第8図に示すように、束線テーブル8から束線を1個
ずつ取り出し、第1式によって束線の配線幅を求める。When all bundled wires are detected from the connection information, the wiring model creation means 2 is activated. As shown in FIG. 7, the wiring model creation means 2 retrieves the circuit element arrangement information from the design database 7 and constructs a wiring model in the work area 9. Next, the wiring width calculation means 3 is activated. Wiring width calculation means 3
As shown in FIG. 8, the bundled wires are taken out one by one from the bundled wire table 8, and the wiring width of the bundled wires is determined by the first equation.
配線幅=束線中の接続数×(単線の配線幅+配線間隔)
・・・(1)次に、配線領域探索手段4が起動される。Wiring width = number of connections in wire bundle x (single wire wiring width + wiring spacing)
(1) Next, the wiring area search means 4 is activated.
配線領域探索手段4は第9図に示すように、束線ごとに
配線幅算出手段3が算出した配線幅の空領域を作業領域
9上で探索する。第5図に示す配置状態では第4図に示
す束線46に対しては配線領域54が、束線47に対し
ては配線領域55が得られる。51〜53は各回路素子
41.43.44.45のパッドをそれぞれ示す。56
は障害を示す。As shown in FIG. 9, the wiring area searching means 4 searches the work area 9 for an empty area of the wiring width calculated by the wiring width calculating means 3 for each wire bundle. In the arrangement shown in FIG. 5, a wiring area 54 is obtained for the wire bundle 46 shown in FIG. 4, and a wiring area 55 is obtained for the wire bundle 47. 51 to 53 indicate pads of each circuit element 41, 43, 44, and 45, respectively. 56
indicates a failure.
配線幅を満足する配線領域が得られない場合は、束線分
割手段5が起動される。束線分割手段5は第10図に示
すように、得られた配線領域から配線可能な束線中の接
続数を第2式により算出する。If a wiring area satisfying the wiring width cannot be obtained, the wire bundle dividing means 5 is activated. As shown in FIG. 10, the wire bundle dividing means 5 calculates the number of connections in the wire bundle that can be wired from the obtained wiring area using the second equation.
次に、束線を求めた接続数のものと残りの接続数のもの
との2つに分割し、もとの束線を束線テーブル8から削
除し、分割した2つの束線を束線テーブル8に登録する
0次に、再び配線幅算出手段3が起動される。Next, divide the bundled wire into two parts, one with the determined number of connections and one with the remaining number of connections, delete the original bundled wire from the bundled wire table 8, and replace the two divided wires with the bundled wire. After zero is registered in the table 8, the wiring width calculation means 3 is activated again.
配線幅を満足する配線領域が得られ、回路素子間をつな
ぐことができる場合は、経路決定手段6が起動される。If a wiring area satisfying the wiring width is obtained and the circuit elements can be connected, the route determining means 6 is activated.
経路決定手段6は第11図に示すように、作業領域9中
の得られた配線領域をピンの並びの順に埋めて配線経路
を決め、設計データベース7に書き込む、束線テーブル
8から束線を削除する6次に、再び配線幅算出手段3が
呼ばれる。As shown in FIG. 11, the route determining means 6 determines the wiring route by filling the obtained wiring area in the work area 9 in the order of the pin arrangement, and writes the bundled wires from the bundled wire table 8 into the design database 7. Delete 6 Next, the wiring width calculation means 3 is called again.
以下これらの処理を束線テーブル8中に格納された束線
がなくなるまで続ける。These processes are continued until there are no more bundled wires stored in the wire bundle table 8.
以上の動作は束線にのみ注目して説明したが、単線も束
線の1部と見なすことによって、全ての接続に対して配
線経路を決定することができる。Although the above operation has been explained focusing only on bundled wires, wiring routes can be determined for all connections by considering single wires as part of bundled wires.
このようにして処理した結果を第3図に示す。The results of processing in this manner are shown in FIG.
以上説明したように本発明は束線を検出し、その配線幅
を算出し、算出した配線幅の領域を探索し、その領域が
配線幅より小さいとき、束線を分割し、並行して配線す
ることにより、未配線本数を減少できる効果がある。As explained above, the present invention detects bundled wires, calculates its wiring width, searches for an area with the calculated wiring width, and when the area is smaller than the wiring width, divides the bundled wires and routes them in parallel. This has the effect of reducing the number of unwired wires.
第1図は本発明の一実施例のブロック図、第2図は従来
の配線方式による配線結果を示すプリントパターン図、
第3図は本発明の配線方式による配線結果を示すプリン
トパターン図、第4図は接続関係を表わす論理回路図、
第5図は第4図に示す論理回路図中の回路素子の配置図
、第6図は第1図に示す束線検出手段の流れ図、第7図
は第1図に示す配線モデル作成手段の流れ図、第8図は
第1図に示す配線幅算出手段の流れ図、第9図は第1図
に示す配線領域探索手段の流れ図、第10図は第1図に
示す束線分割手段の流れ図、第11図は第1図に示す経
路決定手段の流れ図である。FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a printed pattern diagram showing the wiring results using a conventional wiring method.
FIG. 3 is a printed pattern diagram showing the wiring results according to the wiring method of the present invention, FIG. 4 is a logic circuit diagram showing connection relationships,
5 is a layout diagram of circuit elements in the logic circuit diagram shown in FIG. 4, FIG. 6 is a flowchart of the wire bundle detection means shown in FIG. 1, and FIG. 7 is a flowchart of the wiring model creation means shown in FIG. 1. Flowcharts, FIG. 8 is a flowchart of the wiring width calculation means shown in FIG. 1, FIG. 9 is a flowchart of the wiring area search means shown in FIG. 1, FIG. 10 is a flowchart of the wire bundle division means shown in FIG. 1, FIG. 11 is a flowchart of the route determining means shown in FIG.
Claims (1)
おいて、回路素子上の連続して並んだピンと他の回路素
子上の連続して並んだピンとの間の束線を検出する束線
検出手段と、 前記束線検出手段によって検出された束線中の接続数か
ら束線の配線幅を求める配線幅算出手段と、 前記配線幅算出手段で求めた配線幅の配線領域を探索す
る配線領域探索手段と、 前記配線領域探索手段によって探索された配線領域が前
記配線幅算出手段によって求められた配線幅に満たない
ときに、束線を分割する束線分割手段とを有することを
特徴とする自動配線装置。(1) In automatic wiring equipment that connects circuit elements of electronic circuits, bundled wire detection detects bundled wires between consecutive pins on one circuit element and consecutive pins on another circuit element. means, a wiring width calculation means for calculating the wiring width of the wire bundle from the number of connections in the wire bundle detected by the wire bundle detection means, and a wiring region for searching for a wiring region of the wire width determined by the wire width calculation means. The present invention is characterized by comprising: a search means; and a bundled line dividing means for dividing the bundled wires when the wiring area searched by the wiring area searching means does not have the wiring width determined by the wiring width calculating means. Automatic wiring device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63125394A JPH01293700A (en) | 1988-05-23 | 1988-05-23 | Automatic wiring apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63125394A JPH01293700A (en) | 1988-05-23 | 1988-05-23 | Automatic wiring apparatus |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01293700A true JPH01293700A (en) | 1989-11-27 |
Family
ID=14909053
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63125394A Pending JPH01293700A (en) | 1988-05-23 | 1988-05-23 | Automatic wiring apparatus |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01293700A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08221458A (en) * | 1995-02-09 | 1996-08-30 | Nec Corp | Bundled wiring design device |
-
1988
- 1988-05-23 JP JP63125394A patent/JPH01293700A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08221458A (en) * | 1995-02-09 | 1996-08-30 | Nec Corp | Bundled wiring design device |
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