JPH01293596A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH01293596A JPH01293596A JP12432488A JP12432488A JPH01293596A JP H01293596 A JPH01293596 A JP H01293596A JP 12432488 A JP12432488 A JP 12432488A JP 12432488 A JP12432488 A JP 12432488A JP H01293596 A JPH01293596 A JP H01293596A
- Authority
- JP
- Japan
- Prior art keywords
- thick
- film electrode
- film
- soldered
- thick film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011521 glass Substances 0.000 claims abstract description 10
- 239000007772 electrode material Substances 0.000 claims abstract description 8
- 230000001681 protective effect Effects 0.000 claims description 7
- 238000005476 soldering Methods 0.000 abstract description 11
- 229910000679 solder Inorganic materials 0.000 abstract description 8
- 229910052709 silver Inorganic materials 0.000 abstract description 3
- 239000004332 silver Substances 0.000 abstract description 3
- 239000010408 film Substances 0.000 abstract 12
- 239000010409 thin film Substances 0.000 abstract 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 210000004899 c-terminal region Anatomy 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、混成集積回路装置に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to a hybrid integrated circuit device.
従来の技術
従来、混成集積回路装置は、第２図ａ、ｂに示す様な構
成であった。第２図ａ、ｂに於いて、９はアルミナ基板
、１ｏは１回の印刷焼成により形成しだ厚膜電極である
。１１はリードはんだ件部のみに、２回の印刷焼成によ
り形成した厚膜電極、１２は保護ガラスで、はんだ付は
部分を除く厚膜電極１０及び印刷抵抗１６を覆っている
。又、リード端子１４及びチップ部品１３を付けるため
に、はんだ１５が用いられている。2. Description of the Related Art Conventionally, hybrid integrated circuit devices have had configurations as shown in FIGS. 2a and 2b. In FIGS. 2a and 2b, 9 is an alumina substrate, and 1o is a thick film electrode formed by one printing and firing process. Reference numeral 11 denotes a thick film electrode formed only on the lead solder part by printing and baking twice, and 12 is a protective glass that covers the thick film electrode 10 and the printed resistor 16 except for the soldered part. Further, solder 15 is used to attach lead terminals 14 and chip components 13.
発明が解決しようとする課題
この様な従来の構造では、厚膜電極１ｏにはんだ付けす
る際に厚膜電極１０の電極材料中の銀がはんだに移行す
ることにより、特に細いパターンの場合アルミナ基板９
と厚膜電極１ｏの接着強度が低下し、しいては、はんだ
付は強度が低下し断線してしまう。しかしはんだ付は以
外の印刷抵抗１６部分の膜厚は、厚いことを必要とせず
、印刷抵抗１６は厚膜電極１０の膜厚が薄い方が抵抗値
のバラツキが小さく、はんだ付は部と相反する条件を必
要としていた。Problems to be Solved by the Invention In such a conventional structure, when soldering to the thick film electrode 1o, the silver in the electrode material of the thick film electrode 10 migrates to the solder, which causes the alumina substrate to break down, especially in the case of a thin pattern. 9
This lowers the adhesive strength of the thick film electrode 1o, which in turn lowers the soldering strength and leads to breakage. However, the film thickness of the printed resistor 16 other than soldering does not need to be thick, and the printed resistor 16 has smaller variations in resistance value when the thick film electrode 10 is thinner, and the soldering is contradictory to the soldering part. I needed conditions to do so.
本発明はこの様な条件を満たすことを目的とするもので
ある。The present invention aims to satisfy such conditions.
課題を解決するだめの手段
この目的を達成するために本発明は、強度が必要なリー
ド端子、チップ部品のはんだ付けする厚膜電極部分を電
極材料を複数回重ねて印刷することにより形成し、この
厚膜電極部分に保護ガラス膜が部分的に重なるように形
成したものである。Means for Solving the Problems In order to achieve this object, the present invention forms thick-film electrode parts for soldering lead terminals and chip components that require strength by printing electrode materials in multiple layers, A protective glass film is formed so as to partially overlap this thick film electrode portion.
作用
この構成により、厚膜電極材料の使用量を減少でき、し
かも抵抗値のバラツキを抑え、又、はんだ付は部の強度
が低下するのを防ぐことができる。Effect: With this configuration, it is possible to reduce the amount of thick film electrode material used, suppress variations in resistance value, and prevent the strength of soldering parts from decreasing.
実施例
第１図ａ、ｂは本発明の一実施例による混成集積回路装
置の要部を示す図で、図において、１はアルミナ基板、
２はこのアルミナ基板１上に所定のパターンとなるよう
に１回の印刷と焼付けで構成した厚膜電極である。３は
この厚膜電極２上のはんだ付は部分に印刷と焼付けによ
り形成した厚膜電極、４は保護ガラスで、第１図＆の点
線で示すように、はんだ付は部分を除いて厚膜電極２及
び厚膜電極３の端部上を覆うように形成されている。５
は電極部を厚膜電極３にばんだ７により接続することに
より実装したチップ部品、ｅは外部へのリード引出し部
としてのリード端子で、所定の厚膜電極３にはんだ了に
より接続されている。Embodiment FIGS. 1a and 1b are diagrams showing essential parts of a hybrid integrated circuit device according to an embodiment of the present invention. In the figures, 1 is an alumina substrate;
Reference numeral 2 denotes a thick film electrode formed by printing and baking once on this alumina substrate 1 so as to form a predetermined pattern. 3 is a thick film electrode formed by printing and baking on the soldered part on this thick film electrode 2, and 4 is a protective glass. It is formed to cover the ends of the electrode 2 and the thick film electrode 3. 5
is a chip component mounted by connecting the electrode part to the thick film electrode 3 with a solder 7, e is a lead terminal as a lead extraction part to the outside, and is connected to a predetermined thick film electrode 3 by soldering. .
８は両端部が厚膜電極２と重なり合うように印刷・焼付
けによりアルミナ基板１上に形成した抵抗体であり、こ
の抵抗体８は保護ガラス４により覆われている。A resistor 8 is formed on the alumina substrate 1 by printing and baking so that both ends overlap the thick film electrodes 2, and the resistor 8 is covered with a protective glass 4.
このように本実施例においては、所定の回路パターンを
形成する厚膜電極２上のはんだ付けされる部分に、厚膜
電極２の形成時とは別に印刷・焼付けを行うことにより
厚膜電極３を形成し、その厚膜電極３上においてはんだ
了によりチップ部品５やリード端子６を接続し、そして
厚膜電極３のはんだ７が付着しない端部に重なるように
、保護ガラス４を形成している。In this way, in this embodiment, the thick film electrode 3 is printed and baked separately from the process of forming the thick film electrode 2 on the soldered portion of the thick film electrode 2 that forms a predetermined circuit pattern. The chip components 5 and lead terminals 6 are connected by soldering on the thick film electrode 3, and the protective glass 4 is formed so as to overlap the end of the thick film electrode 3 to which the solder 7 is not attached. There is.
発明の効果
以上のように本発明によれば、混成集積回路装置におけ
る厚膜電極のはんだ付けされる部分のみにさらに別の厚
膜電極を形成しており、銀の移行によるはんだ付は強度
の低下全抑えることができる。又、膜厚を厚くすること
が必要でない部分は一回の印刷・焼付けによる厚膜電極
であるため、厚膜電極材料の使用量を減少させ、抵抗値
のバラツキを抑えることができる。Effects of the Invention As described above, according to the present invention, another thick film electrode is formed only in the part to be soldered of the thick film electrode in the hybrid integrated circuit device, and soldering due to silver migration is improved. The decline can be completely suppressed. Further, since thick film electrodes are formed by printing and baking once in the areas where it is not necessary to increase the film thickness, it is possible to reduce the amount of thick film electrode material used and suppress variations in resistance value.
第１図ａは本発明の一実施例による混成集積回路装置の
要部を示す平面図、第１図すは第１図のＡ−Ａ’で切断
した断面図、第２図４は従来の混成集積回路装置の要部
を示す平面図、第２図すは第２図ａのＢ −Ｂ’で切断
した断面図である。
１・ ・・アルミナ基板、２，３・・・・・・厚膜電極
、４・・・・・・保護ガラス、５・・・・・・チップ部
品、６・・・・・・ＩＪ、−ド端子、ア・・・・・はん
だ、８・・・・・抵抗体。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名ノー
−−ア、ｔ／ミナ五、役
４−−−ｈｊｆ−蹟力゛ラス
６−−チツブ冑？’ａ＋
６−−−リー）′：藻チ
ア −−−＋コんた゛
８−ａ抗イード；
第 １ 図FIG. 1a is a plan view showing the main parts of a hybrid integrated circuit device according to an embodiment of the present invention, FIG. 1 or a sectional view taken along line AA' in FIG. FIG. 2 is a plan view showing essential parts of the hybrid integrated circuit device, and FIG. 2 is a sectional view taken along line BB' in FIG. 2a. 1... Alumina substrate, 2, 3... Thick film electrode, 4... Protective glass, 5... Chip parts, 6... IJ, - C terminal, A...Solder, 8...Resistor. Agent's name: Patent attorney Toshi Nakao, and one other person: Noah, T/Minago, Yaku4---hjf-Kanryoku゛ras6--Chitsubuka? Figure 1
Claims (1)
て印刷することにより形成し、この厚膜電極部分に保護
ガラス膜が部分的に重なるように形成した混成集積回路
装置。A hybrid integrated circuit device in which a thick-film electrode portion to be soldered is formed by printing multiple layers of electrode material, and a protective glass film is formed so as to partially overlap the thick-film electrode portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12432488A JPH01293596A (en) | 1988-05-20 | 1988-05-20 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12432488A JPH01293596A (en) | 1988-05-20 | 1988-05-20 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01293596A true JPH01293596A (en) | 1989-11-27 |
Family
ID=14882522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12432488A Pending JPH01293596A (en) | 1988-05-20 | 1988-05-20 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01293596A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0529298A2 (en) * | 1991-08-23 | 1993-03-03 | E.I. Du Pont De Nemours And Company | Method for making thick film/solder joints |
-
1988
- 1988-05-20 JP JP12432488A patent/JPH01293596A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0529298A2 (en) * | 1991-08-23 | 1993-03-03 | E.I. Du Pont De Nemours And Company | Method for making thick film/solder joints |
| EP0529298A3 (en) * | 1991-08-23 | 1994-08-10 | Du Pont | Method for making thick film/solder joints |
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