JPH01283973A - Mounting device for photodetecting element - Google Patents

Mounting device for photodetecting element

Info

Publication number
JPH01283973A
JPH01283973A JP63112430A JP11243088A JPH01283973A JP H01283973 A JPH01283973 A JP H01283973A JP 63112430 A JP63112430 A JP 63112430A JP 11243088 A JP11243088 A JP 11243088A JP H01283973 A JPH01283973 A JP H01283973A
Authority
JP
Japan
Prior art keywords
chip
light
chips
package
state image
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63112430A
Other languages
Japanese (ja)
Inventor
Norio Koike
小池 紀雄
Toshibumi Ozaki
俊文 尾崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP63112430A priority Critical patent/JPH01283973A/en
Publication of JPH01283973A publication Critical patent/JPH01283973A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/162Disposition
    • H01L2924/1627Disposition stacked type assemblies, e.g. stacked multi-cavities
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Abstract

PURPOSE:To improve the function of a solid state image pickup device by sealing mounting parts on which photoelectric conversion element chips are mounted with a translucent substance, while by sealing mounting parts on which element chips other than the photoelectric conversion element chips are mounted with a light shielding or translucent substance. CONSTITUTION:In a package structure where chips can be mounted on both surfaces, a solid state image pickup element chip 6'-1 is mounted on a surface of a package 12 onto which light is injected and a drive circuit or a signal processing circuit, etc., on a surface thereof onto which light is not injected. The side onto which the light is injected is sealed by a translucent plate 10', while the side onto which the light is not injected is sealed, as necessary, by sealing means 14 such as a translucent or nontranslucent plate. Accordingly, many function circuit chips 6'-2 in addition to the solid state image pickup element chip 6'-1 can be mounted with in the same mounting device, thereby reducing image pickup the size of and increasing the functions of the solid state image pickup element device.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体基板上に光電変換素子、信号を取出す
ための走査素子、等を集積化した固体撮像素子或いは、
各種の光検出素子を実装するための光検出素子用実装装
置に関するものである。
[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a solid-state image sensor in which a photoelectric conversion element, a scanning element for extracting signals, etc. are integrated on a semiconductor substrate, or
The present invention relates to a photodetecting element mounting apparatus for mounting various photodetecting elements.

〔従来の技術〕[Conventional technology]

固体撮像素子は現行のテレビジョン放送で使用されてい
る撮像用電子管並みの解像力を備えた撮像板を必要とし
、このため垂直方向に500個、水平方向に500〜8
00個を配列した絵素(光電変換素子)マトリックスと
それに相当する走査素子が必要となる。したがって、上
記固体撮像素子は高集積化が必要なMO5大規模回路技
術を用いて作られ、構成素子として一般にCODあるい
はMoSトランジスタ等が使用されている。
Solid-state imaging devices require an imaging plate with a resolution comparable to that of the imaging electron tubes used in current television broadcasting, and for this reason, there are 500 in the vertical direction and 500 to 8 in the horizontal direction.
A matrix of 00 picture elements (photoelectric conversion elements) and a corresponding scanning element are required. Therefore, the solid-state image sensor is manufactured using MO5 large-scale circuit technology that requires high integration, and generally uses COD or MoS transistors as constituent elements.

第2図(a)にCCDC固形撮像索子のチップ概略図を
示す、1は光ダイオード、垂直CODシフトレジスタ等
からなる光電変換領域、2は垂直CODシフトレジスタ
により転送されてきた信号電荷を出力回路3に向けて転
送する水平CODシフトレジスタである。4はCODを
駆動するクロックパルス、電源電圧等を供給するポンデ
ィングパッド、5はパルス等を伝達する配線であり、例
えば4vは垂直COD駆動用クロックを1例えば4Hは
水平COD駆動用クロックを、40は出力回路を駆動す
る電源電圧等を供給するパッドである。また、6は光電
変換素子、水平CCD、出力回路、配線、パッド等を集
積化した固体撮像素子チップである。
Figure 2 (a) shows a schematic diagram of the chip of the CCDC solid-state imaging probe. 1 is a photoelectric conversion area consisting of a photodiode, a vertical COD shift register, etc., and 2 is an output signal charge transferred by the vertical COD shift register. This is a horizontal COD shift register that transfers data toward circuit 3. 4 is a bonding pad that supplies clock pulses, power supply voltage, etc. that drive the COD, 5 is a wiring that transmits pulses, etc. For example, 4V is a clock for vertical COD driving; 1, for example, 4H is a clock for horizontal COD driving; Reference numeral 40 denotes a pad that supplies power supply voltage and the like for driving the output circuit. Further, 6 is a solid-state image sensor chip in which a photoelectric conversion element, a horizontal CCD, an output circuit, wiring, pads, etc. are integrated.

第2図(b)は上記の固体撮像索子チップを実装するパ
ッケージの概略を示している。6は固体撮像素子チップ
、7はパッケージ側のポンディングパッド、8はチップ
側のパッド(4)とパッケージ側のパッド7を電気的に
接続するワイヤ(一般にAQ、Au@等が使われる)、
9はビン端子であり、各々のビンは所定のパッド7と電
気的につながっている。
FIG. 2(b) schematically shows a package in which the above solid-state imaging probe chip is mounted. 6 is a solid-state image sensor chip, 7 is a bonding pad on the package side, 8 is a wire (generally AQ, Au@, etc. is used) that electrically connects the pad (4) on the chip side and the pad 7 on the package side.
Numeral 9 is a bin terminal, and each bin is electrically connected to a predetermined pad 7.

また、10はパッケージ内にチップを封止する封止板で
、光学情報11を通すため一般に透明ガラス等が使用さ
れる。
Further, 10 is a sealing plate for sealing the chip inside the package, and transparent glass or the like is generally used to pass optical information 11 therethrough.

上記のようにパッケージに撮像チップを封仕した固体搬
像素子実装装置は周知のように小型、軽量、メインテナ
ンスフリーなど、電子管撮像装置に較べて固体化に伴う
多くの利点を有しており。
As is well known, the solid-state imaging device mounting device in which the imaging chip is sealed in a package as described above has many advantages over electron tube imaging devices due to its solid state structure, such as being small, lightweight, and maintenance-free.

撮像装置として将来が期待されているものである。This is a device that is expected to have a promising future as an imaging device.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし乍ら、現行の固体撮像素子実装装置は未だ開発の
途上にあり、以下に挙げるような問題点を抱えている。
However, the current solid-state image sensor mounting apparatus is still in the process of development and has the following problems.

(1)固体撮像素子の他に駆動回路、信号処理回路、メ
モリ等を一体化し1機能および信頼度の向上。
(1) In addition to the solid-state image sensor, drive circuits, signal processing circuits, memory, etc. are integrated to improve functionality and reliability.

寄生容量の低減による混入雌音の低減および広帯域化等
を図ってゆく必要がある。しかし、これら周辺回路を撮
像素子内に集積化しようとすると、全体のチップサイズ
は著しく大きくなり、価格の上昇を招く。またチップ内
で消費する電力が大きくなり、チップ発熱による暗電流
の増加を招く等、集積化による利点より常置の方が大き
くなってしまう。
It is necessary to reduce mixed sounds by reducing parasitic capacitance and to widen the band. However, when attempting to integrate these peripheral circuits into an image sensor, the overall chip size becomes significantly large, leading to an increase in price. In addition, the power consumed within the chip increases, leading to an increase in dark current due to chip heat generation, and so the advantages of permanent installation outweigh the benefits of integration.

(2)固体撮像索子そのものは小型であるが、現実のビ
テオカメラにおいては駆動回路、信号処理回路の装置も
カメラ構成要素として必要なため、カメラ全体の小型化
には限界がある。また、各回路を実装するための実験費
(パッケージ費用)が個々の回路について必要となるた
め、カメラ価格の上昇を招く等、問題点は固体撮像装置
の実用化と並行して増加する傾向にある。
(2) Although the solid-state imaging probe itself is small, in an actual video camera, a drive circuit and a signal processing circuit are also required as camera components, so there is a limit to miniaturization of the entire camera. In addition, experiment costs (package costs) to implement each circuit are required for each circuit, leading to an increase in camera prices, and other problems tend to increase in parallel with the commercialization of solid-state imaging devices. be.

したがって、固体撮像装置の機能向上を図り、かつ装置
全体の小型化を図ることが大切な課題となる。
Therefore, it is an important issue to improve the functionality of solid-state imaging devices and to reduce the size of the entire device.

本発明の目的は、上記の問題点を解決することにあり、
機能の高い小型の固体撮像装置を提供することにある。
The purpose of the present invention is to solve the above problems,
An object of the present invention is to provide a compact solid-state imaging device with high functionality.

〔課題を解決するための手段〕[Means to solve the problem]

上記本発明の目的は、固体撮像素子を実装するパッケー
ジの両面に諸種のチップを設置することにより達成され
る。具体的にいえば、チップを両面に設置することがで
きるようなパッケージ構造軽考え、パッケージの光が入
射する面の側に固体撮像素子チップを、光の入射しない
面の側に駆動回路、或いは信号処理回路等のチップを取
付けるようにし、光が入射する側は光透過性の板により
封止し、光入射のない側は必要に応じて光透過性もしく
は非透過性の板あるいは他の封止手段により封止するよ
うにしたところに特徴がある。
The above object of the present invention is achieved by installing various types of chips on both sides of a package in which a solid-state image sensor is mounted. Specifically, we have developed a light package structure that allows the chip to be installed on both sides, the solid-state image sensor chip is placed on the side of the package where light enters, and the drive circuit is placed on the side where light does not enter. Chips such as signal processing circuits are attached, and the side where light enters is sealed with a light-transmissive plate, and the side where light is not entered is sealed with a light-transparent or non-transparent board or other sealing as necessary. The feature is that it is sealed by a sealing means.

〔作用〕[Effect]

上述のとおり1本発明固体撮像素子用実装装置において
は、同一実装装置の中に固体撮像素子チップの他に、幾
多の機能回路チップを取付けることができる。
As described above, in one mounting apparatus for a solid-state image sensor of the present invention, in addition to the solid-state image sensor chip, a number of functional circuit chips can be mounted in the same mounting apparatus.

したがって、固体撮像素子チップの寸法を大きくしなく
とも、実効的に固体撮像装置の小型化、機能化を図るこ
とが可能である。
Therefore, it is possible to effectively downsize and improve the functionality of the solid-state imaging device without increasing the size of the solid-state imaging device chip.

〔実施例〕〔Example〕

以下1本発明を実施例を用いて詳細に説明する。 The present invention will be explained in detail below using examples.

第1図は本発明の骨子となる実施例を示す図で、固体撮
像素子用実装装置の構造を示したものである。第1図に
おいて、12は2つのチップ取付は部13−1.13−
2を備えた実装装置、すなわちパッケージ、6′−1は
固体撮像索子チップ、6′−2は駆動回路、或いは信号
処理回路等を集積化したチップである。7’−1,7’
 −2はパッケージ側のパッド、8′−1は撮像索子チ
ップとパッケージ側パッドを電気的に接続するワイヤ−
、8′−2は例えば駆動回路チップとノ(ツケージ側パ
ッドを接続するワイヤである。10′は光が入射する側
、すなわち撮像索子チップ側に取付けた透光性の封止板
、一方、14′は光電変換に関係のない駆動回路チップ
等を設置した側に取付けた封止板である。封止板14は
光を通す必要はないので、不透明な材料(例えば、金属
、透過性のない無機材料)を用いるのが望ましい、或い
は。
FIG. 1 is a diagram showing an embodiment that is the gist of the present invention, and shows the structure of a mounting apparatus for a solid-state image sensor. In Fig. 1, 12 indicates the two chip mounting portions 13-1.13-
2 is a mounting device, that is, a package, 6'-1 is a solid-state imaging probe chip, and 6'-2 is a chip in which a driving circuit, a signal processing circuit, etc. are integrated. 7'-1,7'
-2 is a pad on the package side, 8'-1 is a wire that electrically connects the imaging probe chip and the pad on the package side.
, 8'-2 are wires connecting the drive circuit chip and the cage side pads. 10' is a translucent sealing plate attached to the side where light enters, that is, the imaging cable chip side; , 14' is a sealing plate attached to the side where drive circuit chips etc. not related to photoelectric conversion are installed.Since the sealing plate 14 does not need to pass light, it is made of an opaque material (for example, metal, transparent material, etc.). or

封止板を用いる方法ではなく、一般のICのモールド剤
としてよく使われるレジン樹脂を用い、領域15の部分
にレジン樹脂を流し込むことによりチップ6′−2をレ
ジン樹脂で封止するようにしてもよい。
Instead of using a sealing plate, the chip 6'-2 is sealed with a resin resin that is often used as a molding agent for general ICs by pouring the resin into the area 15. Good too.

チップ6′−2を例えば駆動回路に見立てた場合、駆動
回路で発生した駆動パルスは撮像素子チップに入力され
素子を駆動する。駆動パルスを出力するパッド(7’−
2−n:nは複数あるパッドの中の所定の番号を表わし
ている)と駆動パルスを入力するパッド(7’−1−n
)はパッケージ内に敷設する配線レイアウトによりパッ
ケージ内部で電気的に接続されていてもよいしく図示せ
ず)第1図(b)に示すようにパッケージ12に2個の
ビン端子、すなわちパッド7’2−n用のピン端子(9
’−2−n)とパッド7’−1−n用のピン端子(9’
−1−n)を設け、これら2つのビン端子(9’−1−
nと9’−2−n)をパッケージ外部に設ける配1li
A16により電気的に接続するようにしてもよい。上記
のような本発明の実装装置により撮像索子自体のチップ
サイズを大きくすることなく、実質的に撮像索子の機能
を上げることが可能となる。
When the chip 6'-2 is assumed to be a drive circuit, for example, drive pulses generated by the drive circuit are input to the image pickup element chip and drive the element. Pad (7'-
2-n: n represents a predetermined number among multiple pads) and a pad for inputting the drive pulse (7'-1-n
) may be electrically connected inside the package depending on the wiring layout laid inside the package (not shown) As shown in FIG. 2-n pin terminal (9
'-2-n) and pin terminal for pad 7'-1-n (9'
-1-n), and these two bin terminals (9'-1-n) are provided.
n and 9'-2-n) on the outside of the package.
The electrical connection may be made through A16. By using the mounting apparatus of the present invention as described above, it is possible to substantially improve the functionality of the imaging probe without increasing the chip size of the imaging probe itself.

第1図(Q)はチップ取付は部13−1.13−2の寸
法(或いは面積でもよい)を異なる大きさにした実施例
である。この例では取付は部13−2の寸法(或いは面
積)撮像索子チップ6′−1の取付は部13−1より小
さくした例を示したが、駆動回路或いは信号処理回路等
の機能化回路を形成するチップが撮像素子チップよりも
大きくなる場合は、取付は部13−2の寸法(或いは面
積)を取付は部13−1より大きくするようにしても構
わない。
FIG. 1(Q) shows an embodiment in which the chip mounting portions 13-1 and 13-2 have different dimensions (or areas). In this example, the dimensions (or area) of the mounting section 13-2 and the mounting of the imaging probe chip 6'-1 are smaller than those of the section 13-1. If the chip forming the image sensor chip is larger than the image sensor chip, the size (or area) of the mounting portion 13-2 may be made larger than that of the mounting portion 13-1.

第3図は本発明の別の実施例を示す図であり、第3図(
a)は取付は部13−2に複数個のチップを取付けるよ
うにしたものである。6′−2は例えば駆動回路チップ
でありワイヤー8′−2を介してパッケージのパッド7
′−2に、6′−3は例えば信号処理回路用のチップで
ありワイヤ8′−3を介してパッド7′−3に電気的に
接続されている。この実施例では撮像素子チップも含め
3個のチップを取付けた例を示したが、上記のチップの
他に、映像メモリ、アナログ・デジタルコンバータなど
多数のチップを取付けるようにしても構わない。
FIG. 3 is a diagram showing another embodiment of the present invention, and FIG.
In a), a plurality of chips are attached to the portion 13-2. 6'-2 is, for example, a drive circuit chip, which is connected to the pad 7 of the package via a wire 8'-2.
'-2 and 6'-3 are chips for, for example, a signal processing circuit, and are electrically connected to pads 7'-3 via wires 8'-3. In this embodiment, an example is shown in which three chips including an image sensor chip are attached, but in addition to the above-mentioned chips, a large number of chips such as a video memory, an analog/digital converter, etc. may be attached.

第3図(b)は同図(a)と同じように複数個のチップ
を取付けられるようにした例であるが、パッド用の台座
17を新たに設け、パッケージ側パッド7’ −2’ 
、7’ −3’ を新設した実施例である。これらのパ
ッドの増設によりチップ6′−2,6’ −3の機能が
より向上するという利点が得られる。ここで、ビン端子
9′の数はパッドの数が増えた分だけ増やしてもよいが
、装置の取扱い易さを考慮するとパッド間(7’ −2
’ と7’ −3’ )はパッケージ内部で配線接続す
ることにより装置の外部に出すピン端子9′の数は減ら
しておくことが望ましい。また、この例では台座の頭部
18と封止板14の間に間隙があるが封止板14と接触
するようにし、封止板を支えるような構造にしても構わ
ない。
FIG. 3(b) is an example in which a plurality of chips can be attached in the same way as in FIG. 3(a), but a pad pedestal 17 is newly provided, and the package side pads 7'-2'
, 7'-3' is newly added. The addition of these pads has the advantage of further improving the functionality of the chips 6'-2 and 6'-3. Here, the number of pin terminals 9' may be increased by the increase in the number of pads, but considering the ease of handling the device, the distance between pads (7' - 2
It is desirable to reduce the number of pin terminals 9' exposed to the outside of the device by connecting the pin terminals 9' and 7'-3' inside the package. Further, in this example, there is a gap between the head 18 of the pedestal and the sealing plate 14, but the structure may be such that it contacts the sealing plate 14 and supports the sealing plate.

第4図はチップ取付は部13−1と13−2の間に固定
板19を設けた例である。この固定板19により撮像索
子実装装置をカメラ(図示せず)等に固定することがで
きる(すなわち、光学的位置合せを行うことができる。
FIG. 4 shows an example in which a fixing plate 19 is provided between the chip mounting parts 13-1 and 13-2. With this fixing plate 19, the imaging cord mounting device can be fixed to a camera (not shown) or the like (that is, optical alignment can be performed).

この固定板19に金属を使用すると、撮像チップ6′−
1と他の回路チップ6′−2を電気的にシールドするこ
とができ、回路チップから撮像チップに飛込む雑音を低
減することができる。さらに回路チップの消費電力が大
きい場合等は電力消費による発熱の放熱板として利用す
ることができるので、撮像チップの温度上昇を防止する
ことができる(撮像チップの温度上昇は暗電流の増加を
招き画質を低下させる)。
If metal is used for this fixing plate 19, the imaging chip 6'-
1 and the other circuit chip 6'-2 can be electrically shielded, and noise that enters the imaging chip from the circuit chip can be reduced. Furthermore, when the power consumption of the circuit chip is large, it can be used as a heat dissipation plate for the heat generated by power consumption, so it is possible to prevent the temperature of the imaging chip from rising (a rise in temperature of the imaging chip causes an increase in dark current) (decreases image quality).

第5図はピン端子を第1図に示したようなリード端子形
から埋込み端子形に変えた構造を示している。このよう
な構造にするとピン端子も含めてパッケージ全体の小型
化を図ることができる。この実施例では上下に2列の端
子20−1.20−2を設ける例を示したが、1列のみ
でもよいし、3列、4列と増やしてもよい。
FIG. 5 shows a structure in which the pin terminal is changed from the lead terminal type shown in FIG. 1 to a buried terminal type. With this structure, the entire package including the pin terminals can be made smaller. Although this embodiment shows an example in which two rows of terminals 20-1 and 20-2 are provided above and below, there may be only one row, or the number may be increased to three or four rows.

第6図は複数のパッケージを用いて単一の実装装置に一
体化した実施例を示している。第6図(、)において2
1−1は撮像素子チップ6′−1と他の回路チップ6′
−2を取付けたパッケージ、10’ は21−1を封止
するための透光性の封仕板、一方、21−2はさらに他
の回路チップ6′−3を取付けたパッケージである。2
つのパッケージ21−1と21−2は、各チップを所定
のパッケージ21−1.21−2に取付けた後、各パッ
ケージの接触面22に接着剤等を塗布し接着(一体化)
する。
FIG. 6 shows an embodiment in which a plurality of packages are integrated into a single mounting device. In Figure 6 (,) 2
1-1 is an image sensor chip 6'-1 and another circuit chip 6'
-2 is attached to the package, 10' is a translucent sealing plate for sealing 21-1, and 21-2 is a package to which another circuit chip 6'-3 is attached. 2
The two packages 21-1 and 21-2 are bonded (integrated) by applying adhesive or the like to the contact surface 22 of each package after each chip is attached to a predetermined package 21-1 or 21-2.
do.

第6図(b)は、形態が同様のパッケージ21′−1と
21’ −2を接着し一体化したものである。
FIG. 6(b) shows packages 21'-1 and 21'-2, which are similar in form, glued together and integrated.

パッケージ21’−1には撮像チップ6′−1と他の回
路チップ6′−2を、21’ −2にはさらに他の2チ
ップ6’−3,6’ −4を取付け、21’−1は透光
性の封仕板10′により、一方、21’ −2は遮光性
の封止板により封止されている。第6図(a)、(b)
ともに図面の複雑化をさけるためピン端子の記載は省略
したが1本構造の実装装置においても第1図或いは第5
図と同様の位置にリード形ピン端子、埋込み形ピン端子
を設ければよい。
An imaging chip 6'-1 and another circuit chip 6'-2 are attached to the package 21'-1, and two other chips 6'-3 and 6'-4 are attached to the package 21'-2. 1 is sealed by a light-transmitting sealing plate 10', and 21'-2 is sealed by a light-shielding sealing plate. Figure 6 (a), (b)
In both cases, pin terminals are omitted to avoid complicating the drawings, but the pin terminals shown in Figure 1 or Figure 5 are
Lead type pin terminals and embedded type pin terminals may be provided at the same positions as shown in the figure.

第7図は従来のパッケージと同じように片側だけにチッ
プを取付ける形の実装装置を示している。
FIG. 7 shows a mounting device in which a chip is mounted only on one side, similar to a conventional package.

第7図において、6′−1は撮像索子チップ、6′−2
は他の回路チップである。チップ6′−2には光を入れ
る必要がない、或いは光が漏洩すると回路動作が不安定
になる危険性があるので。
In FIG. 7, 6'-1 is an imaging probe chip, 6'-2
is another circuit chip. There is no need to introduce light into the chip 6'-2, or there is a risk that the circuit operation will become unstable if light leaks.

透光性封止板10’の一部に(チップ6′−2の上部に
相当する領域に)遮光板22を貼付けている。この遮光
板はチップ6′−2の上部に貼付けてもよい或いは、し
や光膜をチップ上に直接蒸着するようにしてもよい、或
いは透光板10′においてチップ6′−2に相当する領
域に遮光膜(金属膜等)を蒸着するようにしてもよい、
ここで、チップ取付は部13−2にチップ6′−2の他
にさらに別の回路チップを設けるようにしてもよいしく
すなわち、13−2に複数の回路チップを取付けるよう
にしてもよいし)、この図では2個の取付は部(13−
1,13−2)を設ける例を示したが、取付は部を3個
、4個、・・・と増やしても構わない。また1台座17
は必ず必要とするものではないので17を設けないよう
にしてもよいし、チップ6′−1と6′−2を直接ワイ
ヤで接続するようにしてもよい(チップ上に設けた各々
のパッド間をワイヤで直接接続するようにしてもよい)
A light shielding plate 22 is attached to a part of the transparent sealing plate 10' (in a region corresponding to the upper part of the chip 6'-2). This light-shielding plate may be pasted on the top of the chip 6'-2, or a shielding film may be deposited directly on the chip, or it may be placed on the light-transmitting plate 10' corresponding to the chip 6'-2. A light shielding film (metal film, etc.) may be deposited on the area.
Here, for chip mounting, another circuit chip in addition to the chip 6'-2 may be provided in the section 13-2, or in other words, a plurality of circuit chips may be mounted in the section 13-2. ), in this figure the two mountings are part (13-
1, 13-2), but the number of mounting parts may be increased to three, four, etc. Another pedestal 17
is not absolutely necessary, so 17 may be omitted, or chips 6'-1 and 6'-2 may be directly connected with wires (each pad provided on the chip (You may also connect them directly with a wire)
.

〔発明の効果〕〔Effect of the invention〕

以上、実施例を用いて詳細に説明したように、本発明に
よれば、実装装置の工夫により単一の実装装置に複数の
チップを取付けすることが可能となり、撮像素子チップ
自体のチップ寸法を大きくすることなく単一の実装装置
で実質的に撮像装置の機能、特性および信頼度の向上、
小型化、低価格化等を図ることができる。さらに、この
ような実装装置の単一化によりチップ間に寄生する容量
も減少するので信号の広帯域化、雑音の低減を図ること
等も可能となり本発明の実用価値は極めて大きい。
As described above in detail using the embodiments, according to the present invention, it is possible to mount a plurality of chips on a single mounting device by devising the mounting device, and the chip size of the image sensor chip itself can be reduced. Substantially improving the functions, characteristics and reliability of the imaging device with a single mounting device without increasing the size;
It is possible to achieve miniaturization and cost reduction. Furthermore, by unifying such a mounting device, the parasitic capacitance between chips is reduced, so that it is possible to widen the signal band and reduce noise, and the practical value of the present invention is extremely large.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の固体撮像素子用実装装置の構造を示す
断面図、第2図は従来の固体撮像索子用実装装置の構造
を示す平面図および断面図、第3図、第4図、第5図、
第6図および第7図は本発明の他の実施例を示す断面図
である。 1・・・光電変換領域、4・・・ポンディングパッド、
6・・・固体撮像素子チップ、7・・・パッケージ側パ
ッド、8・・・ワイヤー、9・・・ピン端子、10.1
4・・・封止板、13・・・チップ取付は部、19・・
・固定板、20・・・埋込み形ピン端子。 第  l  圀 (し) (C) (b) 1 、、、t、を変p乏領りに        8 ・
  ワイヤー7 ゛・ノで7ケ一ジ償II■/ド 第3図 (り 第 4 口 第 5 口 lデ ・ II 定板 20 ・j1込9f杉ヒ“シ貸賑シ
FIG. 1 is a sectional view showing the structure of a mounting device for a solid-state imaging device according to the present invention, FIG. 2 is a plan view and a sectional view showing the structure of a conventional mounting device for a solid-state imaging device, FIGS. 3 and 4. , Figure 5,
FIGS. 6 and 7 are cross-sectional views showing other embodiments of the present invention. 1... Photoelectric conversion area, 4... Ponding pad,
6... Solid-state image sensor chip, 7... Package side pad, 8... Wire, 9... Pin terminal, 10.1
4... Sealing plate, 13... Chip mounting part, 19...
・Fixing plate, 20...embedded pin terminal. (C) (b) 1,,,t, changed to p-poor 8 ・
Wire 7 ゛・ノ 7-key compensation II ■/de Figure 3

Claims (1)

【特許請求の範囲】[Claims] 1、半導体基板上に光電変換素子を形成した光検出素子
を実装する単一の光検出素子用実装装置において、上記
実装装置の複数の面に光電変換素子をはじめとする複数
の素子チップを設置することができる複数のチップ取付
け部を設け、上記光電変換素子チップを取付けた上記取
付け部を透光性のある物質で封止し、一方、光電変換に
与からない素子チップを取付けた上記取付け部を遮光性
、或いは透光性の物質で封止するようにしたことを特徴
とする光検出素子用実装装置。
1. In a single photodetecting element mounting device that mounts a photodetecting element with a photoelectric conversion element formed on a semiconductor substrate, multiple element chips including the photoelectric conversion element are installed on multiple surfaces of the mounting device. A plurality of chip mounting parts are provided, and the mounting part to which the photoelectric conversion element chip is mounted is sealed with a light-transmitting material, while the mounting part to which the element chip that does not participate in photoelectric conversion is mounted is provided. 1. A mounting device for a photodetecting element, characterized in that a portion thereof is sealed with a light-shielding or light-transmitting material.
JP63112430A 1988-05-11 1988-05-11 Mounting device for photodetecting element Pending JPH01283973A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63112430A JPH01283973A (en) 1988-05-11 1988-05-11 Mounting device for photodetecting element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63112430A JPH01283973A (en) 1988-05-11 1988-05-11 Mounting device for photodetecting element

Publications (1)

Publication Number Publication Date
JPH01283973A true JPH01283973A (en) 1989-11-15

Family

ID=14586443

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63112430A Pending JPH01283973A (en) 1988-05-11 1988-05-11 Mounting device for photodetecting element

Country Status (1)

Country Link
JP (1) JPH01283973A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6153928A (en) * 1996-05-17 2000-11-28 Hyuandai Electronics Industries Co., Ltd. Substrate for semiconductor package, fabrication method thereof, and stacked-type semiconductor package using the substrate
EP1813951A1 (en) * 2006-01-30 2007-08-01 Infineon Technologies SensoNor AS Inertial measurement unit and packages thereof
WO2007125633A1 (en) * 2006-04-28 2007-11-08 Kabushiki Kaisha Toshiba High-frequency semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6153928A (en) * 1996-05-17 2000-11-28 Hyuandai Electronics Industries Co., Ltd. Substrate for semiconductor package, fabrication method thereof, and stacked-type semiconductor package using the substrate
EP1813951A1 (en) * 2006-01-30 2007-08-01 Infineon Technologies SensoNor AS Inertial measurement unit and packages thereof
WO2007125633A1 (en) * 2006-04-28 2007-11-08 Kabushiki Kaisha Toshiba High-frequency semiconductor device
EP2015392A1 (en) * 2006-04-28 2009-01-14 Kabushiki Kaisha Toshiba High-frequency semiconductor device
JPWO2007125633A1 (en) * 2006-04-28 2009-09-10 株式会社東芝 High frequency semiconductor devices
US7667322B2 (en) 2006-04-28 2010-02-23 Kabushiki Kaisha Toshiba High-frequency semiconductor device
US7994637B2 (en) 2006-04-28 2011-08-09 Kabushiki Kaisha Toshiba High-frequency semiconductor device
EP2015392A4 (en) * 2006-04-28 2011-09-07 Toshiba Kk High-frequency semiconductor device

Similar Documents

Publication Publication Date Title
US8902356B2 (en) Image sensor module having image sensor package
US5336879A (en) Pixel array having image forming pixel elements integral with peripheral circuit elements
US20060024857A1 (en) Image sensor package structure and method for fabricating the same
US7566854B2 (en) Image sensor module
EP1942661A2 (en) Electronic assembly for image sensor device and fabrication method thereof
US20060030070A1 (en) Packaging structure and method of an image sensor module
KR100596104B1 (en) Cmos image sensor
US10074757B2 (en) Semiconductor package, sensor module, and production method
US6703617B1 (en) Device for imaging radiation
US20040256687A1 (en) Optical module, method of manufacturing the same, and electronic instrument
JPH11261044A (en) Semiconductor device with solid-state image sensing element and manufacture of this semiconductor device
JP7414720B2 (en) Semiconductor device, electronic device, and method for manufacturing semiconductor device
US20080023809A1 (en) Chip package and digital camera module using same
US20090026567A1 (en) Image sensor package structure and method for fabricating the same
US6172361B1 (en) Methods for mounting an imager to a support structure and circuitry and systems embodying the same
US6172351B1 (en) Photoelectric integrated circuit device
US6740973B1 (en) Stacked structure for an image sensor
JP2006032561A (en) Semiconductor image sensor module
JPH01283973A (en) Mounting device for photodetecting element
JPH0226080A (en) Semiconductor device
JP3424360B2 (en) Solid-state imaging device
US20050189624A1 (en) Chip on photosensitive device package structure and electrical connection thereof
TWM576691U (en) Image-capturing module and portable electric device
JPH05191733A (en) Solid-state image pickup device
JP3817859B2 (en) Imaging device