JPH01283842A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01283842A JPH01283842A JP11399988A JP11399988A JPH01283842A JP H01283842 A JPH01283842 A JP H01283842A JP 11399988 A JP11399988 A JP 11399988A JP 11399988 A JP11399988 A JP 11399988A JP H01283842 A JPH01283842 A JP H01283842A
- Authority
- JP
- Japan
- Prior art keywords
- film
- inner lead
- semiconductor device
- semiconductor element
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 238000000926 separation method Methods 0.000 abstract 2
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 238000007747 plating Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
テープボンディング型半導体装置のインナーリードとフ
ィルムとの接着部の改良に関し、簡単且つ容易に製造す
ることが可能な、インナーリードがフィルムの変形の影
響を受は難い、]゛AB型の半導体装置の提供を目的と
し、半導体素子のバンプに対応するインナーリードをテ
ープ状のフィルムにくり返し形成し、前記インナーリー
ドの先端部と、前記半導体素子の前記バンプとを接合し
て前記半導体素子を搭載するテープボンディング型半導
体装置であって、前記インナーリードと前記フィルムと
を全面で接着せず、その接着部分を最小の面積とするよ
う構成する。[Detailed Description of the Invention] [Summary] Regarding the improvement of the bond between the inner lead and the film of a tape bonding type semiconductor device, the inner lead is not affected by the deformation of the film, which can be simply and easily manufactured. ] ゛Aiming at providing an AB type semiconductor device, inner leads corresponding to the bumps of the semiconductor element are repeatedly formed on a tape-like film, and the tips of the inner leads and the bumps of the semiconductor element are formed repeatedly. The semiconductor device is a tape bonding type semiconductor device in which the semiconductor element is mounted by bonding the inner leads and the film, and the inner lead and the film are not bonded over the entire surface, but the bonded portion is configured to have a minimum area.
本発明は、半導体装置に係り、特にテープボンディング
型半導体装置のインナーリードとフィルムとの接着部の
改良に関するものである。The present invention relates to a semiconductor device, and particularly to an improvement in the adhesive portion between an inner lead and a film of a tape bonding type semiconductor device.
半導体装置を組立てるのには種々の方式が用いられてい
るが、その一つにテープ状のフィルムにくり返し形成さ
れた導体のインナーリードと、半導体素子のバンプの対
応する部分とを重ね合わせ、熱圧着により接合して多数
の配線を同時に接合するテープ・オートメーテツド・ボ
ンディング(tapeautomated bondi
ng、以下、TABと略称する。)がある。Various methods are used to assemble semiconductor devices, one of which is to overlay conductor inner leads repeatedly formed on a tape-like film and the corresponding portions of the bumps on the semiconductor element, and heat them. Tape automated bonding, which connects multiple wires at the same time by crimping
ng, hereinafter abbreviated as TAB. ).
この方式においては、ポリイミドよりなるフィルムにイ
ンナーリードを全面で接着して形成し°ζいる。In this method, inner leads are formed by adhering the entire surface to a polyimide film.
半導体装置の製造工程において半導体装置の信φ■度試
験の一環として、バーンインと称する高温度に半導体装
置を加熱する試験が行われているが、フィルムとインナ
ーリードの材質の相違から、この試験の際にフィルムが
熱のために変形し、この変形によりフィルムに全面で接
着しているインナーリードも変形するためにインナーリ
ード変形、インナーリード切断或いはインナーリードと
バンプの接合部において、バンプのはがれ、インナーリ
ードのメツキ剥離等が発生している。In the manufacturing process of semiconductor devices, as part of the reliability test of semiconductor devices, a test called burn-in is conducted in which semiconductor devices are heated to a high temperature. At this time, the film is deformed due to heat, and this deformation also deforms the inner lead, which is completely adhered to the film, resulting in deformation of the inner lead, cutting of the inner lead, or peeling off of the bump at the joint between the inner lead and the bump. Peeling of the inner lead plating, etc. has occurred.
以上のような状況から、加熱及び冷却の際のフィルムに
生じる歪に起因する障害を防止することが可能な半導体
装置が要望されている。Under the above circumstances, there is a demand for a semiconductor device that can prevent failures caused by distortion that occurs in the film during heating and cooling.
従来のTAB型半導体装置の構造を第2図〜第3図につ
いて説明する。The structure of a conventional TAB type semiconductor device will be explained with reference to FIGS. 2 and 3.
第2図(alはTAB型半導体装置の形状を示す平面図
であり、第2図中)は側面図である。FIG. 2 (al is a plan view showing the shape of the TAB type semiconductor device, and FIG. 2 is a side view) is a side view.
第3図は従来のTAB型半導体装置の主要部の形状を示
す側面図である。FIG. 3 is a side view showing the shape of the main parts of a conventional TAB type semiconductor device.
第2図において、ポリイミドよりなる膜厚125μmの
テープ状のフィルム3には、半導体素子1の周囲に設け
た150μm角で厚さ25μmのバンプ1aに対応する
インナーリード2が、くり返し形成されている。In FIG. 2, inner leads 2 corresponding to bumps 1a of 150 μm square and 25 μm thick provided around the semiconductor element 1 are repeatedly formed on a tape-shaped film 3 made of polyimide and having a thickness of 125 μm. .
このインナーリード2は厚さが30μmで、幅が100
μmの銅箔に膜厚0.5μIの錫メツキを施したもので
ある。This inner lead 2 has a thickness of 30 μm and a width of 100 μm.
This is a copper foil with a thickness of 0.5μI and tin plating.
半導体素子lのバンプ1aをこのインナーリード2の先
端部と重ね合わせ、加熱及び加圧して接合している。The bumps 1a of the semiconductor element 1 are overlapped with the tips of the inner leads 2 and bonded by heating and pressurizing.
このような半導体装置を高温のバーンイン試験にかける
と、インナーリード2がフィルム3に全面で接着されて
いるので、第3図Ta)の状態のものが第3図中)に示
すようにフィルム3の変形のためにインナーリード2と
半導体素子lのバンプ1aとの接合部において、バンプ
1aのはがれ、インナーリード2のメツキ剥離等が生じ
、断線が発生している。When such a semiconductor device is subjected to a high-temperature burn-in test, the inner leads 2 are bonded to the film 3 over the entire surface, so that the state shown in FIG. Due to this deformation, peeling of the bumps 1a, peeling off of the plating of the inner leads 2, etc. occur at the joints between the inner leads 2 and the bumps 1a of the semiconductor element 1, resulting in disconnection.
以上説明の従来のTAB型半導体装置においては、半導
体装置をバーンイン試験にかけると、フィルムの変形に
起因するインナーリードと半導体素子のバンプとの接合
部において、バンプのはがれ、インナーリードのメツキ
剥離等が生じて接触不良が発生し、断線するという問題
点があった。In the conventional TAB type semiconductor device described above, when the semiconductor device is subjected to a burn-in test, peeling of the bumps, peeling off of plating on the inner leads, etc. at the joints between the inner leads and the bumps of the semiconductor element due to film deformation occur. This causes problems such as poor contact and disconnection.
本発明は以上のような状況から、簡単且つ容易に製造す
ることが可能な、インナーリードがフィルムの変形の影
響を受は難い、TAB型の半導体装置の提供を目的とし
たものである。In view of the above-mentioned circumstances, the present invention aims to provide a TAB type semiconductor device which can be simply and easily manufactured and whose inner leads are hardly affected by film deformation.
上記問題点は、半導体素子のバンプに対応するインナー
リードをテープ状のフィルムにくり返し形成し、前記イ
ンナーリードの先端部と、前記半導体素子の前記バンプ
とを接合して前記半導体素子を搭載するテープボンディ
ング型半導体装置であって、前記インナーリードと前記
フィルムとを全面で接着せず、その接着部分を最小の面
積とする本発明による半導体装置によって解決される。The above problem is solved by repeatedly forming inner leads corresponding to the bumps of the semiconductor element on a tape-like film, and bonding the tips of the inner leads and the bumps of the semiconductor element to the tape on which the semiconductor element is mounted. The problem is solved by a bonding type semiconductor device according to the present invention, in which the inner lead and the film are not bonded over the entire surface, and the bonded portion has a minimum area.
即ち本発明においては、インナーリードのフィルムへの
接着部分を最小面積としているので、加熱によりフィル
ムに変形が生じても、半導体素子のバンプとインナーリ
ードの先端との接合部が剥離し、断線するのを防止する
ことが可能となる。That is, in the present invention, since the area of the bonded portion of the inner lead to the film is minimized, even if the film is deformed by heating, the bond between the bump of the semiconductor element and the tip of the inner lead will peel off and disconnect. This makes it possible to prevent
以下第1図〜第3図について本発明の一実施例を説明す
る。An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.
本発明の半導体装置はインナーリード2とフィルム3と
の接着部分を最小面積としたこと以外は第2図に示す従
来の半導体装置と同じ形状を有している。The semiconductor device of the present invention has the same shape as the conventional semiconductor device shown in FIG. 2, except that the adhesive portion between the inner lead 2 and the film 3 has a minimum area.
本発明の特徴とするインナーリード2とフィルム3との
接着部の四通りの実施例を第1図に示す。FIG. 1 shows four embodiments of the bonding portion between the inner lead 2 and the film 3, which is a feature of the present invention.
第1図(alは接着部を二分割したものであり、第1図
(b)は接着部を二分割し、その間のインナーリード2
にたるみを持たせたものである。Figure 1 (al is the adhesive part divided into two parts, Figure 1 (b) is the adhesive part divided into two parts, and the inner lead 2 between them.
It is made to have some slack.
第1図fc)はインナーリード2とバンブ1aとの接合
部の反対の端部のみでインナーリードをフィルム3に接
着したものである。In FIG. 1 fc), the inner lead is bonded to the film 3 only at the end opposite to the joint between the inner lead 2 and the bump 1a.
第1図fd)は第1図(C)のインナーリード2とバン
ブ1aとの接合部をフィルム3の面より更に遠くするこ
とにより、半導体素子1がフィルム3面と同一面に位置
するようにしたものである。In FIG. 1fd), the junction between the inner lead 2 and the bump 1a in FIG. 1C is moved further away from the surface of the film 3, so that the semiconductor element 1 is located on the same plane as the surface of the film 3. This is what I did.
このようにインナーリード2とフィルム3との接着部を
極力小面積とすることにより、フィルム3の熱変形の影
響がインナーリードに波及するのを防止することが可能
となる。By making the area of the bonded portion between the inner lead 2 and the film 3 as small as possible in this way, it is possible to prevent the influence of thermal deformation of the film 3 from spreading to the inner lead.
以上の説明から明らかなように、本発明によれば極めて
簡単インナーリードとフィルムとの接着部の面積を最小
にすることにより、半導体素子のバンブとインナーリー
ドの先端部との接合部にフィルムの熱変形に起因する応
力が加わるのを防止でき、半導体素子のバンブとインナ
ーリードの先端部との接合部が剥離するのを防止するこ
とが可能となり、この剥離に起因する半導体装置の組立
歩留の低下を防止することが可能となる等の利点があり
、著しい経済的及び、信頼性向上の効果が期待でき工業
的には極めて有用なものである。As is clear from the above description, according to the present invention, by minimizing the area of the bonding area between the inner lead and the film, it is possible to attach the film to the bonding area between the bump of the semiconductor element and the tip of the inner lead. It is possible to prevent the stress caused by thermal deformation from being applied, and it is possible to prevent the bond between the bump of the semiconductor element and the tip of the inner lead from peeling off, which reduces the assembly yield of semiconductor devices due to this peeling. It has advantages such as being able to prevent a decrease in the temperature, and can be expected to have a significant economical and reliability improvement effect, making it extremely useful industrially.
第1図は本発明の各種の実施例のインナーリードとフィ
ルムとの接着方法を示す側面
図、
第2図はTAB型半導体装置の形状を示す図、第3図は
従来の半導体装置の主要部の形状を示す側面図、である
。
図において、
1は半導体素子、
1aはバンブ、
2はインナーリード、
3はフィルム、
4は接着剤、
を示す。
」1−
(al@lの実施例
(′b1°第1°実施例
+e+ 第3の実施例
+d+ 第4の実施例
1J41 図
(B)平面図
山)側面図
TAB型半導体装置の形状を示す図
第2図
(al 正常な状態を示す側面図
(b) 加熱し変形した状態を示す側面図従来の半導
体装置の主要部の形状を示す側面図第3図FIG. 1 is a side view showing the bonding method between the inner lead and film of various embodiments of the present invention, FIG. 2 is a diagram showing the shape of a TAB type semiconductor device, and FIG. 3 is a diagram showing the main parts of a conventional semiconductor device. FIG. In the figure, 1 is a semiconductor element, 1a is a bump, 2 is an inner lead, 3 is a film, and 4 is an adhesive. 1- (Al@l Example ('b1° 1st Example + e + 3rd Example + d + 4th Example 1J41 Figure (B) Top View Mountain) Side View Showing the Shape of a TAB Type Semiconductor Device Figure 2 (al) Side view showing the normal state (b) Side view showing the heated and deformed state Figure 3 Side view showing the shape of the main parts of a conventional semiconductor device
Claims (1)
ーリード(2)をテープ状のフィルム(3)にくり返し
形成し、前記インナーリード(2)の先端部と、前記半
導体素子(1)の前記バンプ(1a)とを接合して前記
半導体素子(1)を搭載するテープボンディング型半導
体装置であって、前記インナーリード(2)と前記フィ
ルム(3)とを全面で接着せず、その接着部分を最小の
面積とすることを特徴とする半導体装置。Inner leads (2) corresponding to the bumps (1a) of the semiconductor element (1) are repeatedly formed on a tape-like film (3), and the tips of the inner leads (2) and the bumps (1a) of the semiconductor element (1) are formed repeatedly. A tape bonding type semiconductor device in which the semiconductor element (1) is mounted by bonding the semiconductor element (1) with a bump (1a), wherein the inner lead (2) and the film (3) are not bonded on the entire surface, but only on the bonded portion. A semiconductor device characterized by having a minimum area.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11399988A JPH01283842A (en) | 1988-05-10 | 1988-05-10 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11399988A JPH01283842A (en) | 1988-05-10 | 1988-05-10 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01283842A true JPH01283842A (en) | 1989-11-15 |
Family
ID=14626528
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11399988A Pending JPH01283842A (en) | 1988-05-10 | 1988-05-10 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01283842A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54111763A (en) * | 1978-02-22 | 1979-09-01 | Hitachi Ltd | Carrier tape for tape carrier |
JPS6126233A (en) * | 1984-07-13 | 1986-02-05 | Matsushita Electric Ind Co Ltd | Semiconductor device |
-
1988
- 1988-05-10 JP JP11399988A patent/JPH01283842A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54111763A (en) * | 1978-02-22 | 1979-09-01 | Hitachi Ltd | Carrier tape for tape carrier |
JPS6126233A (en) * | 1984-07-13 | 1986-02-05 | Matsushita Electric Ind Co Ltd | Semiconductor device |
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