JPH01282822A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH01282822A
JPH01282822A JP11280288A JP11280288A JPH01282822A JP H01282822 A JPH01282822 A JP H01282822A JP 11280288 A JP11280288 A JP 11280288A JP 11280288 A JP11280288 A JP 11280288A JP H01282822 A JPH01282822 A JP H01282822A
Authority
JP
Japan
Prior art keywords
heat treatment
temperature
resistivity
hydrogen atmosphere
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11280288A
Other languages
Japanese (ja)
Other versions
JPH07101693B2 (en
Inventor
Mitsuyoshi Takeda
武田 満喜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11280288A priority Critical patent/JPH07101693B2/en
Publication of JPH01282822A publication Critical patent/JPH01282822A/en
Publication of JPH07101693B2 publication Critical patent/JPH07101693B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To inhibit the lowering of the resistivity of an n-type substrate, and to prevent the deterioration of breakdown strength characteristics by executing heat treatment in a hydrogen atmosphere at the temperature and the time of 1100 deg.C/10Hr equivalent values or more as the preprocess of a process in which an electrode is evaporated. CONSTITUTION:A semiconductor device is manufactured by using an n-type silicon substrate having resistivity rho of 10OMEGA.cm or more. A heat treatment process 8 in a hydrogen atmosphere at the temperature and the time of 1100 deg.C/10Hr equivalent values or more is provided as the preprocess of a process 6 in which an electrode is evaporated. The effect of the heat treatment process in the hydrogen atmosphere is displayed with the higher temperature of treatment and the longer time of treatment, and the relationship of the temperature and the time can be selected from the capacity of the device and an economical viewpoint. Even when heat treatment at approximately 500 deg.C is executed, the resistivity of a base body is not lowered, thus preventing the deterioration of breakdown strength characteristics. Accordingly, the lowering of the resistivity of the N-type substrate is suppressed, and the deterioration of breakdown strength characteristics is obviated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は特に基板中の不純物濃度に応じた耐圧特性を
得るための半導体装置の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention particularly relates to a method of manufacturing a semiconductor device for obtaining breakdown voltage characteristics depending on the impurity concentration in a substrate.

〔従来の技術〕[Conventional technology]

一般に半導体装置は一定の不純物をもつn形のSi基板
にP形、n形の不純物元素を1000’0以上の熱拡散
法によって導入し、p−n接合を得る工程と、500°
C前後の電極付けの工程により製造されているが、この
製造方法を第4図で詳述する。ここで、基板はp=’n
Ω”m、FZ法、n形(Pドープ)Si単結晶ウェハで
ある。まず、工程1では1100″O/3Hrsのスチ
ーム酸化を行ない基板両面にS iO,膜を形成する。
In general, semiconductor devices require two steps: introducing P-type and n-type impurity elements into an n-type Si substrate containing a certain amount of impurities by thermal diffusion at an angle of 1000'0 or more to obtain a p-n junction;
This manufacturing method is described in detail with reference to FIG. 4, which is manufactured by the electrode attachment process before and after step C. Here, the substrate is p='n
Ω''m, FZ method, n-type (P-doped) Si single crystal wafer. First, in step 1, steam oxidation is performed at 1100''O/3Hrs to form a SiO film on both sides of the substrate.

工程2では、周知のホトレジストをマスクとして基板表
面のSiO2膜を除去する。工程3ではp形層を形成す
るB拡散工程で、公知のB、03、BN 、 BBr、
 、 B2H,などを用いた900℃でのデボ工程と、
それに続くドライブ工程とから成る。この場合、表面濃
度lXl0”/m接合深さ50μmとするため12.5
0℃/90Hrsを25960.75%Ntノ雰囲気で
行なっている。
In step 2, the SiO2 film on the surface of the substrate is removed using a well-known photoresist as a mask. Step 3 is a B diffusion step to form a p-type layer, in which well-known B, 03, BN, BBr,
, B2H, etc., at 900°C, and
It consists of a subsequent drive process. In this case, 12.5
The test was carried out at 0° C. for 90 hours in an atmosphere of 25960.75% Nt.

工程4は工程2と同様裏面のSin、を除去する工程で
、工程5は9層を得るためのP拡散工程であり、公知の
POCI、 、 PH3を用いたデポ工程とドライブ工
程とから成り、拡散深さ5μmを得るために1200’
O/ 5 Hrを0.100%雰囲名中で行なっている
Step 4 is a step of removing Sin on the back side, similar to step 2, and step 5 is a P diffusion step to obtain 9 layers, which consists of a deposition step using known POCI, PH3, and a drive step. 1200' to obtain a diffusion depth of 5 μm.
O/5 Hr was conducted in a 0.100% atmosphere.

工程6は、Siに直接液する層にAIを電極材料として
蒸着法で形成する工程、工程7は、蒸着金属膜とSiと
の十分な接着強度を得るために450℃殉分のN!雰囲
気中でのシンタリング処理をおこなう工程である。
Step 6 is a step of forming a layer that is directly applied to Si using an evaporation method using AI as an electrode material. Step 7 is a step of forming an electrode layer using an evaporation method using AI as an electrode material. In step 7, N! This is a process of performing sintering treatment in an atmosphere.

ところで、基板の比抵抗ρは、要求される逆阻止電圧(
以下耐圧と称する)によって選択され、基板の比抵抗p
と、その基板を使った場合に得られる耐圧との関係は文
献により広く知られており、第5図のとおり、比抵抗p
の低下にともない耐圧も低下することになる。ところで
、メサ形ダイオードウェハの製造工程においては、第4
図のような最終の450℃の熱処理工程7で第6図のよ
うにρの低下が発生する。第6図中、横軸は450°C
での熱処理時間、左側の縦軸はρの低下率、右側の縦軸
は測定されたρの値であり、シンタリング時間が長くな
るとeが低下することになる。一方、第7図は耐圧分布
の変化を示すもので、図のように熱処理時間の増加とと
もにeが低下することにより、それにつれて耐圧分布も
低下することになる。
By the way, the specific resistance ρ of the substrate is the required reverse blocking voltage (
(hereinafter referred to as withstand voltage), and the specific resistance p of the substrate
The relationship between the specific resistance p and the withstand voltage obtained when using that substrate is widely known in the literature, and as shown in Figure 5, the specific resistance p
The withstand voltage also decreases with the decrease in . By the way, in the manufacturing process of mesa diode wafers, the fourth
In the final heat treatment step 7 at 450° C. as shown in the figure, a decrease in ρ occurs as shown in FIG. In Figure 6, the horizontal axis is 450°C
The vertical axis on the left is the rate of decrease in ρ, and the vertical axis on the right is the measured value of ρ. As the sintering time increases, e decreases. On the other hand, FIG. 7 shows changes in the breakdown voltage distribution, and as shown in the figure, as e decreases as the heat treatment time increases, the breakdown voltage distribution also decreases accordingly.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記のように従来の半導体装置の製造方法では、p−n
接合を形成後、500 ’0前後の熱処理工程で、n形
基体の比抵抗が初期に比べて低下し、所望の耐圧特性が
得られないという課題があった。
As mentioned above, in the conventional semiconductor device manufacturing method, p-n
After forming the bond, in the heat treatment process at around 500'0, the resistivity of the n-type substrate decreased compared to the initial stage, and there was a problem that the desired breakdown voltage characteristics could not be obtained.

また、従来方法の別の例としてp−n接合形成後、接合
を露出するようにメサ溝を形成し、この溝内に低融点ガ
ラスを埋め込んで作られる様な、云わゆるガラスパシベ
ーション型構造では、Siとガラス界面の除歪のために
500°C前後で60分〜120分アニールする工程が
一般に用いられるが、このような場合には得られる耐圧
分布の低下は非常に大きなものとなる。
Another example of the conventional method is a so-called glass passivation type structure in which after forming a p-n junction, a mesa groove is formed to expose the junction, and low melting point glass is buried in this groove. Generally, a step of annealing at around 500° C. for 60 to 120 minutes is used to remove strain at the interface between Si and glass, but in such a case, the resulting breakdown voltage distribution deteriorates significantly.

この発明は、上記の様な課題を解決するためになされた
もので、500°C前後の熱処理による基板の比抵抗の
低下を抑制し、耐圧特性の低下を防止できる半導体装置
の製造方法を得ることを目的としている。
This invention was made to solve the above-mentioned problems, and provides a method for manufacturing a semiconductor device that can suppress a decrease in specific resistance of a substrate due to heat treatment at around 500°C and prevent a decrease in breakdown voltage characteristics. The purpose is to

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置の製造方法は、n形の抵抗率
eが10Ω・α以上のFZシリコン基板を用いて半導体
装置を製造する方法において、電極を蒸着する工程の前
工程として、1100℃/10Hr相当以上の温度と時
間で、水素雰囲気にて熱処理をおこなう工程を含むもの
である。
The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device using an FZ silicon substrate having an n-type resistivity e of 10Ω·α or more, in which the process is performed at 1100° C./ This process includes a step of performing heat treatment in a hydrogen atmosphere at a temperature and time equivalent to 10 hours or more.

〔作用〕[Effect]

この発明においては、1100℃前後の水素雰囲気での
熱処理工程を導入しており、500°C前後の熱処理を
実施しても基体の比抵抗の低下が発生せず、従がって耐
圧特性の低下が防止される。水素雰囲気の熱処理工程の
効果は、処理の温度が高い程、又処理の時間が長い程効
果があり、温度と時間の関係は装置の能力や経済的な観
点から選択できる。
In this invention, a heat treatment process in a hydrogen atmosphere at around 1100°C is introduced, and even if the heat treatment is performed at around 500°C, the specific resistance of the substrate does not decrease, and therefore the voltage resistance characteristics are improved. Deterioration is prevented. The higher the treatment temperature and the longer the treatment time, the more effective the heat treatment step in a hydrogen atmosphere becomes, and the relationship between temperature and time can be selected from the viewpoint of equipment capacity and economics.

〔実施例〕〔Example〕

以下この発明の一実施例を第1図の工程図で説明する。 An embodiment of the present invention will be described below with reference to the process diagram of FIG.

この工程では工程5の後に水素雰囲気での熱処理工程8
を追加するものであり、他の工程は従来と同様である。
In this step, heat treatment step 8 in a hydrogen atmosphere is performed after step 5.
The other steps are the same as before.

この工程の特性を第2図に示す。この図はρの低下を引
き起こすためのシンタリングの条件を450℃/60分
としたときの図で、水素処理の温度をパラメータとして
、縦軸にρの低下率、横軸は水素処理時間である。この
図から明らかなように、処理時間が長い程、又温度が高
い程、シンタリング工程でのeの低下率が減少すること
がわかる。従って、第3図のように従来方法と比較する
と、ρの低下率が大幅に抑えられていることがわかる。
The characteristics of this process are shown in FIG. This figure is a diagram when the sintering conditions to cause a decrease in ρ are 450℃/60 minutes.The vertical axis is the rate of decrease in ρ, and the horizontal axis is the hydrogen treatment time, using the hydrogen treatment temperature as a parameter. be. As is clear from this figure, it can be seen that the longer the processing time and the higher the temperature, the lower the rate of decrease in e in the sintering process. Therefore, when compared with the conventional method as shown in FIG. 3, it can be seen that the rate of decrease in ρ is significantly suppressed.

この様な現象と効果の原因については、1017ato
r/cntの酸素を含むとされるCZ法で作られたSi
結晶では、400〜550°Cの熱処理によって101
ン慕オーダのドナーの増加が勧測されることは良く知ら
れており、10”7mのように酸素濃度が少ないとされ
ているFZウェハでも、高温で長時間の酸化雰囲気処理
中にSi中の酸素濃度が高まり、水素雰囲気下の処理で
酸素の形態の変化が起こっていることに起因しているこ
とが考えられる。
Regarding the causes of such phenomena and effects, please refer to 1017ato
Si made by the CZ method is said to contain r/cnt of oxygen.
In crystals, 101
It is well known that an increase in the number of donors on the order of 1000 nm is recommended, and even in FZ wafers such as 10"7m, which are said to have a low oxygen concentration, the increase in the number of donors in Si during long-term oxidation atmosphere treatment at high temperatures is well known. This is thought to be due to an increase in the oxygen concentration in the hydrogen atmosphere and a change in the form of oxygen during treatment under a hydrogen atmosphere.

このように、p≧10Ω・cm (5X 10”/ad
 )の比抵抗のn形siを使用する場合に、450°C
でのアニールによって生ずる耐圧低下を防止するには1
100°O/15Hrに相当する水素雰囲気での熱処理
を実施すれば良C)。
In this way, p≧10Ω・cm (5X 10”/ad
) when using an n-type SI with a specific resistance of 450°C.
To prevent the breakdown voltage drop caused by annealing in
It is sufficient to carry out heat treatment in a hydrogen atmosphere corresponding to 100°O/15HrC).

また、この雰囲気を水素にして熱処理する工程は、工程
3のp型拡散や、工程5のn型拡散において実施しても
同様の効果がある。
Moreover, the same effect can be obtained even if the step of heat treatment using hydrogen in this atmosphere is carried out in the p-type diffusion in step 3 or the n-type diffusion in step 5.

〔発明の効果〕〔Effect of the invention〕

この発明はn形の抵抗率eが100・儂以上のFZシリ
コン基板を用いて半導体装置を製造する方法において、
電極と蒸着する工程の前工程として、1100°O/1
0Hr相当以上の温度と時間で、水素雰囲気にて熱処理
をおこなう工程を含むものであり、p−n接合を形成後
における500°C前後の熱処理工程でのn形基板の比
抵抗の低下が抑制され、耐圧特性の低下を防止できる効
果がある。
This invention provides a method for manufacturing a semiconductor device using an FZ silicon substrate having an n-type resistivity e of 100.
1100°O/1 as a pre-process to the electrode and vapor deposition process.
This process includes a process of heat treatment in a hydrogen atmosphere at a temperature and time equivalent to 0Hr or more, and suppresses the decrease in specific resistance of the n-type substrate during the heat treatment process at around 500°C after forming a p-n junction. This has the effect of preventing deterioration of voltage resistance characteristics.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例を示す工程図、第2図はこ
の発明の水素処理時間と比抵抗との関係を示すグラフ、
第3図は同様にシンタリング時間と比抵抗との関係を示
すグラフ、第4図は従来の方法を示す工程図、第5図は
ブレークダウン電圧と比抵抗との関係を示すグラフ、第
6図は従来方法のシンタリング時間と比抵抗との関係を
示すグラフ、第7図は従来のブレークダウン電圧とシン
タリング時間との関係を示すグラフである。図中、8は
水素雰囲気での熱処理工程である。 なお、各図中同一符号は同−又は相当部分を示す。
FIG. 1 is a process diagram showing an embodiment of the present invention, and FIG. 2 is a graph showing the relationship between hydrogen treatment time and specific resistance of the present invention.
Similarly, Fig. 3 is a graph showing the relationship between sintering time and specific resistance, Fig. 4 is a process diagram showing the conventional method, Fig. 5 is a graph showing the relationship between breakdown voltage and specific resistance, and Fig. 6 is a graph showing the relationship between breakdown voltage and specific resistance. The figure is a graph showing the relationship between sintering time and resistivity in the conventional method, and FIG. 7 is a graph showing the relationship between breakdown voltage and sintering time in the conventional method. In the figure, 8 is a heat treatment step in a hydrogen atmosphere. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims]  n形の抵抗率ρが10Ω・cm以上のFZシリコン基
板を用いて半導体装置を製造する方法において、電極を
蒸着する工程の前工程として、1100℃/10Hr相
当以上の温度と時間で、水素雰囲気にて熱処理をおこな
う工程を含むことを特徴とする半導体装置の製造方法。
In a method for manufacturing a semiconductor device using an FZ silicon substrate with an n-type resistivity ρ of 10 Ω・cm or more, as a pre-step to the step of vapor depositing an electrode, a hydrogen atmosphere is heated at a temperature and time equivalent to 1100°C/10 Hr or more 1. A method of manufacturing a semiconductor device, the method comprising the step of performing heat treatment at a temperature.
JP11280288A 1988-05-10 1988-05-10 Method for manufacturing semiconductor device Expired - Lifetime JPH07101693B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11280288A JPH07101693B2 (en) 1988-05-10 1988-05-10 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11280288A JPH07101693B2 (en) 1988-05-10 1988-05-10 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH01282822A true JPH01282822A (en) 1989-11-14
JPH07101693B2 JPH07101693B2 (en) 1995-11-01

Family

ID=14595894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11280288A Expired - Lifetime JPH07101693B2 (en) 1988-05-10 1988-05-10 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH07101693B2 (en)

Also Published As

Publication number Publication date
JPH07101693B2 (en) 1995-11-01

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