JPH01279496A - Method and apparatus for rewriting nonvolatile memory - Google Patents

Abstract

PURPOSE:To facilitate data rewrite to an externally mounted memory by inputting a prescribed address or the like to a prescribed port of a CPU and transferring the address to a nonvolatile memory. CONSTITUTION:Ports A, B are fixed to a prescribed logic level by using a pull-down resistor 8 and a pullup resistor 9 normally through a connector receptacle 5 in A, B input/output terminals 7 of a control CPU 1 connecting to a nonvolatile memory 2. When a connector 3 to which connection pins are connected by a prescribed combination and subjected to coding is plugged into the connector 5, the connection pin 4 is inserted to a connection pin 6, the logic level is fixed to the code set to the connector 3 and all prescribed address, data or instruction code or prescribed information are inputted to the CPU 1 based on the code and when a prescribed code is decided, the storage content of the memory 2 is rewritten.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to rewriting the contents of an external nonvolatile memory in a microcomputer by external data manipulation.

[Conventional technology]

As an example of conventional technology, for example, a microcomputer
When renting or leasing a circuit device, etc., it is necessary to reset the usage time and other data storage contents at the time of rental.For this reason, it is currently necessary to replace the memory or write the internal data to a ROM writer. They use methods such as rewriting it to a predetermined one.

[Problem to be solved by the invention]

In this way, in the case of rental or leased circuit devices equipped with conventional microcomputers, the external nonvolatile memory itself must be replaced each time it is used, or it can be replaced externally with a device such as a ROM writer. Since the structure is such that data can be rewritten, the rewriting operation is not only very complicated and expensive, but also has the problem that only certain technical ideas can perform the operation. This invention was made by focusing on such conventional problems, and involves inputting a predetermined address, data, etc. to a predetermined port of a CPU that controls an external non-volatile memory, and transmitting this to the non-volatile memory. The aim is to solve the above problems by transferring the data to

[Means to solve the problem]

In this invention, a connector (male) is connected to the A and B input/output port terminals of the control CPU, and normally the A and B input/output port terminals are fixed to a predetermined logic, and rewriting to external nonvolatile memory is performed. If the need arises, use a connector (
(female) into the connector (male) by hand-held operation, change the logic of the A and B input/output port terminals of the control 1ffl CP tJ, and then transfer the data to the nonvolatile memory by the control CPU, This allows you to perform the task of rewriting the contents.

[For use]

In FIGS. 1 and 2, the A and 13 output terminals 7 of the control CPU to which the non-volatile memory 2 is connected are normally A and A, respectively, through a side connector (male) 5. The B boat has a pull-down resistor 8 or a pull-up resistor 9, and each terminal is fixed to a predetermined logic. Here, when the connector (female) 3 whose connecting pins are connected in a predetermined combination and coded is inserted into the receiving side connector (male) 5, the connecting pins (female) 4 are connected to the connecting pins (
male) inserted into 6, A. The logic of the B input/output port terminal 7 is fixed to a coat set in the connector (female) 3 through a connecting pin, and based on the coat, all or any of the predetermined addresses, data, command codes, etc. Predetermined information is input to the CPUI, and when the CPUI determines that the code is a predetermined code, the stored contents of the external nonvolatile memory 2 are rewritten.

[First example]

An embodiment of the present invention will be described below with reference to the accompanying drawings. In FIGS. 1 and 2, the No. 7 terminal C7 of the boat C of the control CPtJI is normally biased to H level by the pull-up resistor 8a, but the connector (female)
3 is connected, it changes to L level and the control wholesale CPU
The program flow No. 1 reads the contents of boats A and B, and rewrites the stored contents of the external non-volatile memory 2 according to the contents. For example, if boat A is an address and boat B is data, boat date data (eg, FA) is written to the port address (eg, IA) of the external nonvolatile memory 2. Therefore, the contents of the external nonvolatile memory 2 will be rewritten. Note that these addresses and data values can be processed as necessary by the internal processing of the control cPu1, and in the above case, the upper address is added to address IA to make it (IFIA). Or, data (FA) can be written by specifying the data write area from (IFIA) to (1F2A). This process will be explained with reference to the flowchart of FIG. Boat data reading step・・・Boat A
. Read the status of B, C, and interrupt ports not shown, ie, L or 11 (STI). Connector connection status step: Checks whether or not connector 3 is connected to connector (male) 5 based on the logic status of boat C7. If the logic is correct, connect it. (Sr1). Code processing step: Reads the data entered into boat B and checks whether the data is a predetermined code (Sr1). In this step, it is checked whether the connector (female) 3 is a regular one. Time integration step: For example, the working time is integrated by counting clock pulses from a timer (not shown) (Sr1). E2FROM (non-volatile memory 2) data update sleeve...The address of the non-volatile memory 2 specified to the boat by the connector (female) 3 is connected to the address of the boat B.
The data entered manually is updated (ST5). Display step: The integrated time is displayed on a display (not shown) (ST6). Next, the operation of the above configuration will be explained. In Fig. 1, when the power is turned on, the program proceeds to the initial setting step, initializes the RAM etc. in the CPtJ l, reads the boat data, and performs step (STI).
The time information is input from the external interrupt board in , and it is determined in the connector connection status step (ST2) that the connector (female) 3 is not mated to the connector (male) 5.
Thereafter, in a time integration step (ST4), the time elapsed since the power was turned on is integrated, and the time is displayed in a display step (ST6), and the process returns to the boat data reading step (ST I ). Here, when the connector (female) 3 is fitted to the connector (male) 5, it is determined in the code comparison step (ST3) whether the code information supplied from the connector (female) 3 is a predetermined code. , if it is determined to be correct, E2F
In the ROM data update step (ST3), the stored contents of the non-volatile memory 2 are updated, and the process returns to the boat data reading step (ST1) via the aforementioned steps (ST4) and (ST6). In addition, if the code information is not regular, even if the connector (female) 3 is fitted to the connector (male) 5, the memory contents of the nonvolatile memory are not rewritten, and the above-mentioned step (ST4
) and (ST6) to return to the vote data reading step (STI).

[Second example]

In this embodiment, in FIG. 1 explained in the first embodiment,
An ignition switch IO was added and its output was supplied to the control B c p U 1, so that the next IGN in FIG. 5 as shown in FIG. A step (ST7) for determining the number of SW (ignition switch) switching is added. Step for determining the number of IGN and SW switching (ST7)...
. . . The number of times the ignition switch 10 has been operated is read from, for example, C6 in FIG. It is determined whether the OFF operation has been performed, and if it is determined that the normal operation has been performed, the E" FROM data update step (
The process proceeds to ST5), and if it is determined that the operation is not normal, the process proceeds to a time adjustment step (ST4). In the above embodiment, the logic of the board C7 is checked in the connector connection step (ST2), and the connector (
It was determined whether the connector (female) 3 was mated to the connector (male) 5, but the IN
Check the logic of the T (interconnected) terminal, for example “
It is also possible to proceed to the code comparison step (S T 3) when the logic changes from ``H'' to ``L''. In this case, since the process of rewriting the non-volatile memory 2 is not performed in the main flowchart, the processing speed can be reduced. without affecting
The probability of erroneous operation of the nonvolatile memory 2 can be reduced. In addition, in the above two embodiments, two codes, address and data, are specified, but the connector (
The coat formed by the connection pin 4 of (female) 3 may be made to correspond to commands such as all clear and all set of the nonvolatile memory 2. In this case, one code specification is required, so the number of ports can be reduced. It is possible to rewrite the stored contents as described above. When using the instruction set, by setting the boat to read data before connecting the connector (female) 3, the control CPU
Trouble caused by malfunction in step 1 can also be prevented.

【Effect of the invention】

As explained above, in this invention, data can be rewritten in an external non-volatile memory by inserting a connector whose connecting pins are connected in a predetermined combination into the connector connected to the input/output board of the control CPU. , has the advantage that it can be easily executed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention. FIG. 2 is a combined connection diagram of a CPU input/output board and connector in one embodiment. FIG. 3 is a sequence flowchart for the included routine. FIG. 4 is a sequence flowchart of the data rewriting routine shown in the embodiment. FIG. 5 is a flowchart in the case of the embodiment. FIG. 6 is a flowchart for a modified example. In the figure, l is a control CPU, 2 is a non-volatile memory,
3 is the connector (female), 4 is the connection pin (female), 5 is the receiver side connector (male), 6 is the connection pin (male), 7 is the input/output boat terminal, 8 is the level of the boat A terminal fixed. 8a is a pull-down resistor for boat C terminal, 9 is a pull-amp resistor for fixing the level of boat B terminal, 1
0 is the ignition switch. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Patent applicant: Kanto Seiki Co., Ltd. (2 others) Figure 4 TN Figure 3

Claims (2)

[Claims] (1) Connect the connection pins (4
) are connected in a predetermined combination, and the CPU (1) reads the code resulting from the predetermined combination, thereby rewriting the memory contents of the non-volatile memory (2) connected to the CPU. A nonvolatile memory rewriting method characterized by: (2) A CPU (1) having multiple input terminals, and
Non-volatile memory whose memory contents can be rewritten by U (
2) A microcomputer comprising: a connector (5) having connection pins (4) combined in a predetermined connection relationship and detachably fitted to the plurality of input terminals (7); Connect the connecting pin (6) of the connector to the CP
A rewriting device for a nonvolatile memory, characterized in that when the nonvolatile memory (2) is connected to an input terminal of the nonvolatile memory (2), the stored contents are rewritten.