JPS6354642A - Memory controlling circuit - Google Patents

Abstract

PURPOSE:To shorten the time used exclusively for write of a data by a CPU by constituting the central processing unit so that a data is written by an interruption processing, the interruption is released by an interruption request signal stopping circuit, and a preparation for the next data write is executed. CONSTITUTION:By a Q output of an interrupting FF circuit 6 a CPU1 is allowed to generate an interruption request signal. The CPU1 receives this interruption request signal and starts a processing of an interruption routine. In this interruption routine, the CPU1 executes data write to the next byte, and thereafter outputs a reset pulse from an I/O port 5 in order to reset the Q output of the interrupting FF circuit 6. Also, even in case of writing a large quantity of data, the same operation is repeated. By such an interruption processing, write of an erasable nonvolatile semiconductor memory (E<2>PROM)4, therefore it is unnecessary to hold in a program until the E<2>PROM4 is released as to its re-write and the time when the CPU1 is used exclusively for write of a data can be shortened.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a memory control circuit, and in particular, the central processing unit (hereinafter referred to as CPU) of the memory control circuit is an electrically writable/erasable nonvolatile Semiconductor memory (hereinafter referred to as
It is called E2P ROM. ) relates to a memory control circuit that reduces the amount of time it takes to write data to a memory device.

[Prior Art] Conventionally, in a memory control circuit that writes data to an E2PROM, a CPU determines whether writing is possible through an input port.

FIG. 4 shows the configuration of a conventional memory control circuit.

In the figure, 1 is a CPU, and 2 is a read-only memory (hereinafter referred to as ROM) in which a CPU processing program is written.
That's what it means. ), 3 is a read/write memory (hereinafter referred to as
It is called RAM. ).

Reference numeral 4 denotes an E2FROM, which retains stored data even when the power is turned off, and outputs a rewrite determination signal (hereinafter referred to as an R/B signal) for determining whether data can be written. 5 is an I10 boat, CPU
is the R/E of E'PROM4 through this I10 boat 5.
3 Monitor the signal.

FIG. 5 shows a flowchart of a program for writing continuous data into the E2PROM.

In the above configuration, when writing continuous data to E2FROM4, the CPU writes R of E2PROM4 through I10 port 5 to determine whether the next byte can be written each time one byte of data is written.
It was necessary to continue monitoring the /B signal. For this reason, 22
When writing a large amount of data to FROM4, use R/
The amount of time spent monitoring the B signal increased, and the time the CPU was used exclusively for writing data increased, reducing the processing capacity of the CPU.

[Problems to be solved] In the conventional memory control circuit described above, in order to write to the E2PROM, the CPU continuously monitors the E2PROM rewrite determination signal from the I10 port every time one byte is written, and waits until the next byte is written. The program had to wait until it was available. And E2P
When writing a large amount of data to the ROM, there is a problem in that the waiting time increases the amount of time the CPU is occupied with writing, reducing the processing capacity of the CPU.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a memory control circuit that reduces the time that the CPU spends writing data to E2PR○M and improves the processing performance of the CPU. do.

[Means for solving problems] In order to achieve the above object, the memory control circuit of the present invention has the following features:
A circuit that generates an interrupt request signal based on a rewrite determination signal of an electrically writable/erasable nonvolatile semiconductor memory, and a circuit that stops the output of the interrupt request signal generation circuit according to a command from a central processing unit, The arithmetic processing unit accepts the interrupt request signal, writes data in interrupt processing, and causes the interrupt request signal stop circuit to cancel the interrupt.
It is configured to prepare for the next data write.

As a result, data writing can be performed by simple interrupt processing, thereby making it possible to shorten the time occupied by the CPU for data writing.

[Example] Hereinafter, the present invention will be described in detail based on the drawings. Note that parts common to or corresponding to those of the conventional example are denoted by the same reference numerals.

1 is a block diagram showing the configuration of a memory control circuit according to an embodiment of the present invention, FIG. 2 is a timing chart of the memory control circuit of FIG. 1, and FIG. 3 is a program of the memory control circuit of FIG. 1. It is a flowchart which shows.

In FIG. 1, reference numeral 6 denotes a flip-flop circuit (hereinafter referred to as an FF circuit) for generating an interrupt request signal.

), when E2FROM4 is write-protected, that is, R
When the /B signal is at the "Ljl" level, the Q output is at the "L" level. Then, the E'PROM4 is in a write-enabled state, that is, the R/B signal changes from the '°L' level to II HI.
When it reaches the T level, the Q output becomes the II HIT level. Furthermore, after writing 1 byte data, when a reset signal is output from the I10 port 5 in response to a command from the CPUI, the Q output becomes the II LIT level again.

In the above configuration, after writing 1 byte data to E'PROM4, writing is disabled for -1 moment, and during this time the R/B signal is IT Ll! level. Then, when it becomes possible to write data to the next byte, the R/white signal becomes “L”.
level to "H" level, and the Q output of the interrupt FF circuit 6 generates an interrupt request signal to the CPUI.The CPUI accepts this interrupt request signal,
As shown in FIG. 3, processing of the interrupt routine is started. In this interrupt routine, the CPUI writes data to the next byte, and then outputs a reset pulse from the I10 port 5 in order to reset the Q output of the interrupt FF circuit 6. Furthermore, the same operation is repeated when writing a large amount of data.

In this way, in this embodiment, the E2PR is
In order to write to OM4, E2PR is used as before.
There is no need to wait in the program until OM4 is released from rewriting, and the time that the CPU is exclusively used for writing data can be shortened. Further, the CPUI can perform other processing as necessary.

[Effects of the Invention] As explained above, the present invention has a simple circuit configuration that allows the CPU to
This has the effect of reducing the time spent writing data in the E2PRoM and improving the processing capacity of the CPU.

Furthermore, by applying the present invention to a control/monitoring device using a general microcomputer that writes a large amount of data using E2FROM and needs to retain the stored data even if the power is turned off, It is possible to effectively utilize the idle time of the microprocessor.

[Brief explanation of the drawing]

1 is a block diagram of a memory control circuit according to an embodiment of the present invention, FIG. 2 is a timing chart of the memory control circuit of FIG. 1, and FIG. 3 is a flowchart of a program of the memory control circuit of FIG. 1. FIG. 4 is a block diagram of a memory control circuit according to a conventional embodiment, and FIG. 5 is a flowchart of a program of the memory control circuit of FIG.

Claims (1)

[Claims] In a memory control circuit that writes data to the electrically programmable and erasable nonvolatile semiconductor memory by a central processing unit, an interrupt request signal is generated based on the rewrite determination signal of the electrically programmable and erasable nonvolatile semiconductor memory. and a circuit for stopping the output of the interrupt request signal generation circuit according to a command from the central processing unit, and the central processing unit, upon receiving the interrupt request signal, performs data writing by interrupt processing; A memory control circuit configured to release an interrupt by the interrupt request signal stop circuit and prepare for writing the next data.