JPH01279344A - Writing device - Google Patents

Abstract

PURPOSE:To ensure the secret protection and test functions of a built-in memory by producing the read-out memory information and the expected value used for decision of the propriety of said memory information via the same information converting circuit. CONSTITUTION:In a microcomputer MCU the read data RD is converted into the read data RD' by an information converting circuit TB for the purpose of protection of a program stored in an EPROM. Then the data RD' is transmitted through a specific input/output port PO. At the same time, a writing device WRD which writes the information into the EPROM contains an information converting circuits TB' of the same constitution as the circuit TB so as to verify the writing job, i.e., to perform a test that decides whether the write data is correctly stored or not.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a writing device, and is applicable, for example, to a writing device for a microcomputer that has a built-in non-volatile memory circuit in which confidential data or programs are stored. It is about effective techniques.

[Conventional technology]

One-chip microcomputers with a built-in EPROM (erasable and programmable read-only memory) are sold by Hitachi under the 'HD63701' series and 'rHD63705' series. In this one-chip microcomputer, EP
Since it contains ROM, it is possible to write any user program.

[Problem to be solved by the invention]

If an EPROM is included in which programs such as those described above are stored, it is necessary to add a function to read out whether or not the written programs have been written correctly. However, when such a reading function is added, software that is desired to be kept confidential can be easily read out by a third party, and its security cannot be protected.

Therefore, it is conceivable to provide a key code and restrict its reading, but this is not sufficient from the viewpoint of security protection.

SUMMARY OF THE INVENTION An object of the present invention is to provide a writing device for a semiconductor integrated circuit device that has both the functions of protecting the security of information stored in a built-in storage device and testing the same.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, for an information processing device that includes an electrically writable nonvolatile memory circuit and has a function of outputting data to the outside through an information conversion circuit that converts read data from the nonvolatile memory circuit under certain conditions, A writing device is prepared that includes the same information conversion circuit as described above and has a function of performing a read test of the information processing device using write data passed through the information conversion circuit as an expected value.

[For production]

According to the above-mentioned means, since the read stored information and the expected value for determining its acceptability are generated through the same information conversion circuit, it can only be performed by a person who has a writing device equipped with the information conversion circuit. Read test becomes possible.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a writing device according to the present invention and a one-chip microcomputer to which writing is performed using the writing device.

The microcomputer MCU will be explained in detail later, but it includes a microprocessor CPU, an EFROM in which programs are stored, a RAM (random access memory) used for data storage, a timer TM, etc. I'm here. In order to protect the program stored in the EPROM, the microcomputer MCU of this embodiment converts the read data RD into read data RD' by the information conversion circuit TB and outputs it from a specific input/output port PO. .

Since the microcomputer MCU has the above configuration, the write 1i for writing to the EPROM is
The write device WRD has the same information conversion circuit TB'' as described above in order to verify it, in other words, to test whether the write data is correctly stored or not. ,
It consists of the following circuits.

ROM (read only memory) is the master RO
M, and EP in the microcomputer M CU
A program to be written to the ROM is stored. Although not particularly limited, a RAM' is provided as a buffer, and during a write operation, the data in the ROM is transferred to the RAM', and from this RAM' the data is transferred to the E through a specific input/output port P○ of the microcomputer MCU.
Written to PROM. Note that control signals necessary for write/read operations of the EPROM are also supplied through the input/output port PO. Furthermore, in the case where the write high voltage is supplied from an external terminal instead of the configuration in which the write high voltage is generated by an internal booster circuit, the high voltage is also supplied from the write device WRD.

The information conversion circuit TB" is the above-mentioned microcomputer MC.
It is used during the read test of U's EFROM. That is, when a read test is instructed by the control circuit CNT, the information conversion circuit TB'' is activated by the signal VF, and the write data WD read from the master ROM is converted into an expected value WD for the read test. '
Convert to

The writing device WRD sends an EOR to the microcomputer MCU in parallel with reading from the master ROM and generating expected values by the information conversion circuit TB.
Instructs to read OM.

As a result, the microcomputer MCU enters the test mode, reads out the information stored in the EPROM, converts the data using the information conversion circuit TB, and outputs the data through the input/output port PO. The writing device WRD receives the read data RD' outputted from the input/output port, and compares the expected value WD" with the digital comparator CMP to form a mismatch detection signal. In the figure, the read data RD''' is shown to be transmitted to CMP through RAM', but it is transmitted to the comparator CMP through an internal data bus. In addition, the master ROM is connected to the above-mentioned RAM" and the information conversion circuit T.
Although each of B' is depicted as having two outputs, it actually has one output terminal, and signals are transmitted as described above in accordance with each operating mode.

When the writing device WRD has RAM'' as a buffer memory as described above, the writing device WRD may first specify the test mode to the microcomputer MCU and instruct it to read the EPROM. In this case, , the read data RD from the EPROM is converted into data RD'' by the information conversion circuit TB as described above, and is once taken into the RAM'' as a buffer memory of the writing device WRD. EPROM
When all of the storage information of
Enables the reading of M and the operation of the information conversion circuit TB', and instructs the reading of the RAM". The converted write data WD' from the master ROM thus read and the buffer memory The EPROM read data RD' which has already been transferred to the RAM' is compared with the read data RD' by the digital comparator CMP, and a match/mismatch is determined here, and if there is a mismatch, a mismatch detection signal FL is generated.

Note that the writing device WRD has the master ROM, R
Address signal and EPRO for access of AM'
Although it has an address generation circuit that generates an address signal for accessing M, it is omitted in the figure.

FIG. 2 shows the above-mentioned one-chip microcomputer MC.
A block diagram of one embodiment of U is shown. In the figure, the area surrounded by a broken line constitutes one integrated circuit, and each circuit block formed here is fabricated on one semiconductor substrate such as single crystal silicon using known semiconductor S integrated circuit manufacturing technology. Formed above.

The symbol CPU is a microprocessor, and its main constituent blocks are exemplarily shown as a representative.

A is accumulator, X is index register, CC
is the condition code register, SP is the stack pointer, PCH and PCL are the program counters, and CPU-
C0NT is a CPLI controller, and ALU is an arithmetic logic unit.

The configuration of such a microprocessor CPU is known, for example, from ``Fundamentals of Microcomputers'' by Mitsuharu Yada, published by Ohmsha on April 10, 1978, and a detailed explanation thereof will be omitted.

Indicated by symbols POI to PO4 are input/output ports, which contain data transmission direction registers therein. The above input/output ports PO3 and PO4 are 8bee/
In addition to being used for inputting and outputting data, it also has the function of sending out an address signal included in the path BtJS, which will be described later. For example, input/output port PO3 and bus B
A multiplexer is provided between the multiplexer and the tJS, and switching between the data and the address is performed by switching the multiplexer.

Further, the input/output port PO4 becomes a data input/output port or an address output port depending on the setting of the operation mode.

The input/output port P○2 is not particularly controlled, but consists of six terminals, and the input/output direction is determined by its data direction register. The 6-bit output sofa is a three-state output sofa, and when used as an input, the output sofa is in a high impedance state.

The four terminals of PO2 (input/output capo) are used for mode programming during the reset period. The levels of these four terminals at the time of reset are held in the launch circuit of input/output port PO2. Types of mode settings using the above four terminals include, for example, single-chip mode, ex-band multiplex mode, ex-band multiplex mode, and test mode as described below. Such mode identification is performed by the mode determining circuit MODE.

What is indicated by the symbol O8C is an oscillation circuit, which forms a highly accurate reference frequency signal using an external crystal resonator Xtal, although it is not particularly limited. This reference frequency signal forms the clock pulses required in the microprocessor CPU. Further, the reference frequency signal is also used as a reference time pulse of a timer.

This timer consists of counter C0UT, prescaler PR
and a controller CONT. These timers also include watchdog timer circuits.

The symbol RAM is a random access
It is a memory and is used, for example, as a storage circuit for -time data, a stack area, or a general-purpose register.

What is indicated by the symbol EFROM is an erasable and programmable read-only memory, in which programs and the like for various information processing are mainly written.

This EPROM is made non-erasable by not having an erasing window in its puff cage, although this is not particularly limited. That is, even though the circuit element itself is configured as an EPROM, writing can only be performed once.

The above circuit blocks are connected to each other by a bus BUS, with the microprocessor CPU as the center. This bus BUS includes a data bus, an address bus, and various control signal lines.

The included control circuit INTC receives an interrupt signal Nt,
It performs interrupt control operations for IRQ. Furthermore, the interwoven control circuit TNTC may include a halt control circuit and a reset control circuit. In this case, the corresponding input signal HALT,
RES (not shown) is supplied. Further, as the input terminal for such interrupts, etc., any one of the input/output ports P01 to PO4 may be shared.

FIG. 3 shows an information conversion circuit TB provided in the microcomputer MCU and the writing device WRD, respectively;
A circuit diagram of one embodiment of TB' is shown.

For example, when a program or data is written in units of 8 bits (1 byte) consisting of bits Do-D7,
EPROM has additional bits PO and PL consisting of 2 bits.
is added to each program or data. Therefore, in the EPROM of this embodiment, memory access is performed in units of 10 bits.

10-bit signal DO~D read from EFROM
7, PO, and PI are temporarily held in latch circuits FF0 to FF9, although they are not particularly limited.

Among the output signals DO to P1 of the launch circuits FF0 to FF9, DO and Dl are respectively supplied to the inverting circuit IVO. The inverting circuit I■0 includes switches 30 and 31 that selectively switch between the output signal of the inverter circuit and its input signal.
It consists of These changeover switches SO and 81
The switching is instructed by the additional bit PO. For example, when the signal PO is at a high level, the switches SO and SL transmit inverted versions of DO and DI using an inverter circuit, and when the signal PO is at a low level, the switches SO and SI transmit Do and DI as they are. The bits of the output signal passed through the inverting circuit vO are selectively exchanged by a switch circuit SWO constituted by switches S2 and 83. Switches S2 and 83 are instructed to switch by additional bit P1.

For example, if the signal P1 is at a high level, the switches S2 and 33 transmit Do and DI interchangeably, and the signals P1 and DI are switched.
If O is low level, Do and Di are transmitted as they are. For each of the other two bits D2 and D3, D4 and D5, and D6 and D7, inverting circuits rVl to IV similar to the above are used.
3 and switch circuits SW1 to SW3 are provided.

These switches SO~83 etc. are the transmission gate MO3F.
It is constructed using an ET or a gate circuit.

As a result, the 8-bit signals DO' to D7'' output from the information conversion circuit TB (TB') are converted into 1R signals according to the additional bits PO and PI with respect to the original data Do-07. be done.

In this configuration, even if bits DO-D7 are the same program word or data, they are converted into 4i1 by the combination of additional bits PO and Pl. 4 as above
In normal conversion, you might think that it is small, but if you look at the converted data DO゛~D7°, data with different bit patterns may be output as the same data, so it is possible to make it virtually impossible to decipher the software. In other words, in order to decipher the entire program, 4 units are required for each unit of program words.
This is because it requires a huge amount of data processing to make the exact changes and combine them as many times as there are program tests.

If the additional bits are increased to 3 or 4 bits,
Since many combinations of the above inversions and permutations can be made, it becomes even more difficult to decipher them.

In the embodiment of FIG. 3, means may be added to enable the above-mentioned additional pins PO and Pl in the test mode. In this configuration, in the test mode, the additional bits PO and Pl are enabled, and a corresponding bit-converted signal as described above is output. At times other than the test mode, in other words, when a program stored in the EFROM is executed by the microprocessor CPU, the additional bits PO and Pi are invalidated and forced to logic "O". As a result, the signals DO to D7 read from the EPROM are output as they are. In this case, external reading of the EPROM is permitted only in the test mode. With this configuration, the output circuit of the EPROM can be provided with the information conversion circuit and coupled to the data bus.

The information conversion circuit TB as described above may be built in the readout circuit of the EPROM, or may be provided in any of the input/output capacitors P2 to P4 that output data. In this case, the EFROM read signal is read to the microprocessor CPtJ via the internal data bus.

In this embodiment, the writing device WRD also has the same information conversion circuit TB" and converts the same write data to form an expected value. Therefore, the read test using the data converted for security protection is performed. It becomes possible.

FIG. 4 shows a block diagram of another embodiment of the information conversion circuits TB, TB''.

In this embodiment, instead of providing additional bits as described above, the information conversion circuits TB, TB'' count the number of logic "1"s in the read signal from the EPROM and output the counting result. Consists of circuit AU.For example, when the EPROM is read out in 8-bit units like Do-D7 as described above, the output conversion signal is
It is compressed into 4-bit data such as DO~D3'.

This configuration makes it virtually impossible to decode the data unless all bits are logic "1" and logic "O". For example, even if the count value is 7, it is
7 is 01111111.10111111.11011
This is because there are as many as 8 types such as 111...11111110. As the count value decreases, the number of combinations increases.

With this configuration, during a read test, it is possible to detect that one specific bit among the 8 bits is inverted from logic "1" to logic "0" or vice versa. This makes it possible to indirectly determine whether the product is good or bad. Normally, EPR determined to be good through screening etc.
Because it writes to OM, one of the two bits changes from logic “0” to logic “1” and the other changes to logic “1”.
The probability of a defect in which the value is reversed from 0 to logic 0 is extremely low. Therefore, the 1-bit defect detection function can also be used as a sufficient determination of the quality of written information.

In order to make it difficult to decipher all bits of logic "O" and logic "1", for example, if the data consists of 8 pins as described above, the number of bits to be output is limited to 3 bits, and the DO"
It is very good to output count values from 0 to 7 using ~D2'. In this case, the count output will be 0 whether all bits are logic "O" or logic "L", making it difficult to distinguish between them.

In this case, all bits written to logic “0” are
Since all bits are not read as logic "1" or vice versa, there is no problem in read determination.

The effects obtained from the above examples are as follows. That is, (1) an information processing device that includes an electrically writable nonvolatile memory circuit and has a function of outputting data to the outside through an information conversion circuit that converts read data from the nonvolatile memory circuit under certain conditions; On the other hand, a writing device is provided which includes the same information conversion circuit as described above and has a function of performing a read test of the information processing device using write data obtained by passing through the information conversion circuit as an expected value. In this j4 configuration, the read memory information and the expected value for determining its acceptability are generated by connecting the same information conversion circuit, so it is necessary to have a writing device with that information conversion circuit. This has the effect that reading tests can be performed only by a person who is a person.

(2) The above-mentioned information conversion circuit shall receive the stored information stored in the built-in storage device and invert the information bits and/or replace other information bits using the additional bits of the stored information. In the operation mode in which the information is output to the outside, the read information from the storage device is passed through the information conversion circuit, thereby making it possible to perform a read test of the write signal, and also to make it possible to test the read signal of the write signal without knowing the contents of the additional bits. This has the effect of preventing third parties from decoding the written data.

(3) The information conversion circuit receives the stored information stored in the built-in storage device, counts the number of logic "0" or logic "1" in the stored information, and outputs it. By providing a circuit and in an operation mode in which the stored information is outputted to the outside, information read from the storage device is passed through the information conversion circuit.
In addition to making it possible to perform a read test (determination of pass/fail) of the write signal, it is also possible to substantially prevent a third party who does not know the contents of the write bit pattern from decoding it.

(4) After reading test by fuse means etc.
Compared to the EPROM which prohibits any external output function, it is extremely convenient for failure analysis and maintenance in the market because those who know the contents of the program and data can test the contents at any time. You can get the effect of becoming something.

(5) The writing device does not have a conversion circuit that reversely converts the converted information, but uses the same information conversion circuit that the microcomputer has to form the expected value. Even if a third party obtains the data and performs a read test, it is a comparison of essentially meaningless data, so even if a third party performs a read test, confidentiality can be maintained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the information conversion circuit can take various embodiments such as a configuration in which in addition to inverting or exchanging signals, addition or multiplication with additional bits or previous data is performed. RAM as buffer memory
o is not particularly required and can be omitted. The master ROM may be other storage devices such as floppy disk memory or the like. In this way, the internal configuration of the writing device can adopt various embodiments provided that the expected value is generated using the information conversion circuit.

Furthermore, in a one-chip microcomputer MCU, the method 1i1jJ for setting the test mode may be made private, or a keyword may be required for setting the test mode.

By doing so, the security of the EFROM of the microcomputer may be further strengthened. The system configuration of the l-chip microcomputer can take various embodiments, and the nonvolatile memory circuit may be anything electrically writable, such as EPROM or EEPROM.

This invention has a one-chip microcomputer, various games using the same, an information processing function for performing various information processing according to a program stored in a so-called IC card or a built-in device, and a function for converting and outputting the program. It can be widely used in writing devices for various semiconductor integrated circuit devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, it is an information processing function that includes an electrically writable non-volatile memory circuit and outputs it to the outside through an information conversion circuit that converts read data from the non-volatile memory circuit under certain conditions. A writing device is provided with the same information conversion circuit as described above, and a read test of the information processing device is performed using write data passed through this information conversion circuit as an expected value. In this configuration, since the read stored information and the expected value for determining its acceptability are generated through the same information conversion circuit, the read test can only be performed by a person who has a writing device equipped with the information conversion circuit. It becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a writing device according to the present invention and a l-chip microcomputer in which writing and reading tests are performed using the writing device, and FIG.
FIG. 3 is a block diagram showing an example of an information conversion circuit provided in the writing device and microcomputer; FIG. 4 is a block diagram showing an information conversion circuit provided in the writing device and microcomputer; FIG. FIG. 3 is a block diagram showing another embodiment of the conversion circuit. WRD...Writing device, ROM...Master ROM,
TB, TB'...information conversion circuit, CMP...digital comparator, CNT...control circuit, rvo~
IV3...inversion circuit, 5wo-5W3...changeover switch circuit (bit swapping), SO~S4...switch, FFO~FF9...lasoji circuit, AU...addition circuit,
CPU...Microprocessor, CPU-C0NT...
CPU controller, ALU...arithmetic logic unit, A...accumulator, CC...condition code register, SP...stack pointer, PCI, PC
L: program counter, RAM: rung access memory, EPROM: erasable and programmable read-only memory, INTC: interwoven control circuit, P○1 to PO4: input/output board, ○
SC...Oscillation circuit, C0UT...Counter, C0NT...
・Controller, PR・・Prescaler, BUS・・Bus, MODE・・Mode determination circuit

Claims (1)

[Claims] 1. Information that includes an electrically writable nonvolatile memory circuit and has a function of outputting it to the outside through an information conversion circuit that converts read data from the nonvolatile memory circuit under certain conditions. A writing device for a processing device, the writing device comprising:
A writing device comprising the same information conversion circuit as described above, and having a function of performing a read test of the information processing device using write data passed through the information conversion circuit as an expected value. 2. The writing device according to claim 1, wherein the information processing device is a one-chip microcomputer that performs information processing operations according to a program stored in a nonvolatile storage circuit. 3. Writing according to claim 1 or 2, wherein the information conversion operation by the information conversion circuit combines the inversion of information bits and the replacement of other information bits using additional bits. Device.