JPH01278146A - Packet switching electronic system - Google Patents

Abstract

PURPOSE: To improve reliability and communication speed of a system by configuring by means of plural processing units which are mutually connected by means of four communication lines. CONSTITUTION: A control function is assigned to control units 1 and 2, a signal conversion and packet switching function is assigned to packet switches 3-5 and a man-machine communication function is assigned to an auxiliary unit which forms a console 6. Then, four internal information transfer buses 7 execute mutual communication among respective units, so that the all of the processing units can communicate with the others. Thus, the reliability of communication and communication speed are improved.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a communication system between computers, and in detail,
The present invention relates to a novel electronic system for packet switching having two control units and up to 34 packet switches interconnected by main communication lines.

BACKGROUND OF THE INVENTION A plurality of computer terminals interconnected by telephone lines or other communication lines and capable of transmitting and processing information according to different programs stored at different locations and on different devices within a system. Packet switching electronic systems utilized are known.

(Problems to be Solved by the Invention, Means and Effects) The present invention relates to a packet switching system designed to be used as a switching center and as a data communication relay device.

The center of the network created by this system performs packet switching according to substantial circuit technology. With this technique, a packet switching network controls communications between two subscribers without physically connecting them.

The storage and retransmission capabilities of the network allow subscribers to remain connected to each other until the end of the communication.

The functions performed by this system are as follows.

Control function Signaling function Packet switching function Man-machine communication function Among these functions, the purpose of the control function is to manage the services and monitor the operation of the entire system. The purpose of the signaling function is to exchange information between subscriber terminals and other network centers to create, maintain and store information. The packet switching function is to store, process, and retransmit packets between the actual input and output circuits.

The purpose of the man-machine communication function is interaction and interaction between the operator and the system for operation and maintenance.

The structure of this system is based on the concepts of function distribution and load distribution. According to the concept of functional distribution, centers are organized on the basis of units specified in the performance of the different functions mentioned above. Based on the load distribution concept, the system distributes the message processing load to different parts of its functional units and, if necessary for the reliability of the system, the message processing load is shared during normal operation and It is equipped with other units which, under certain conditions, allows one of them to handle the entire load of this system.

It is an object of the present invention to provide an electronic system for packet switching consisting of a plurality of processing units interconnected by four communication lines. Two of the processing units, together with the console connected to them, act as control units, and the remaining units become packet switches. These two types of processing units can contain and process programs including application, maintenance and test programs.

It is another object of the present invention to provide an electronic system for packet switching that is capable of receiving and processing information from multiple stations and that is operable to overcome various fault conditions while remaining functional.

(Embodiments and Effects of the Invention) FIG. 1 shows the basic configuration of the system of the present invention. In this configuration, control functions are provided by control unit 1.2, and signaling and packet switching functions are provided by packet switches 3, 4.
5 and man-machine communication functions are respectively assigned to the auxiliary units forming the console 6. Internal information transfer bus 7 provides intercommunication between the individual units of the system.

Center Structure The center has a multiprocessing structure in which the individual processing units communicate with each other by a common information transfer bus system.

The structure of this center is shown in FIG.

The processing functions of this center are performed by a single processing unit, which can be increased in a modular manner according to the needs of this center. This processing unit is created by a microprocessor, its logic and associated peripherals, its memory and a certain number of interfaces for device connections.

Depending on whether these devices are peripheral devices for man-machine communication or transmission lines, this processing unit is called a control unit 1.2 or a packet switch 3, 4.5.

All processing units may communicate with each other via a common bus. There are four such buses in this system to increase the reliability and speed of communication. Access to these busbars is provided by busbar access peripherals 27, 28, 29, 46, 47.
．． 48. A console 6 containing the independent peripheral units necessary for man-machine communication is connected to 1 and 2 by suitable peripheral interfaces. The transmission line is connected to line interface port 31゜32.33 which will be described later.
3.4.5 to the packet switches or computers 3.4.5 that connect them.

The internal structure of the processing unit will be described next.

Controller unit The control unit has the following functions:

Management of system operation Automatic maintenance of the system Control of peripheral devices of the system Measurement and quantification of the system The load for performing these functions is distributed between the two control units 1, 2 in normal operation of the center. In the event of a failure, one control unit 1 or 2 can handle all functions. In order to handle this failure case, each of the control units 1, 2 is constantly informed of the operating functions of the other.

Each control unit 1, 2 internally has a local bus 14.1
5 through which peripheral devices communicate with the processor. The processor 16 or 17 executes a control program stored in its local memory 18 or 19. These peripherals connect to the local bus by corresponding interfaces and interrupt the processor for information exchange by means of interrupt control peripherals 20-21. Peripheral memory 22, event register unit 2
3. Control and display unit 24, alarm unit 2
5 and day clock 26 constitute this system console.

Peripheral memory 22 is a mass storage device that assists in programming the system. Event register unit 23
is for writing all events that occur during the operation of the center. A control and display unit allows the operator to interact with the machine. Alarm unit 25
This system includes audible and visual alarms. The day clock 26 is synchronized with the clock of each processing unit and displays local time on a display device. Impedance adapters 10.11,1 on both sides of the common busbar
There is 2.13.

The maximum number of peripheral devices that can be connected to one control unit is 4.
It is 4. Access to the common bus for transferring information to and from others within these units is controlled by devices called bus access peripherals (27, 28, 46, 47, 48).

packet switch The following basic functions are assigned to the packet switch.

Control of signals from one subscriber and network - Control of data reception/transmission by line interfaces - Control of data transfer by a common bus between the packet switch itself and other packet switches - Exchange with the control unit by a common bus The center of the subsystem measurement and quantification network can include up to 34 packet switches. A control unit that never performs a packet switch function has no line interfaces, but a switch packet unit generally can have a peripheral interface, and the internal structure of a packet switch generally does not have this type of interface. is the same as the control unit.

In this way, the packet switch is local bus 34.35
．． 36, including local memories 40, 41 .
42, interrupt control peripherals 43, 44, 45, and a peripheral interface if this unit performs management functions.

The line interface, which connects to the packet switch via communication lines, uses various communication lines (periodic, aperiodic,
HDLC/SDLC telex, etc.). The maximum number of lines that can be connected to a packet switch depends on the speed and transmission mode of these lines.
The number can be 11 to 44.

Operation of Physical Structures The physical structures described above are an important medium for system programming. This physical structure provides control, management, and packet switching functions for system programming. It provides the basic equipment for the transfer of information between those units.

Information transfer between the individual units of this system takes place as follows.

When a peripheral device or line interface 27-31 receives a control signal from its associated peripheral device or line indicating the start of the transmission of a block of information, it triggers an interrupt control peripheral device 18. 19°41.42. or 43 interrupts the processor 14, 15, 35, 36 or 37.

The processor prepares the direct memory access device of that interface for the direct transfer of information blocks coming from the interface in question into local memory, allocates local memory space 16.17°38.39 or 40, and if necessary l Chain blocks CCaLen
organize direct memory access for aLe).

Upon completion of each block transfer, the interface interrupts the processor again and informs it of the length of the block. Once a processor has placed an entire block in its local memory, it processes it and prepares to transfer the block to its corresponding destination unit. This unit is the same.

- unit or other processing unit: In the case of a transfer to another processing unit, before the transfer the processor checks whether the destination unit will accept the block.

! ! Once granted, this processor occupies the common bus 8 or 9 by bus access peripherals 25, 26, 44.
．． 45 or 46.

The source unit's bus access peripheral informs the common bus of the address of the destination unit's bus access peripheral and its own address. By verifying that address, the destination bus access peripheral confirms that there is space in the destination processor local memory to be allocated to the source processor. The destination bus access peripheral prepares its direct memory access circuitry and presents it to the source bus access peripheral. The source unit's bus line access peripheral then retrieves the block from memory via direct memory access and sends it to the destination unit's bus line access peripheral, which, after evaluating the periodic hole length code, retrieves the block from memory via direct memory access. Put the data into its local memory. Once this transfer is complete, the destination processor informs the source processor of its suitability.

If the transferred block must exit via a line or peripheral interface, the data transfer from local memory to that interface is similar to that described above for the reverse direction. Information transfer for control or management purposes between units is accomplished by reading or directly writing input/output registers located in independent bus access peripherals.

The control unit performs the functions of management, control and maintenance of the common bus.

Program structure of the system The program in the network center has the following divided structure.

- Basic operating system programs - Communication line control programs - Application programs - Development and control center programs - Usage and auxiliary programs - Testing and maintenance programs Basic operating system programs These programs operate the processor, memory and input/output parts of the system. let The main objectives of these programs are as follows.

Task Management This is the basis of the entire operating system. This activates, prepares, blocks or delays tasks, and the exchange of messages between tasks using the interrupt system is controlled according to the priority and re-entry of each task.

There is a program that avoids a certain degree of system failure by using the hole length portion and failure tolerance portion of the failure recovery system, and by notifying the outside of an unrecoverable failure.

The memory management system has a program specified in developing local memory control functions.

Bus Management This function organizes the use of the common and local buses of the system by means of packet switches and interrupts from the control unit.

Interrupt Control The program that performs this function generates interrupts based on their masking and priority, and channels them to the appropriate operators.

Time Management These programs perform all necessary periodization of processing subsystems and control the allocation of time to the entire system.

Load and damping management In this feature, load and program damping are
Consideration is given from local to peripheral storage and from other network centers.

System Generation This feature takes into account parameter generation and dynamic reconfiguration of the system.

There are programs that are specialized in the operation of each of the system's peripherals, such as the peripheral control line interface, peripheral memory, control and display device 22, generation register unit 12, and alarm unit 23.

Communication line control program These programs have the following functions:

a) Control the different line protocols supported by the system.

b) Transfer the information from the line to a separate application program that processes it.

C) Receive information from application programs to supply and transmit them on specified lines.

The basic tasks to be performed by these programs are as follows.

- High speed line operation with X25 processing - Medium speed line operation with ESC transparent and opaque processing, RETD dubrex processing and periodic or aperiodic 1200 DPS or higher terminal control processing.

Application programs These programs have their own entries, which are specified with different functional specifications of the particular data transmission network that characterizes them.

The basic functions of the application program are as follows.

a) Receive information from, provide to, and process information from line control programs.

b) Send the information generated by this process to the line control program.

Generally, there are two types of applications, one is line concentration,
The other is switching.

Some of the tasks that application programs perform are listed below.

- Data backing and unpacking - Information packet processing - Control packet generation and processing - Message handling routine development and management center programs These programs have the following functions.

a) Facilitate the development of programs with compilation, assembly, debugging and testing.

b) As a network management center added as a service center, it provides the necessary medium to utilize the center for its own development.

This group of programs allows the system to be used for administration.

Utilization and subsidy programs The functions of these programs are as follows.

a) Request information for measuring, quantifying, and outplant control of center performance during actual operation of the center.

b) Facilitate the operation of the center.

Here are some of the tasks these programs perform.

- Testing/modifying local or peripheral memory - Managing messages from lines, centers or networks - Tracking of packets by systems and networks - δ from networks, systems, subsystems, applications, tasks, centers and terminals! 1 Obtain constant and quantitative values.

Dynamic damping from local or peripheral memory, or local input/output peripherals or a remote control center. Some of these tasks are performed in-line during center operation, others out-of-line;
These are based on data collected during real-time operation of the center.

Test and maintenance program These programs have the following functions:

a) Provide media for preventive maintenance of the system.

b) Provide the most suitable means for diagnosis, removal and corrective operational testing even under the most unsuitable conditions when a fault occurs.

These types of programs are not built-in, but can be installed during operation considering that they should be broadly divided into two groups.

Programs provided by the machine These runs cannot be duplicated with the runs of other programs, depending on whether they are controlled without the control of the basic operating system.

SERVICE TEST PROGRAMS These programs run under control of the operating system, and they synchronize the functionality of the system with others that are active at the time.

Organization All of these programs are modular and structured data that can be executed on packet switches and control units.

A distinction must be made between:

a) A program that performs the appropriate functions for all of the processing subsystems.

b) A program that performs a specific function of some processing subsystem.

The program pattern for any subsystem can be obtained by selecting from the above-mentioned program group those programs that perform the functions given to it by this subsystem.

The inventor should include actual hardware examples to illustrate what one skilled in the art might use for each of the functional blocks shown in FIG.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing a detailed configuration of the embodiment. 1.2... Control unit, 3, 4.5... Packet switch, 6... Console, 7... Internal information transfer bus, 8.9... Common bus, 10-13... Impedance adapter, 14.15...Local bus bar, 1
6.17... Processor, 18.19... Local memory, 20.21... Interrupt control peripheral device, 22.
...Peripheral device memory, 23...Generation register unit, 24...Control display unit, 25...Alarm unit, 26...Take lock, 27.28°46.
48...Bus access peripheral device, 34-36...Local bus, 37-39...Processor, 40-42
. . . local memory, 43-45 . . . interrupt control peripheral device. Applicant's agent Mr. Sato

Claims (1)

[Claims] One to four common communication buses, each connected to these buses, each separately controlling automatic maintenance of the system, performing measurement and quantification of the system, and having a plurality of peripheral devices. two control units capable of controlling the network, a console connected to these control units for receiving and displaying information from these control units, and a console each connected to said busbar for controlling data from the subscribers; and controlling the reception and reception of data using the line interface and the transfer of data to other packet switches and at least one of said units to control its own internal maintenance, measurement and quantification. An electronic system for packet switching characterized by comprising a packet switch. 2. The electronic system for packet switching according to claim 1, wherein there are up to 34 packet switches. 3. Each of the control units has a local bus, a microprocessor connected to the local bus for executing a control program, and a local memory connected to the local bus for storing data and a control program; an interrupt control peripheral connected to the local bus and the microprocessor to control activation and deactivation of the microprocessor; and an interrupt control peripheral connected to the local bus to the common bus for communication between the units and the common bus. 2. The packet switching electronic system of claim 1, further comprising: two busbar access peripherals for providing the local busbar access, and one to forty-four peripheral interfaces connecting the local busbar to the console and other peripherals. 4. Each of the packet switches includes a local bus, a microprocessor connected to the local bus to execute a control program, and a local memory connected to the local bus to store data and control programs;
an interrupt control peripheral device connected between the local bus and the microprocessor to control activation and deactivation of the microprocessor; and an interrupt control peripheral device that connects the local bus to the common bus to communicate between the units and the common bus. and an interface for connecting 1 to 44 lines to the local bus for receiving and transmitting data to and from said subscribers. electronic systems for packet switching. 5. The local memory is modular and has a capacity of 1
It can be expanded up to ×10^6 (1 mega octate),
4. The electronic system for packet switching according to claim 3, wherein the electronic system is connected to a local bus of each of said packet switches. 6. The packet switching electronic system of claim 1, including four common communication buses connecting each of said two control units and each of said plurality of packet switches. 7. The console has a data clock that provides clock pulses, an alarm unit that activates and indicates a failure, a peripheral memory that locally stores data within the console, and an internal memory between the console and the control unit. 3. The electronic system for packet switching according to claim 2, further comprising an event register unit for registering the occurrence of at least one communication of said console; and a display device for displaying information and data to an operator of said console.