JP3823284B2 - Function distribution and load distribution processing multiprocessor system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multiprocessor system that performs function distribution and load distribution processing, and more particularly to a multiprocessor system that performs function distribution processing and load distribution processing in parallel on signals input via an I / O bus. About.
[0002]
In recent years, development of a CDMA (Code Division Multiple Access) communication system has rapidly progressed, and commercial services of a narrowband CDMA communication system have been implemented. Further, in order to exchange not only voice but also large data such as images, development of a W-CDMA (Wide band-CDMA) system having a wider band is urgently required.
[0003]
The present invention relates to a multiprocessor system that is suitably applied to a system that must efficiently process a large amount of data at high speed and stably, such as a processor system in a CDMA communication system or the like.
[0004]
FIG. 10 shows a basic configuration of the W-CDMA communication system. The mobile device 100 transmits data to the plurality of base stations 101_1 to 101_3. Each base station receives this data, converts it into an ATM (Asynchronous Transfer Mode) cell, and transmits it to the wireless network control apparatus 102 by wire.
[0005]
The wireless network control apparatus 102 processes these data in cooperation with the multimedia processing apparatus 103, then converts the data again into ATM cells and transmits them to the switch 104 by wire. The wireless network control device 102 and the multimedia processing device 103 incorporate a protocol termination device and a control device that controls the device.
[0006]
In such a processing system, particularly when handling enormous amounts of data, the wireless network control device 102, the protocol termination device of the multimedia processing device 103, its control device, and the like are required to have a large capacity. Therefore, it is necessary to increase the processing speed and efficiency by adopting a multiprocessor configuration for these devices.
[0007]
[Prior art]
As a conventional multiprocessor system that performs distributed processing of signals, a load distribution processing system that performs signal distribution based on the load factor of each processor (for example, Japanese Patent Application No. 11-141306 “Multi-CPU system and its data communication control method”) And a function distribution processing system that includes a plurality of processors having different functions and distributes signals in accordance with the functions of the processors.
[0008]
In the load distribution processing system, when the processing amount of the processor becomes unbalanced due to congestion or the like, there arises a problem that the processing order of signals from the peripheral function unit is reversed. On the other hand, if a signal is concentrated on a specific processor, the function-distributed processing system cannot process that processor. Therefore, it is necessary to take additional measures such as adding a processor card or transferring the processing to another processor through inter-processor communication. Thus, there arises a problem that it is necessary to deal with processing overload.
[0009]
[Problems to be solved by the invention]
In order to efficiently process a large amount of signals, it is desirable to perform load distribution processing and function distribution processing with a multiprocessor configuration. However, as described above, regardless of which distributed processing is performed, signal processing during congestion, etc. Problems such as sequence reversal or process overloading occur.
[0010]
The present invention provides a function distribution signal (a signal that requires a guarantee of the signal processing order) to be processed for each function of the processor and a load distribution signal (a signal processing order is not required to be guaranteed) to be processed by any of a plurality of processors. It is an object of the present invention to provide a multiprocessor system in which a function distribution process and a load distribution process are separated and processed in parallel according to the signal type.
[0011]
In addition, when a processor failure occurs or when a processor module is blocked, or when hot plugging is performed, the processing is switched to the spare processor without any signal loss, and the input / output (I / O) unit is the processor. An object of the present invention is to provide a multiprocessor system capable of stable switching without dealing with any switching.
[0012]
[Means for Solving the Problems]
The function distribution and load distribution processing multiprocessor system of the present invention includes a main control unit including a plurality of processor modules, a global memory and a bus control unit, and a peripheral including a plurality of input / output (I / O) units for signal transmission / reception. The bus control unit in the main control unit uses a state monitoring bus to collect the status of each processor module, collect processor congestion information, and processor failure (including when shut down and hot plugging) Switching control to the spare processor module, and each input / output (I / O) unit in the peripheral function unit has a function distribution unit, and a function distribution signal and load distribution to the main control unit for each signal type Signals are transmitted in a distributed manner.
[0013]
(1) In a multiprocessor system including a main control unit including a plurality of processor modules and a peripheral function unit including an input / output unit connected to the plurality of processor modules via an input / output bus, The input / output unit distinguishes between a function distribution signal transmitted to a processor module having a specific function in the main control unit and a load distribution signal transmitted without specifying a processor module in the main control unit. And a function identification information adding means for adding the identification information to the transmitted signal and transmitting it to the input / output bus, wherein the main control unit is based on a load factor of each processor module in the main control unit. And a means for sending module identification information of the processor module to each processor module, The processor module is configured to identify a signal to be received based on the function identification information with respect to a signal sent from the input / output unit in the peripheral function unit to the input / output bus, and based on the module identification information. Module identifying means for identifying a signal to be received.
[0014]
(2) The main control unit stores the function identification information stored in the function identification unit of the processor module in which the fault has occurred in the function identification unit of the spare processor module, and the load of the faulty processor module The processor module switching control means for setting the rate to the load factor of the spare processor module to release the spare state of the spare processor module and setting the faulty processor module to the spare state.
[0015]
(3) The processor module switching control means stores the function identification information stored in the function identification means of the processor module in which the failure has occurred in the function identification means of the spare processor module, and then sets the spare status of the spare processor module. The module identification information of the failed processor module is stored in the module identification means of the spare processor module until the signal is released, and during that time, the signal to be received by the failed processor module is received by the spare processor module. is there.
[0016]
(4) The processor module switching control means performs control to switch the processor module to the spare processor module as the failed processor module when the processor module in the main control unit is closed or hot-plugged.
[0017]
(5) The main control unit includes a state monitoring unit that monitors a state of each processor module and a bus control unit that includes the processor module switching control unit, and the state monitoring unit detects a failure of the processor module. Sometimes, the processor module switching control means controls to switch between the failed processor module and the spare processor module.
[0018]
(6) Each processor module in the main control unit includes state monitoring means for monitoring the state of the own processor module, inter-processor module communication means, and the processor module switching control means. At the time of occurrence detection, the faulty processor module transmits fault information to the processor module switching control means in the spare processor module by means of communication means between processor modules, and the switching control means in the spare processor module includes the faulty processor module and the spare processor. Control to switch between modules.
[0019]
(7) The bus control unit includes a distribution table storing a load factor of each processor module in the main control unit. The distribution table includes module identification information of the processor module and function identification information of the processor module. And the load factor of the processor module are stored in association with each other.
[0020]
(8) The input / output unit in the peripheral function unit includes a function distribution table, and the function distribution table stores function identification information of a destination processor module corresponding to a signal type transmitted to the input / output bus, The function identification information adding means has a configuration in which function identification information is added to a transmission signal and transmitted based on the function distribution table.
[0021]
(9) The input / output unit in the peripheral function unit includes a function distribution table. The function distribution table stores signal identification information corresponding to a signal type transmitted to the input / output bus, and adds the function identification information. The means includes means for adding the signal identification information to the transmission signal as the function identification information based on the function distribution table and transmitting the signal. The processor modules send the input / output unit from the input / output unit in the peripheral function unit onto the input / output bus. The function identification means for identifying the signal to be received by converting the signal identification information of the signal to be received into the logic identification information of the own processor module.
[0022]
(10) Physical module identification information is used as the module identification information of each processor module. (11) Logical identification information is used as module identification information of each processor module.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a diagram showing the system configuration of the first embodiment of the present invention. As shown in the figure, the multiprocessor system according to the present invention includes a main control unit 11 including a plurality of processor modules, a peripheral function unit 19 including an input / output (I / O) unit, and an I connected between them. / O bus 116.
[0024]
The main control unit 11 includes a bus control unit 12, processor modules 13_0 to 13_n, and a global memory 18. The bus control unit 12 and the processor modules 13_0 to 13_n are connected by a state monitoring bus 114, and the processor modules 13_0 to 13_n are globally connected. The memory 18 is connected to the global bus 115.
[0025]
The bus control unit 12 includes a switching control unit 12_1 and a distribution table 12_2. When a failure occurs in a certain processor module, the switching control unit 12_1 performs control to switch the failed processor module to a spare processor module, and the distribution table 12_2 stores identification information and state information for optimally performing function distribution processing or load distribution processing.
[0026]
FIG. 2 shows a configuration example of the switching control unit 12_1. The switching control unit 12_1 includes a distribution table change control unit 20, a register (REG) change control unit 21, a spare module ID storage register 22, a fault module function ID storage register 23, a fault module ID storage register 24, and alarm (ALM) information storage. A register 25 is provided.
[0027]
In each of the registers 23 to 25, information associated with the failure is written from the processor module in which the failure has occurred via the state monitoring bus. That is, an alarm (ALM) signal indicating the occurrence of a failure transmitted from the failed processor module is stored in the alarm (ALM) information storage register 25, and the module identification information also transmitted from the failed processor module is stored in the failed module ID storage register. The function identification information of the processor module is stored in the failure module function ID storage register 23. The spare module ID storage register 22 stores the module identification information of the processor module in the spare state.
[0028]
The register (REG) change control unit 21 reads the information written in the registers 22 to 25 and notifies the register in the spare processor module of switching. The distributed table change control unit 20 reads information in the failure module function ID storage register 23 and the failure module ID storage register 24 and updates the distribution table.
[0029]
FIG. 3 shows a configuration example of the distribution table. The distribution table stores the correspondence between the module ID, function ID, and load factor of the processor module. Here, the module ID is physical identification information (physical ID) such as mounting position and dip switch setting information, and the function ID is identification information (logical ID) corresponding to the function type.
[0030]
The load factor of each processor module is collected by the bus control unit 12 measuring the task running time for each processor module via the state monitoring bus (Japanese Patent Application No. 11-141306, “Multi-CPU System and Data”). Refer to “Communication control method”. Further, on the distribution table, the function ID and the load factor of the processor module in the spare state are locked to “No Func” and “No Acceptance”, respectively.
[0031]
As shown in FIG. 1, each processor module includes a central processing unit (CPU) 14_0 to 14_n and first and second module ID storage registers (REG1, REG2) 15_0 to 15_n, 16_0 storing their own module IDs. 16_n and a function ID storage register (FREG) 17_0 to 17_n that stores the function ID of the own module.
[0032]
As shown in FIG. 1, the peripheral function unit 19 includes a plurality of input / output (I / O) units 110_0 to 110_n, and each of the input / output (I / O) units 110_0 to 110_n includes a central processing unit (CPU). ) 111_0 to 111_n and function distribution units 112_0 to 112_n.
[0033]
When the multiprocessor system of the present invention is used in a W-CDMA radio network controller, each input / output (I / O) unit 110_0 to 110_n includes a mobile device 100 and a base station 101_1 as shown in FIG. ˜101_3, the multimedia processing apparatus 103, the exchange 104, and the like, and exchanges signals with various functional blocks.
[0034]
At this time, each input / output (I / O) unit 110_0 to 110_n has a unique channel set between each function block, and performs signal transmission / reception for function distribution or load distribution for each channel.
[0035]
For example, control information (partial) between the mobile device 100 and control information (monitoring information, etc.) in the wireless network control device 102 are function distributed signals, while the base stations 101_1 to 101_3 and the multimedia processing device. The control information between the switch 103 and the exchange 104 has a correspondence relationship between each channel and the function distribution / load distribution signal, such as a load distribution signal. That is, the CPUs 111_0 to 111_n in the input / output (I / O) unit determine the function distribution and the load distribution by identifying the types of these channels.
[0036]
The CPUs 111_0 to 111_n in the I / O unit have a function of distributing an external signal into a function distribution signal and a load distribution signal according to the signal type. The function distribution signal is transmitted to the I / O bus 116 via the function distribution units 112_0 to 112_n, and the load distribution signal is directly transmitted to the I / O bus 116.
[0037]
FIG. 4 shows a configuration example of the function distribution unit in the input / output (I / O) unit. The function distribution unit includes a transmission destination function ID addition unit 40 and a function distribution table 41. The function distribution table 41 stores a correspondence relationship between a signal type and its function ID. The transmission destination function ID adding unit 40 identifies the types of function distribution signals from the CPUs 111_0 to 111_n in the I / O unit, and adds a function ID corresponding to the signal type to the signal based on the function distribution table 41. , And sent to the I / O bus 116.
[0038]
FIG. 5 is a diagram showing a flow of distributed processing of the present invention. First, in step S5_1, the CPUs 111_0 to 111_n in the input / output (I / O) unit sort the signals into function distribution signals and load distribution signals. Thereafter, the function distribution signal is transmitted to the function distribution unit in step S5_2, and the function distribution unit assigns the destination function ID corresponding to the signal type to the signal data (S5_3), and then sends it to the I / O bus ( S5_4).
[0039]
The processor module in the main control unit compares the function ID in the signal data sent on the I / O bus with the function ID stored in the function ID storage register (FREG) in its own processor module. Then, signal data is received (S5_5), and processing is performed (S5_6).
[0040]
On the other hand, after the load distribution signal is sent directly on the I / O bus in step S5_7, the light load processor module loads the load distribution signal according to the load factor of each processor module stored in the distribution table in the bus control unit of the main control unit. Received and processed (S5_8, 9).
[0041]
The means for fetching the load distribution signal with the processor module with a light load is as follows. The bus control unit 12 refers to the load factor in the distribution table 12_2, selects one of the processor modules with a light load factor, and sets its module ID to I / O. Each of the processor modules 13_0 to 13_n sends the module ID stored in its module ID storage register (REG1 or REG2) and the module ID sent to the I / O bus 116. Only when they match, the load distribution signal on the I / O bus can be taken in.
[0042]
As another method, the bus control unit 12 refers to the load factor in the distribution table 12_2, selects one of the processor modules having a low load factor, and selects the I / O bus 116 or the state monitoring bus 114 as the processor module. In this case, it is possible to instruct loading of the load distribution signal on the I / O bus.
[0043]
As another method, when the bus control unit 12 receives a load distribution signal from the CPUs 111_0 to 111_n in the input / output (I / O) unit, the load factor in the distribution table 12_2 is referred to and the processor module with a light load factor is referred to. One is selected and the module ID is transmitted to the input / output (I / O) unit of the load distribution signal source, and the input / output (I / O) unit of the load distribution signal source is The processor module 13_0 to 13_n can be configured to take in the load distribution signal to which the own module ID is added by adding the transmission destination module ID to the load distribution signal and retransmitting it (special feature). No. 11-141306 “Multi-CPU system and data communication control method thereof”).
[0044]
FIG. 6 shows a flow of switching processing when a failure occurs in the processor module. When the processor module is closed or when the processor module is hot-plugged, it can be switched to the spare processor module in the same manner as when a failure occurs.
[0045]
When a failure occurs in the processor modules 13_0 to 13_n in the main control unit (S6_1), the processor module switches the alarm (ALM) signal, its own module ID, and module function ID information via the state monitoring bus 114. Write to the alarm (ALM) information storage register 25, the fault module ID storage register 24, and the fault module function ID storage register 23 in 12_1 (S6_2).
[0046]
The register (REG) change control unit 21 reads the information written in step S6_2 and the information stored in advance in the spare module ID storage register 22 (S6_3) and simultaneously stores the information in the fault module ID storage register 24. The written fault module ID is written into the spare module ID storage register 22 (S6_4).
[0047]
Thereafter, the register (REG) change control unit 21 writes the function ID of the failed processor module to the function ID storage register (FREG) in the spare processor module via the state monitoring bus (S6_5), and then in the spare processor module. The module ID of the failed processor module is written only in the second module ID storage register (REG2) (S6_6).
[0048]
By rewriting the function ID storage register (FREG) of the spare processor module in step S6_5, the function distribution signal transmission destinations from the input / output (I / O) units 110_0 to 110_n are switched. / O) The units 110_0 to 110_n do not need to cope with the switching of the processor module.
[0049]
In addition, the fault module ID is written in the second module ID storage register (REG2) in step S6_6 because the load distribution signal that the fault module should originally process is transiently processed by the spare module, and the signal loss due to the fault is detected. This is to prevent it.
[0050]
This is because switching to the spare module requires rewriting processing of the function ID storage register (FREG) of the spare module and rewriting processing of the distributed table, and prevents signal processing from being lost due to a time lag between them. Therefore, in addition to the first module ID storage register (REG1) that stores the original self module ID in an excessive state after the rewrite processing of the function ID storage register (FREG) of the spare module and before the rewrite processing of the distribution table 2 includes a second module ID storage register (REG2) for storing the module ID of the faulty module, and the load distribution signal having the module ID stored in any of the module ID storage registers (REG1, REG2) as a transmission destination By taking in and processing, the loss of signal processing is prevented.
[0051]
Thereafter, the distributed table change control unit 20 in the switching control unit reads the module ID of the fault module and the function ID written in the fault module ID storage register 24 and the fault module function ID storage register 23 in step S6_2, The distribution table is updated based on the information (S6_7).
[0052]
After the distribution table is updated, the fault module is newly set as a spare module, so the load distribution signal destination will not be the fault module. The module ID storage register (REG2) 2 of the module ID (REG2) is changed again from the module ID of the failed module written in step S6_6 by the register (REG) change control unit 21 (original module ID of the spare processor module). ) Or an invalid module ID (S6_8).
[0053]
As described above, in order to assign the destination processor module according to the signal type from the input / output (I / O) units 110_0 to 110_n, the contents of the function ID storage register (FREG) of the spare processor module are changed, the bus control unit The switching of the processor modules is completed by changing the distribution table and changing the excessive contents of the second module ID storage register (REG2) of the spare processor module.
[0054]
FIG. 7 is a diagram showing a system configuration of the second exemplary embodiment of the present invention. The second embodiment is a system configuration example in which switching control is performed by performing communication between processor modules. In this embodiment, similarly to the system configuration shown in FIG. 1, a main control unit 71 including a plurality of processor modules, a peripheral function capital 710 including an input / output (I / O) unit, and a connection between them are connected. And an I / O bus 717.
[0055]
The main control unit 71 includes a bus control unit 72, processor modules 73_0 to 73_n, and a global memory 79, which are connected by a state monitoring bus 714 and a global bus 715, respectively, similarly to the configuration shown in FIG.
[0056]
Further, the processor modules 73_0 to 73_n are connected to each other by an inter-module communication bus 716. The bus control unit 72 includes a distribution table 72_1 that stores identification information and state information for optimally performing distributed processing.
[0057]
The processor modules 73_0 to 73_n include a central processing unit (CPU) 74_0 to 74_n, a switching control unit 78_0 to 78_n, and first and second module ID storage registers (REG1, REG2) 75_0 to 75_n storing their own module IDs. , 76_0 to 76_n and a function ID storage register (FREG) 77_10 to 77_n storing the function ID of the own module.
[0058]
The peripheral function unit 710 includes a plurality of input / output (I / O) units 711_0 to 711_n, and the input / output (I / O) units 711_0 to 711_n include central processing units (CPUs) 712_0 to 712_n and functions. Dispersion units 713_0 to 713-n are provided.
[0059]
In the second embodiment shown in FIG. 7, the switching controller 12_1 provided in the bus controller 12 in the first embodiment shown in FIG. 1 is provided in each of the processor modules 73_0 to 73_n. .
[0060]
FIG. 8 shows a flow of processor module switching processing in the system configuration of the second embodiment. When a failure occurs in any of the processor modules 73_0 to 73n in the main control unit 71 (S8_1), the switching control unit (for example, 78_0) in the failure module uses the state monitoring bus 714 to distribute in the bus control unit 72. The table 72_1 is accessed (S8_2), and the function ID corresponding to the faulty module in the distributed table 72_1 is locked to “Reserve (NoFunc)” and the load factor is locked to “rejection” (S8_3).
[0061]
Next, the switching control unit (for example, 78_0) in the faulty module sends the fault module ID and function ID on the inter-module communication bus (S8_4). The module ID and function ID are received only by the switching control unit (for example, 78_n) in the standby module, and the switching control unit (for example, 78_n) receives the second module ID storage register (REG2) in its own module. The failure module ID is written into the function ID storage register (FREG) (S8_5). As a result, thereafter, a signal for which the faulty module transmitted by the input / output (I / O) units 711_0 to 711_n is transmitted is received by the spare module.
[0062]
Thereafter, the switching control unit (for example, 78_n) in the spare module accesses the distribution table 72_1 in the bus control unit 72 via the state monitoring bus 714, and performs “acceptance refusal” of the load factor corresponding to the spare module ID. After that, the load factor of the spare module is made readable (S8_6), and the function ID (fault module function ID) written in the function ID storage register (FREG) of the spare module in step S8_5 Is written in the function ID area corresponding to the spare module ID (S8_7).
[0063]
Note that the above-described rewriting process of the distribution table 72_1 may be performed by a process of exchanging the module ID of the failed module and the module ID of the spare module stored in the module ID column.
[0064]
After the rewriting of the distribution table 72_1 is completed, the switching control unit (for example, 78_n) in the spare module, the information of the first module ID storage register (REG1) in the own module (original ID of the spare module itself) or invalid The module ID is overwritten in the second module ID storage register (REG2) (the module ID of the failed module is written) (S8_8). With the above flow, switching from the failed module to the spare module is completed.
[0065]
In the above-described embodiment, the function distribution signal transmitted from the input / output (I / O) unit is identified by the function ID added according to the signal type, and the load distribution signal is specified by the bus control unit. Although the configuration identified by the ID is shown, the present invention is not limited to this. For example, the signal identification ID indicating the signal type or the physical ID of the transmission destination module is added from the input / output (I / O) unit, and then transmitted. Each processor module may be configured to identify a signal captured by the own module based on the ID information. In addition to the physical identification ID (physical ID), a logical ID may be used as the module ID for designating the transmission destination of the load distribution signal.
[0066]
FIG. 9 shows an example of a mapping table of signal types and processor module identification IDs. (A) in the figure shows an example of a signal distribution table in each input / output (I / O) unit, (B) in the figure shows an example of a signal ID mapping table in each processor module, and (C) in the figure shows An example of a distribution table in the bus control unit is shown.
[0067]
If the input / output (I / O) unit adds a signal identification ID corresponding to the signal type and sends the signal to the I / O bus according to the signal distribution table shown in FIG. The received signal identification ID is converted into a logical ID of the processor module using the signal ID mapping table shown in FIG. 9B, and when it matches the module logical ID of the own module, The signal can be acquired in the same manner as the above-described acquisition of the function distribution signal.
[0068]
Further, as shown in FIG. 9C, the bus control unit stores physical module identification information (physical ID), corresponding logical identification information (logical ID), and its load factor in the distribution table, By selecting a processor module with a low load factor and specifying the logical identification information (logical ID) of the selected processor module as the transmission destination, the load is distributed to the module with a low load factor in the same manner as the load distribution signal fetching described above. A signal can be captured.
[0069]
The signal to each processor module is sent to the I / O bus with the module ID (physical ID) of the destination given by the function distribution table in the function distribution unit of the input / output (I / O) unit. The processor module is configured to read the transmission destination physical ID in the signal from the input / output (I / O) unit, convert the physical ID into a logical ID using a mapping table, and take in the signal if it matches the logical ID of the own module. You can also
[0070]
Furthermore, the transmission destination of the function distribution signal is recognized by the bus control unit, the bus control unit specifies the physical ID or logical ID of the transmission destination processor module, and the transmission destination processor module is specified to take in the signal, etc. It goes without saying that various modifications are possible without departing from the spirit of the present invention.
[0071]
【The invention's effect】
As described above, according to the present invention, in the input / output (I / O) unit, the signal sent to the main control unit is classified into the function distribution signal and the load distribution signal, and the identification information is added to the signal. The main control unit performs function distribution processing or load distribution processing on the received signal based on the added identification information, thereby separating function distribution processing and load distribution processing according to the type of signal. Can be done in parallel.
[0072]
This prevents the load from concentrating on a specific processor and allows signal processing to be performed with an optimal processor module corresponding to the signal processing order and the importance of signals, resulting in signal order reversal. Is eliminated, and an efficient multiprocessor processing system can be constructed.
[0073]
Further, at least one of the plurality of processor modules is a spare processor module, and the faulty processor module and the spare processor module are rewritten by rewriting identification information storage means for identifying a signal to be captured between the faulty processor module and the spare processor module. Therefore, it is possible to quickly switch to the spare processor module and to prevent signal loss.
[0074]
Therefore, a highly reliable and stable multiprocessor system can be constructed, and the input / output (I / O) unit does not have to cope with the switching of the processor module, and the configuration is simplified. be able to.
[Brief description of the drawings]
FIG. 1 is a diagram showing a system configuration of a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a configuration of a switching control unit according to the first embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration example of a distribution table according to the present invention.
FIG. 4 is a diagram showing a configuration of a function distribution unit in the input / output unit of the present invention.
FIG. 5 is a flowchart of signal distribution processing according to the present invention.
FIG. 6 is a flowchart of processor module switching processing according to the first embodiment of this invention;
FIG. 7 is a diagram showing a system configuration of a second exemplary embodiment of the present invention.
FIG. 8 is a flowchart of processor module switching processing according to the second embodiment of this invention;
FIG. 9 is a diagram showing an example of a mapping table of signal types and processor module identification IDs according to the present invention.
FIG. 10 is a diagram showing a basic configuration of a W-CDMA communication system.
[Explanation of symbols]
11 Main control unit
12 Bus control unit
12_1 switching control unit
12_2 Distributed table
13_0-13_n processor module
14_0-14_n Central processing unit (CPU)
15_0 to 15_n first module ID storage register (REG1)
16_0 to 16_n second module ID storage register (REG2)
17_0 to 17_n Function ID storage register (FREG)
18 Global memory
19 Peripheral functions
110_0 to 110_n input / output (I / O) section
111_0 to 111_n Central processing unit (CPU)
112_0 to 112_n function distribution unit
114 Condition monitoring bus
115 Global Bus
116 I / O bus

Claims (11)

In a multiprocessor system including a main control unit including a plurality of processor modules and a peripheral function unit including an input / output unit connected to the plurality of processor modules via an input / output bus,
The input / output unit in the peripheral function unit distinguishes between a function distribution signal and a load distribution signal, and function identification information that adds function identification information that identifies a function to the function distribution signal and transmits the function identification information to the input / output bus With additional means,
The main control unit identifies one processor module based on a load factor of each processor module stored in a distribution table in the main control unit when a load distribution signal is transmitted on the input / output bus , and Means for sending module identification information of the processor module to each processor module;
Each processor module in the main control unit identifies a signal to be received based on the function identification information added to the signal sent from the input / output unit in the peripheral function unit to the input / output bus. A function distribution and load distribution processing multiprocessor system comprising function identification means and module identification means for identifying a signal to be received based on the module identification information. The main control unit stores the function identification information stored in the function identification unit of the processor module in which the failure has occurred, in the function identification unit of the spare processor module, and the failure processor module stored in the distribution table . 2. A processor module switching control means for setting a load factor to a load factor of a spare processor module to cancel a spare state of the spare processor module and setting a failed processor module to a spare state. The function distribution and load distribution processing multiprocessor system described in 1.   The processor module switching control unit stores the function identification information stored in the function identification unit of the processor module in which the failure has occurred in the function identification unit of the spare processor module and then releases the spare state of the spare processor module. The module identification information of the failed processor module is stored in the module identifying means of the spare processor module, and a signal to be received by the failed processor module is received by the spare processor module during that time. 3. A function distribution and load distribution processing multiprocessor system according to 2.   The processor module switching control means performs control to switch the processor module to a spare processor module as the failed processor module when the processor module in the main control unit is closed or hot-plugged. 4. The function distribution and load distribution processing multiprocessor system according to 3.   The main control unit includes a state monitoring unit that monitors a state of each processor module and a bus control unit that includes the processor module switching control unit, and the processor detects a failure of the processor module by the state monitoring unit. 4. The function distribution and load distribution processing multiprocessor system according to claim 2, wherein control for switching between a faulty processor module and a spare processor module is performed by module switching control means.   Each processor module in the main control unit includes state monitoring means for monitoring the state of the own processor module, inter-processor module communication means, and the processor module switching control means. The faulty processor module transmits fault information to the processor module switching control means in the spare processor module by means of inter-processor module communication means, and the switching control means in the spare processor module controls switching between the faulty processor module and the spare processor module. 4. The function distribution and load distribution processing multiprocessor system according to claim 2 or 3, wherein: The main control unit includes a bus control unit , and the bus control unit includes a distribution table storing a load factor of each processor module in the main control unit, and the distribution table includes module identification information of the processor module, the 2. The function distribution and load distribution processing multiprocessor system according to claim 1, wherein the function identification information of the processor module and the load factor of the processor module are stored in association with each other.   The input / output unit in the peripheral function unit includes a function distribution table, which stores function identification information of a destination processor module corresponding to a signal type transmitted to the input / output bus, and adds the function identification information. 2. The function distribution and load distribution processing multiprocessor system according to claim 1, wherein the means has a configuration in which function identification information is added to a transmission signal and transmitted based on the function distribution table.   The input / output unit in the peripheral function unit includes a function distribution table, the function distribution table stores signal identification information corresponding to a signal type to be transmitted to the input / output bus, and the function identification information adding unit includes the function distribution table. A means for adding signal identification information to a transmission signal as function identification information based on a distribution table and transmitting the signal is provided, and each processor module is configured to output a signal transmitted from an input / output unit in a peripheral function unit onto an input / output bus. The function distribution and load according to claim 1, further comprising function identification means for converting the signal identification information of the signal to be received into the logic identification information of the processor module to identify the signal to be received. Distributed processing multiprocessor system.   2. The function distribution and load distribution processing multiprocessor system according to claim 1, wherein physical module identification information is used as the module identification information of each processor module.   2. The function distribution and load distribution processing multiprocessor system according to claim 1, wherein logic identification information is used as module identification information of each processor module.

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