JP2001166960A - Multi-processor system having individual area in shared memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the deterioration of processing capabilities, and to efficiently and economically structure a highly reliable and stable system in a multi- processor system in which the individual memory of each processor module is assigned as an individual area in a shared memory. SOLUTION: This multi-processor system is provided with plural processor modules 10-0-10-n including at least one primary processor module 10-n and a shared memory 15 to be commonly used by each processor module. The shared memory 15 is provided with individual areas 17-0-17-n-1 assigned to each processor module, and a shared memory mapping table 16-1 and an address converting part 16-2 for converting memory access from each processor module into access to each individual area in the shared memory 15. Also, this multi- processor system is provided with a switching control part 18-1 for switching the assignment of the individual areas of the processor module in which any failure is generated and the primary processor module by monitoring each processor module.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a multiprocessor system in which individual memories for each processor module in a multiprocessor system are allocated as individual areas in a shared memory commonly used by the processor modules.

In recent years, CDMA (Code Division Multiple)
Access) The communication system has been rapidly developed, and commercial services of a narrow band CDMA communication system have been implemented. In addition, in order to exchange not only audio but also large data such as images, a system having a wider band (W-C
The development of DMA (Wide band-CDMA) is urgent.

[0003] The present invention relates to a multiprocessor system suitably applied to a system in which a huge amount of data must be efficiently processed at high speed and stably, such as a processor system in a CDMA communication system or the like.

[0004]

2. Description of the Related Art FIG. 8 shows a basic configuration of a W-CDMA communication system. The mobile device 80 includes a plurality of base stations 81_1 to 81_1.
_3 is transmitted. Each base station 81_1 to 8
After receiving this data, 1_3 receives an ATM (Asynchro
nous Transfer Mode) and converts it to a cell and sends it to the wireless network controller 82 by wire.

[0005] The wireless network control device 82 processes these data in cooperation with the multimedia processing device 83, converts the data into ATM cells again, and transmits the ATM cells to the exchange 84 by wire. The wireless network control device 82 and the multimedia processing device 83 have a built-in protocol termination device and a control device for controlling the device.

In such a processing system, especially when a huge amount of data is handled, the radio network controller 82
The large-capacity processing capability is required for the protocol termination device of the multimedia processing device 83 and its control device. Therefore, it is necessary to increase the processing speed and efficiency by adopting a multiprocessor configuration in these devices.

As a conventional multiprocessor system,
A shared memory type load distribution multiprocessor system as shown in FIG. 9 and an individual memory type function distribution multiprocessor system as shown in FIG. 10 are known (see, for example, JP-A-1-318138). )

As shown in FIG. 9, a shared memory type load distribution multiprocessor system includes a plurality of multiprocessor modules 90_0 to 90_n (each a CPU 91_n).
0 to 91 — n) for the shared memory 92
And each of the multiprocessor modules 90_0 to 90_90
_N and a shared memory 92 are connected by a global bus 93.

As shown in FIG. 10, an individual memory type function distributed multiprocessor system includes a plurality of multiprocessor modules 100_0 to 100_n (each having a CPU
101_0 to 101_n), memories 102_0 to 102_n are individually provided, and the multiprocessor modules 100_0 to 100_n are connected by the interprocessor communication path 103.

[0010]

When economically constructing a multiprocessor system, it is important to efficiently combine hardware and applications designed based on different architectures.

However, for example, when an application designed for an individual memory-type function-distributed multiprocessor system is operated on hardware employing a shared memory-type load-distribution multiprocessor configuration, each processor simultaneously accesses a shared resource. Exclusive control for eliminating access is required. As a result, the processing is complicated and reliability is reduced. In addition, when a failure occurs in a processor module, the processing cannot be taken over by a spare processor module. Occurs.

According to the present invention, as described above, when an application for an individual memory type function distributed multiprocessor system is combined with hardware of a shared memory type load distribution multiprocessor configuration to economically construct a system. In this way, it is possible to prevent a decrease in reliability due to exclusive control of shared resources, and to quickly transfer information being processed by the processor to another processor when a processor failure occurs. It is an object of the present invention to provide a multiprocessor system having an individual area in a shared memory that can maintain high reliability.

[0013]

A multiprocessor system according to the present invention includes (1) a plurality of processor modules including at least one spare processor module, and a shared memory commonly used by the plurality of processor modules. In the multiprocessor system, the shared memory is occupied by each processor module as an individual memory, has an individual area allocated to each processor module, and allows each processor module to access the individual memory in the shared memory. Individual area access means for converting to access to each individual area, and switching control means for switching the allocation of individual areas in the shared memory of the failed processor module and the spare processor module when a failure occurs in the processor module, Obstacle And it has a configuration in which discrete areas of the raw processor module pre-processor module to continue processing takes over.

(2) The multiprocessor system includes a main control unit for monitoring a failure of each processor module via a state monitoring bus, the main control unit including the switching control unit, and the switching control unit. To switch the allocation of the individual areas in the shared memory, and to take over the processing of the faulty processor module to the spare processor module.

(3) The multiprocessor system has a configuration in which the processor modules are connected to each other by an inter-processor communication bus, and the switching control means is provided in each processor module. Fault information is communicated between the processor module and the spare processor module via the inter-processor communication bus, and the switching control means in the spare processor module switches the allocation of the individual area in the shared memory. It has a configuration that takes over the processing of the generating processor module.

(4) The individual area access means includes a shared memory mapping table storing the allocated capacity corresponding to each processor module, and using the shared memory mapping table to access the individual memory for each processor module. An address conversion unit for converting an address into an address of an individual area in the shared memory.

(5) In the multiprocessor system, when the processor module is closed or hot-plugged, the switching control unit uses the blocked or hot-plugged processor module as the faulty processor module. The configuration is such that the allocation of the individual area in the memory and the individual area of the spare processor module is switched, and the individual area of the processor module is taken over by the spare processor module to continue processing.

(6) Each individual area in the shared memory has a configuration in which one or more memory blocks of a fixed capacity are allocated, and the capacity of the individual area is determined by the number of memory blocks allocated to the individual area. The configuration changes according to the change of

(7) In the multiprocessor system, the individual access means is arranged in a common area in a shared memory accessible to all of the processor modules.

(8) The shared memory mapping table includes a storage unit for storing information indicating a capacity of a unit memory block constituting an individual area in the shared memory;
The storage unit includes a storage unit that stores a correspondence relationship between the identification information of the processor module and the number of memory blocks allocated to the individual area of the processor module, and a storage unit that stores the identification information of the spare processor module.

(9) The shared memory mapping table in the individual area access means includes a storage unit for storing information on a capacity of a unit memory block constituting an individual area in the shared memory, and identification information of each processor module. A storage unit for storing the number of memory blocks in the individual area allocated to each processor module in association with the number of memory blocks in the individual area corresponding to the identification information of the spare processor module. Is stored.

(10) At least one of the processor modules has at least a memory address space covering the entire address space of the shared memory, and the one processor module reallocates an area in the shared memory. , And a configuration in which the settings of the shared memory including the above can be executed collectively.

A shared memory that stores at least a plurality of processor modules having at least duplicated functions and processing results of the plurality of processor modules in a storage area allocated to each of the plurality of processor modules;
A multi-processor system comprising: a spare processor module for spare of the processor module; switching control means for assigning a storage area assigned to the failed processor module as a storage area of the spare processor module; Initialization means for initializing a storage area allocated to the failed processor module when a failure occurs in the spare processor module.

According to the present invention, in the hardware configuration of the shared memory type load distribution multiprocessor, when an application for the individual memory type function distributed multiprocessor is used, an individual area is secured on the shared memory for each processor. This eliminates the need for exclusive control, prevents the reliability from being reduced due to the complicated processing involved in exclusive control, and allows the spare processor module to take over the function when a failure occurs in the processor module.
High reliability can be ensured with a simple configuration.

[0025]

FIG. 1 is a diagram showing a system configuration of a first embodiment of the present invention. As shown in FIG. 1, the multiprocessor system according to the present invention includes a plurality of processor modules 10_0 to 10_n, a shared memory 15, a main control unit 18, a state monitoring bus 19, and a global bus 1.
10, an I / O bus 111 is provided. At least one of the plurality of processor modules 10_0 to 10_n is used as a spare processor module.

Each of the processor modules 10_0 to 10_
n and the main control unit 18 are connected by a state monitoring bus 19, and the processor modules 10 </ b> _ <b> 0 to 10 — n and the shared memory 15 are connected by a global bus 110. Further, the main control unit 18 and the shared memory 15 are connected to a state monitoring bus 19. Further, each of the processor modules 10_0 to 10_n transmits and receives signals to and from a peripheral function unit (not shown) via the I / O bus 111.

Each of the processor modules 10_0 to 10_
n is a central processing unit (CPU) 11_0 to 11_
n, register means (REG) 12_0 to 12_n, I /
It has O interfaces 13_0 to 13_n.

Here, the register means (REG) 12_0
To 12_n, identification information for identifying each processor module (module identification ID, function identification ID, etc.)
Are stored, and their identification information is used when accessing the individual area in the shared memory 15.

The shared memory 15 is divided into a common area 16 accessible by all processor modules and n individual areas 17_0 to 17_n-1 individually accessed by the processor modules.
6 includes a shared memory mapping table 16_1 and an address conversion unit 16_2.

Here, the address conversion unit 16_2 performs
The local individual addresses input from the PUs 11_0 to 11_n are converted into global shared memory addresses. Further, the main control unit 18 includes a switching control unit 18_1, and when a certain processor module fails, the switching control unit 18_1 performs a process for switching the failed processor module to a standby processor module.

FIG. 2 shows a configuration example of the shared memory mapping table. The area of the shared memory is divided into blocks, and each processor module is assigned some of the blocks and occupies those blocks as individual areas.
The shared memory mapping table stores the number of blocks occupied by each processor module.

As shown in FIG. 2, identification information (module identification ID, function identification ID, etc.) for identifying each processor module is stored in register means 22_0 to 22_n-1, and each processor module occupies the corresponding identification information. The number of blocks to be performed is stored in the register means 23_0 to 23_n-1.

The shared memory mapping table shows the correspondence between each processor module and the memory capacity of its individual area. Also, the table contains 1
Information indicating the capacity of the unit block is stored in the capacitor register means (CREG) 20. Further, a spare module register means (SRE) for storing a spare processor module identification ID used at the time of processor module switching.
G) 21 is provided.

Here, the information for identifying the processor module includes logical identification information (logical ID) of the processor module and identification information (physical ID) corresponding to the mounting position.
D), identification information (function ID) corresponding to the function type and the like can be used, and these identification information can be stored in the register means (REG) 1 in the processor modules 10_0 to 10_n.
It corresponds to the information stored in 2_0 to 12_n.

FIG. 3 shows the processor module # 0 (10
_0) shows a switching processing flow when a failure occurs in the module and the spare processor module #n (10_n) is switched.

When a failure occurs in the processor module # 0 (10_0) (S3_1), the processor module switches the alarm signal and the processor module identification information (module ID # 0) in the main control unit via the status monitoring bus 19. It notifies the unit 18_1 (S3_2).

Upon receiving the alarm signal transmitted in the above step (S3_2), the switching control unit 18_1
The switching process is started (S3_3). At this time, the module ID # 0 is stored in an internal register of the switching control unit 18_1.

The switching control unit 18_1 first accesses the shared memory mapping table 16_1 in the shared memory 15 and sets a spare module register (SREG).
The identification information of the spare processor module stored in 21 is written into the ID storage register means 22_0 of the failed processor module (S3_4).

Thereafter, the switching control unit 18_1 writes the module identification ID of the failed module # 0 into the spare module register means 21 in the shared memory mapping table (S3_5). After that, the switching control unit 18_1
Notifies the spare processor module #n to access the shared memory mapping table (S
3_6).

The spare processor module #n has its own module identification ID in the shared memory mapping table.
The number of blocks Num # 0 corresponding to the register means 23_
0, the processing of the faulty processor module # 0 is taken over, and the switching to the spare processor module is completed by the above operation flow (S3_
7).

FIG. 4 shows a mapping example of a memory address space used by a central processing unit (CPU) in a processor module. CPU in each processor module
Has a memory address space 4-1 corresponding to an individual area allocated to itself in the shared memory, and a memory address space 4-2 of the common area. The memory address space of the CPU in the processor module further includes an address space 4-3 for a local memory, an internal register, a boot ROM, an internal I / O, and the like.

The size of the individual area allocated to each processor is determined by the registers 23_0 to 23_n for storing the number of memory blocks in the shared memory mapping table shown in FIG.
By changing the set value of −1 at the time of starting the system, it is possible to make it variable. Each processor module reads out the number of memory blocks 23 — 0 to 23 — n−1 to read the memory address of the individual area of each processor module. Change space.

Even when there is a difference in the amount of data to be processed between the processor modules, the memory capacity of the individual area of each processor module and the address space thereof are changed according to the amount of data, so that the individual memory type function distribution As with the processor system, a flexible system according to the processing amount can be constructed.

When the multiprocessor system fails or when system initialization and resetting are necessary, the setting of the shared memory including the reallocation of the area in the shared memory is collectively performed by one At least one processor module is configured to have, as an address space for the shared memory, a memory address space covering the entire address space of the shared memory so that the processing can be performed by the processor module.

Further, when a module failure occurs when the spare module does not exist or is unavailable, the module is not switched, and the failure is performed using the common area 4-2 in FIG. It is possible to initialize the individual area of the module where the error has occurred. As a result, the start-up time when the failed module is replaced with a new module can be reduced.

Next, as an embodiment of the switching control, as in the first embodiment shown in FIG.
In addition to the embodiment in which the switching to the spare processor module is performed by the switching control unit 18_1 provided for the
However, it is also possible to adopt a configuration in which the processor module performs communication between the processor modules to perform switching without any control. Hereinafter, the second embodiment will be described.

FIG. 5 is a diagram showing a switching control system using communication between processor modules according to the second embodiment. The system according to this embodiment includes a processor module 50_0 to 50_n, a shared memory 55, a main control unit 5
8, status monitoring bus 59, global bus 510, I / O
A bus 511 and an interprocessor communication bus 512 are provided.

Each processor module 50_0-50_
n and the main control unit 58 are connected by a state monitoring bus 59, and each of the processor modules 50 </ b> _ <b> 0 to 50 — n and the shared memory 55 are connected by a global bus 510.

Each of the processor modules 50_0 to 50_0
50 — n are connected by a processor module bus 512 and communicate between the processor modules. Each of the processor modules 50_0 to 50_n is connected to the I / O bus 5
11 transmits and receives signals to and from a peripheral function unit (not shown).

Each processor module 50_0-50_
n is a central processing unit (CPU) 51_0 to 51_
n, register means (REG) 52_0 to 52_n, I /
O interface 53_0-53_n, switching control unit 5
4 — 0 to 54 — n.

Here, register means (REG) 52_0
To 52_n store identification information (module identification ID, function identification ID, and the like) for identifying each processor module, and the identification information is stored in an individual area 57_ in the shared memory 55.
Used to access 0 to 57 — n−1.

Each of the switching control units 54_0 to 54_n
Performs processing for switching a failed processor module to a standby processor module when a processor module fails.

The shared memory 55 includes a common area 56 accessible by all processor modules and n individual areas 57_ each individually accessed by the processor modules.
The common area 56 includes a shared memory mapping table unit 56_1 and an address conversion unit 56_2. The address conversion unit 56_2 outputs the CP
The individual address input from U51_0 to 51_n is converted into a common address.

FIG. 6 shows a switching control flow in the second embodiment shown in FIG. As shown in the figure, when the processor module # 0 (50_0) fails (S6_
1), the processor module # 0 (50_0) sends an alarm signal and its own module identification ID onto the inter-processor module bus 512 (S6_2). Only the spare processor module #n transmits the transmitted signal.
Received by the switching control unit 54_n (S6_3)
.

The spare processor module #n switches the received module identification ID information (# 0) to the switching control unit 54.
_N in the register means or the like, and the switching control unit 54
_N accesses the shared memory mapping table 56_1 in the shared memory and overwrites the module identification ID of the failed processor module # 0 with the ID information of the processor module #n (spare) (S6-).
4).

Next, the switching control unit 54_n of the spare processor module #n accesses the shared memory mapping table 56_1, and stores its own module identification ID information (#n) and the ID information of the failed processor module # 0. Overwrite the existing area (S6_5).

With the above processing, the switching process of the individual allocation area in the shared memory between the failed processor module and the spare processor module is completed on the shared memory mapping table 56_1, and the spare processor module #n is switched from the failed processor module # 0 to the spare processor module #n. The process is taken over and started (S6_6).

FIG. 7 shows a configuration example of a shared memory mapping table according to the second embodiment of the present invention. In this case, a mapping register (71_n, 72_n) of the spare processor module #n is required instead of the spare module register means 21 of FIG. 2, and when the processor module is switched, ID information is exchanged between the failed processor module and the spare processor module. As a result, the individual assignment area in the shared memory is switched.

The address of the individual area on the shared memory allocated to each processor module is calculated by the address conversion unit from the number of memory blocks stored in the shared memory mapping table and the head address of the individual memory in the shared memory. . The calculation of the address of the individual area on the shared memory by the address conversion unit is the same in both the first and second embodiments.

In the second embodiment, as shown in FIG. 7, the shared memory mapping table stores the mapping register (71__) of the spare processor module #n.
n, 72 — n) store the module identification ID (#n) of the spare processor module and information (“spare”) indicating that the spare processor module is spare in the memory block number storage unit.

[0061]

As described above, according to the present invention,
Allocate an individual area to the shared memory for each processor module, each processor module occupies the individual area,
With the configuration in which the individual areas can be individually accessed, each processor module can access each individual area in the shared memory at any time in parallel, and there is no need to perform exclusive control on the shared memory.

Therefore, the entire multiprocessor system not only prevents the processing performance and reliability from being reduced due to complicated processing such as exclusive control, but also shares applications designed based on the architecture of the individual memory type function distributed multiprocessor. Since it can be operated on a memory type load distribution multiprocessor system, it is possible to efficiently and economically construct a processor system.

Further, a shared memory mapping table and an address converter are provided in a common area of the shared memory, and an address to a local individual memory for each processor module is converted to an address of a global individual area in the shared memory. Accordingly, each processor module can access each individual area without being conscious of using the shared memory.

Also, in the shared memory mapping table,
Module identification ID of each operating processor module
And the module IDs of the spare processor module and the module IDs of the failed processor module and the spare processor module are rewritten on the table when a failure occurs, whereby the failed processor module can be quickly switched to the spare processor module. In addition, the failed processor module can be made to stand by as a spare processor module after recovery, and can be switched and operated repeatedly for the failure of another processor module, so that a stable processor system can be constructed at low cost. it can.

[Brief description of the drawings]

FIG. 1 is a diagram showing a system configuration according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a shared memory mapping table according to the first embodiment of this invention.

FIG. 3 is a flow chart of processor module switching according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a mapping of a memory address space of the processor module of the present invention.

FIG. 5 is a diagram illustrating a system configuration according to a second embodiment of the present invention.

FIG. 6 is a flow chart of processor module switching according to the second embodiment of the present invention.

FIG. 7 is a diagram illustrating a shared memory mapping table according to the second embodiment of this invention.

FIG. 8 is a diagram showing a basic configuration of a W-CDMA communication system.

FIG. 9 is a configuration diagram of a shared memory type load distribution multiprocessor system.

FIG. 10 is a configuration diagram of an individual memory type function distributed multiprocessor system.

[Explanation of symbols]

 10_0 to 10_n Processor module 11_0 to 11_n Central processing unit (CPU) 12_0 to 12_n Register means (REG) 13_0 to 13_n I / O interface 15 Shared memory 16 Common area 16_1 Shared memory mapping table 16-2 Address conversion unit 17_0 to 17_n- 1 Individual area 18 Main control unit 18_1 Switching control unit 19 State monitoring bus 110 Global bus 111 I / O bus

Claims (11)

[Claims] 1. A multiprocessor system comprising: a plurality of processor modules including at least one spare processor module; and a shared memory commonly used by the plurality of processor modules, wherein the shared memory includes a plurality of processor modules. An individual area access unit that occupies as an individual memory and has an individual area assigned to each processor module, and converts access from the processor module to the individual memory to access to each individual area in the shared memory; Switching control means for switching the allocation of individual areas in the shared memory between the failed processor module and the spare processor module when a failure occurs in the processor module; Multiprocessor system characterized by having a configuration for further processing takes over the Lumpur. 2. The multiprocessor system according to claim 1, further comprising: a main controller configured to monitor a failure of each processor module via a state monitoring bus. The main controller includes the switching controller, and the switching controller controls a shared memory. Switch the allocation of individual areas within
2. The multiprocessor system according to claim 1, wherein the multiprocessor system has a configuration in which the processing of the failed processor module is taken over by the spare processor module. 3. The multiprocessor system according to claim 1, wherein each of the processor modules is connected to each other by an interprocessor communication bus, and the switching control unit is provided in each of the processor modules. The fault information is communicated between the module and the spare processor module via the inter-processor communication bus, and the switching control means in the spare processor module switches the allocation of the individual area in the shared memory. 2. The multiprocessor system according to claim 1, wherein the multiprocessor system has a configuration taking over the processing of (1). 4. An individual area access means for sharing an address to an individual memory for each processor module using the shared memory mapping table storing the allocated capacity corresponding to each processor module and using the shared memory mapping table. The multiprocessor system according to claim 1, further comprising: an address conversion unit configured to convert an address of an individual area in the memory. 5. The multiprocessor system according to claim 1, wherein, when the processor module is closed or hot-plugged, the switching control unit uses the blocked or hot-plugged processor module as the faulty processor module.
2. The multi-processor according to claim 1, wherein the allocation of the individual area in the shared memory and the individual area of the spare processor module is switched, and the individual area of the processor module is taken over by the spare processor module to continue processing. Processor system. 6. Each individual area in the shared memory has a configuration in which one or more memory blocks of a fixed capacity are allocated, and the capacity of the individual area is changed by changing the number of the memory blocks allocated to the individual area. 2. The multiprocessor system according to claim 1, wherein the multiprocessor system has a variable configuration. 7. The multiprocessor system according to claim 1, wherein the individual access unit is arranged in a common area in a shared memory accessible to all of the processor modules. Multiprocessor system. 8. The shared memory mapping table,
A storage unit for storing information indicating the capacity of a unit memory block constituting an individual area in the shared memory; and a storage unit for storing a correspondence relationship between identification information of the processor module and the number of memory blocks allocated to the individual area of the processor module. The multiprocessor system according to claim 4, further comprising: a storage unit that stores identification information of the spare processor module. 9. The shared memory mapping table in the individual area access means includes a storage unit for storing information on a capacity of a unit memory block constituting an individual area in the shared memory, identification information of each processor module, and each processor module. A storage unit for storing the number of memory blocks of the individual area assigned to the spare processor module in association with the number of memory blocks of the individual area corresponding to the identification information of the spare processor module. The multiprocessor system according to claim 8, wherein is stored. 10. The shared memory including at least one of the processor modules having a memory address space covering an entire address space of the shared memory, wherein the one processor module includes reallocation of an area in the shared memory. The multiprocessor system according to claim 1, wherein the multiprocessor system has a configuration capable of executing the settings in a batch. 11. A shared memory for storing a plurality of processor modules having at least overlapping functions, a processing result of the plurality of processor modules distinguished by a storage area allocated to each of the plurality of processor modules,
A multiprocessor system comprising: a spare processor module for spare of the processor module; switching control means for assigning a storage area assigned to the failed processor module as a storage area of the spare processor module; A multiprocessor system comprising: an initializing means for initializing a storage area allocated to the failed processor module when a failure occurs in the spare processor module.