CA1229400A - Telecommunications packet switching system - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

A switching centre for a telecommunications packet switching system has a number of similar data processing units, a shared memory, at least one common bus connecting the processors and the memory, and devices controlling access to the common bus, each data processing unit in-cluding a microprocessor, an internal memory, an inter-face to the common bus, an external access interface, and an internal bus connecting these components, and a control console connected to the external interfaces of certain of the data processing units which act as control units, communication lines being connected to external access interfaces of other data processing units which act as packet switches. The common bus is preferably duplicated, and the data processing units are redundantly connected so that in the event of failure of a unit, full function can be maintained.

Description

I

The present invention relates to packet switching systems used in telecon~unications~ and more particularly to a switching center and data concentrator for use in data communication networks using the packet switching technic qua.

The present invention uses the "virtual circuit" technique, in which the switching center controls communication bet-wren two subscribers without an actual physical connection between the two being established. Instead, storage and retransmission facilities available in the switching Sinatra enable communication between the subscribers to continue whilst a virtual connection is established. With this "virtual circuit" technique, it is not necessary to deli-gate portions of the switching system to maintenance of a particular connection, and the functions of the center can be effectively modularized, and rendered more efficient and reliable by the provision of redundant circuits for the performance of particular classes of function.

According to the invention, a switching center for a tote-communications packet switching system comprises a plural-fly of similar data processing units, a shared memory, at least one cannon bus connecting said processors and said memory, and means controlling access to said common bus, each data processing unit comprising a microprocessor r an internal memory, an interface to said common bus an Tory-net access interface, and an internal bus connecting these components, a control console connected to the external access interfaces of curtain of said data processing units, and communication lines connected to external access inter-faces of certain others of said data processing units.

Preferably, the common bus is duplicated, and the data processing units are redundantly connected so that the con trot console and the communications lines are Mach inter-faced to at least -two units.

go Basically, the functions that are carried out by the system are respectively control functions, signaling functions, packet switching functions, and operator-system communication functions.

The purpose of the control functions is to manage the center and supervise the functioning of the system. The purpose of the signaling functions is to exchange inform motion with subscribers' terminals and with other switch-in centers in order to establish, maintain and terminate communications. The purpose of the packet switching lung-lions is to store, process and retransmit packets between virtual input circuits and virtual output circuits. The purpose of the operator-system communications is to allow interaction between the operator and the system for the purpose of operation and maintenance.

The system is based upon the use of particular units for carrying out distinct functions, with these functions nor-molly shared between more than one unit, although a part-cuter function can be sustained by a single unit if necessary. This redundancy assists in providing reliability and efficiency of function.

Further features of the invention will become apparent frown the following description of an exemplary preread embodiment with reference to the ascompanyiny drawing, in which:-Figure 1 shows the basic organization of the system unblock form, whilst a somewhat more detailed diagram is shown in Figure 2.

Referring Jo Figure 1, the control functions mentioned above are assigned to control units 1 and 2, and the signaling and packet switching functions are assigned to packet switches 3, 4 and 5. Operator-~ystem con~unications I

are assigned to a system console 6. A shared memory 7 stores data which may be required by more than one unit of the system, and a common bus 8 maintains communication between the various units of the switching center. The center employs a multi-processor structure in which disk tint processing units, namely the control units 1 and 2 and the packet switches 3, 4 and 5 communicate with each other and with the shared memory 7 by means of the common bus system 8.

The switching center is shown in more detail in Figure Z, in which the processor units 1, 2, 3, 4 and 5 are shown within broken lines. Each of these units may consist of a similar data processing unit or module, and these modules can be increased in number in accordance with the required capacity and degree of redundancy thought desirable in the switching center.

Each processor unit comprises a microprocessor 14, 15, 35, 36 or 37 with support circuits, its own memory and interlaces for connection of the unit.

In Figure I the common bus 8 is shown duplicated by a second common bus 9, both buses being capable of being placed in communication with each of the control units 1 and 2 and packet switches 3, 4 and 5 as jell as with the shared memory 7. The capacity of the shared memory 7 de-ponds upon the requirements of the switching center.
Typically it can be arranged in 32 kilobyte modules, and be of up to l Megabyte capacity. Access to the Canaan buses 8 and 9 is placed under the control of bus control-tens lo and 11. Data passing to and from the shared memory travels along these buses, as does data for trays-for between processing units and data relating to inter ruts generated by the processing units. The processing units are also connected via external interlaces 27, 28, 29, 30 and 31 either Jo the console 6 or to the various Lo communication lines serviced by the switching center, according to whether the units are control units or packet switches.

Considering now the individual control units, the function of these units is supervision of the operation of the center, automatic maintenance of the center, control of peripheral units of the oentre, and maintenance of records and statistics of operation of the center.

In the example shown, the tasks that carrying out these functions imply are divided up amongst the two control units l and 2 during normal operation of the center. In the event of a fault, a single one of the two control units can handle all of the functions. In order to deal with possible fault situations, each control unit monitors the operative condition of the other at all times.

Internally, each control unit 1 and has an internal bus 12 or 13 through which other components of the unit Camille-gate with the microprocessor 14 or 15 which executes con-trot programs stored in its internal memory 16 or 17.

Various peripheral devices are connected by appropriate interfaces to the internal bus of each unit, and interrupt the microprocessor in order to exchange information by means of an interrupt control peripheral 18 or lg. These peripheral devices are concentrated in the system console 6 and communicate with the control units through inter-faces 27 and 28. They comprise a peripheral memory 20, which is a mass storage device storing programs used to control the system. An operations record unit 21 records in hard copy the details of operation of the Sinatra An input and display unit 22 permits the operator to have interactive dialogue with the machine, and an alarm unit 23 comprises audible and visible indicators of the status of the system.
A clock 24 synchronizes the clocks of the various processing units and provides an external time display at the console.

The units 1 and 2 have direct interfaces 47 and 48 from their internal buses 12 and 13 to the shared memory 7 so that they can access the latter without using a common bus 8 and 9. Similarly, the bus controllers 10 and 11 have independent interfaces to the internal buses of the control units 1 and 2 so that the latter can control the bus controllers without using the common buses 8 and 9.

The number of peripherals of one sort or another that can be connected to the internal bus of a control unit 1 or 2 depends upon the number of input and output ports available, but is usually substantial, typically about 40. The inter-net bus of each control unit 1 and 2 is connected to the common buses by a bus access interface 25 or 26.

The data processing units which act as packet switches 3, 4 and 5 are generally similar to the units 1 and 2, but have the functions of controlling signal communications with subscribers and the remainder of the network, control-lying the reception and transmission of data through the line interfaces, controlling transfer of data between the unit itself and another unit via the common buses, control of information exchange with the shared memory over the common buses, and processing of control data and supervisory commands exchanged with either control unit or the other packet switches over the common buses, supervision of the unit itself, and the generation of operating and stalls-tidal data concerning operation of the unit. typically a switching center may contain up to 32 packet switches, dependent upon the architecture of the system.

The internal structure ox each packet switch is the same as that of a control unit, except that instead of a port-furl interface 27 or 28 it has a line interface 29, 30 or 31, and the independent connections to the shared memory 7 and the bus controllers 10 and 11 are omitted. Thus a packet switch consists of an internal bus 32, 33 or 34 to which are connected a processor 35, 36 or 37, an internal memory 38, 39 or 40, an interrupt control peripheral 41, 42 or 43, the line interface 29, 30 or 31, and a bus access peripheral 44, 45 or 46. The line interfaces are serial input and output devices capable of receiving and transmit-tying data to and from communication lines in asynchronous, synchronous and HDLC modes. The maximum number of lines that can be handled by a packet switch depends on the baud rate of the lines and the mode of data transmission, typically being between 10 and I lines.

The hardware so far described is operated under control of a system program. The hardware provides basic information transfer devices in a modular form which allows the system programming to carry out the control and supervision of the packet switching functions. Information transfer amongst the various units of the system takes places as described below.

Zen a peripheral or line interface of one of the processor units receives a control signal from a peripheral or line associated therewith, which signals to it the beginning of transmission of a data block, it interrupts the micro-processor of the unit by means of the interrupt control peripheral. The processor sets up direct access to the internal memory of the unit so that the data block received throuc3h the interface is directly transferred to the inter-net memory. The processor assigns space in the internal memory and organizes the direct memory access in order to concatenate blocks if necessary. Upon completing the transfer of each block, the interface interrupts the pro-censor with information concerning block length. Zen the processor has stored the entire block in its internal memory it processes the block and prepares to transfer it Z9~

to a destination unit within the system; this unit may be the shared memory or another processing unit.

Before carrying out the transfer, the processor ascertains that the destination unit can receive the block and then asks its bus access interface to capture a common bus. In order to achieve this, the bus access interface waits until a bus controller captures the common bus, whereupon the bus controller then supervises the time for which the common bus is captured by the bus access peripheral of the originating unit.

In the case of a transfer to another processor unit, the bus access peripheral of the source unit places on a common bus the address of the bus access interface of the destine-lion unit, as well as -that ox its own bus access peripheral.
Upon recognizes its address, the destination Gus access peripheralverifiesthat there is available space assigned to the source unit in the internal memory of the destine-lion processing unit. The destination bus access purify-fat then sets up direct memory access to its internal memory and indicates to the source bus access peripheral that it is ready to receive data. The transfer of a block or blocks then takes place from one internal memory to the other, with each processing unit making use of direct memory access. Once the transfer is complete, the dust-nation processing unit signals the source unit accordingly.

If the data transferred is to be output through a line interface or peripheral interface, transfer from the inter-net memory of the destination unit to the interface is similar to the transfers previously described.

Data transfer for the purpose of control or supervision of the units it carried out by reading from or writing to input and output registers provided in the bus access peripheral of the units. Means are also provided by which u the internal bus of a processing unit may be connected in a transparent manner to a common bus for the purpose of read/write access to the shared memory by the processing units, in which case the processing unit concerned sees the shared memory as an extension of its own internal memory.

The bus controllers and the shared memory are directly connected, as already mentioned, to the internal buses of the control units for top purposes of supervision, control and maintenance of the system, for which purpose they in-turret the control units by means of the interrupt con-trot peripherals of the latter, in just the same way as any other peripheral.

The programs used to operate the switching center fall into the following classes, namely basic operating system pro-grams, communication line control programs, application programs, programming utilities, operating utility and auxiliary programs, and test and maintenance programs.

The basic operating system programs operate the hardware facilities Go the system, namely the microprocessors, memories and input/output ports of the system. The main functions of these programs are task control, namely the basic sequencing of the entire system according to which tasks are initiated, prepared, stopped or delayed, and the exchange of data between tasks and within the interrupt system is controlled with reference to the priority and reentrance of each task. These programs also deal with error handling, with regard is the redundancy available in the system and those parts of the system which are fault tolerant. If an error cannot be retrieved, the fault should be externally notified. Other junctions are memory management, both of the shared memory and of the internal memories of the various units, bus control, involving organization of thy utilization of the common and internal buses of the system, having regard to the servicing of interrupts generated by the packet switches and the control units and the provision of access to the shared memory. Interrupt management is required, having regard to the priority and masking of interrupts, and their routing to appropriate service routines. Clock control functions are provided to the entire system, have in regard for the necessity of synchronizing operation of the various processing subsystems. The loading and dumping of programs is controlled, both locally within the switching center as well as remotely to or from another switching center. System reconfiguration may be provided for, both in response to outside parameters as well as on a dynamic reconfiguration basis. This class of programs also includes specialized programs for the operation of each type of peripheral employed in the soys-them, such as those incorporated in the console 6.

The communication line control programs have the functions of controlling the different line protocols that the soys-them supports, transferring information received from the lines to the appropriate application program for its processing, and receiving data from such application pro-grams and transmitting it upon the appropriate output line. The basic task carried out by these programs are operation of high speed lines using ~DLC protocol opera-lion of medium speed lines using BSC transparent and non-transparent protocols, ETUDE duplex protocol, and terminal control protocols at greater than 12Q0 bus, synchronously or asynchronously with or without multiplexing, and operation of low speed lines with control protocols for NCR-270, IBM 2970, Olivetti 349~B and Bound Teletypes terminals.

The applica~îon programs are concerned with implementation of the functional specifications of a special data trays-mission network with which thy are associated The basic function of such application programs is to receive data from the control programs, to process such data and return it to the control programs. The processing may be of two types, namely the concentration of data and the switching ox data. Typical tasks carried out by the application programs are the packing and unpacking of data, the process-in of data packets, the control of the generation and processing of packets, and message routing.

The programming utilities firstly provide the junctions of facilitating implementation of the other programs by pro-voiding compilation, assemble, debugging and testing lung-lions. Furthermore, these programs provide the means for utilizing the switching center itself as a program imply-mentation center, as a network control center, and as an auxiliary data processing services center. This group of programs provides the executable code fox controlling the physical functions of the system.

The operating utility and auxiliary programs firstly provide the functions of capturing data during actual operation of the center for the purpose of providing data and statistics, and thus the means for external control of the performance of the center. Secondly, they facilitate the operation of the center by carrying out tasks such as structuring and reallocating the comma, internal or peripheral memories, monitoring the handling of messages from the communication lines, the switching center or the network, tracing packets through the switching center and the network, and capturing data and statistics from not only the system but the network as a whole, the subsystems within the center, and data relating to specific applique-lions, tasks, locations and terl~als within the system Such programs may further be used to control the dumping of data from the various memories in the system, as well as from its peripherals or remote switching centers. Some of these tasks are executed on line, during operation of the switching center, whilst others are carried out off line based on data collected in real time during operation of the center.

The test and maintenance programs have the functions o-f providing data enabling preventive maintenance of the system, and, once an actual or potential fault is detected, providing the most appropriate means for its diagnosis and elimination, and the maintenance of correct operation even under unfavorable conditions. This type of program generally has no reason to be resident, and can be loaded as required. Such programs fall into two groups, namely programs which cannot be run concurrently with other programs, and service programs which can run under control of the operating system concurrently with other programs.

All ox the programs are written in modular structured form, and their data and instruction can be resident in both the internal memories of the various units as well as in the common unit, being in general capable of briny executed both by the packet switches as well as the control units.
In -this connection it is necessary to distinguish between programs which carry out shared functions for all of the processing units, and programs which carry out specific functions of only certain types of processing unit. Pro-grams of the first type are available to all of the processing units, normally having their instructions in the internal memory of the unit and their data partly in the internal memory and partly in the common memory. All of the instructions stored in the internal memory of a unit are redundant, being available elsewhere in the system. The second type of program is present only in those processing units why ah are required to provide the function controlled by the program. As before, the in-structions art help by the internal memory, and the data can be shared between the internal memory and the common memory. In this case, however the redundancy only exists as between those processing units which carry out the same specific functions.

Claims (13)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A switching centre for a telecommunications packet switching system comprising a plurality of similar data processing units, a shared memory, at least one common bus connecting said processors and said memory, and means controlling access to said common bus, each data proces-sing unit comprising a microprocessor, an internal memory, an interface to said common bus, an external access inter-face, and an internal bus connecting these components, a control console connected to the external access inter-faces of certain of said data processing units, and com-munication lines connected to external access interfaces of certain others of said data processing units, wherein those other of the data processing units connected to the communication lines act as packet switches, and wherein those data processing units connected to the control con-sole function redundantly as control units for the system, so as to establish virtual circuits between communication lines connected to the packet switches.

2. A switching centre according to Claim 1, wherein the common bus is duplicated, and the data processing units are redundantly connected so that the control console and the communications lines are each interfaced to at least two units.

3. A switching centre according to Claim 1 or 2, wherein the console comprises a peripheral memory, an operations record unit, an input and display unit, an alarm unit and a real time clock.

4. A switching centre according to Claim 1 or 2, wherein the internal memories of the data processing units redun-dantly store the instructions or programs forming part of an operating system for the centre, the data for such programs being located partly in said internal memories and partly in the shared memory.

5. A switching centre according to Claim 1 or 2, wherein access to the at least one common bus by the processing units is controlled by bus controllers connected to said control units.

6. A switching centre for establishing virtual circuits between line interfaces in a telecommunications packet switching system, comprising:

a shared internal communication bus;

two control units connected to said shared communication bus, each independently capable of controlling an auto-matic maintenance of the system, the taking of measure-ments and statistics of the system and controlling a plurality of peripherals for the system;

a shared memory connected to said shared communication bus for receiving, storing and transmitting stored infor-mation from a plurality of sources on said shared commu-nication bus;

a console connected to said two control units for receiv-ing and displaying information from said control units and for supplying information to said control units; and a plurality of packet switches each connected to said shared communication bus and each for controlling data from subscribers of the system, for controlling the receipt and transmission of data using line interfaces, for controlling data transfer to other packet switches and to at least one of said control units, for control-ling exchange of information with said shared memory and for controlling internal maintenance, measurements and statistics for itself.

7. A switching centre according to claim 6, including up to 32 of said packet switches connected to said shared communication bus.

8. A switching centre according to Claim 7, wherein each of said control units comprises an internal bus, a micro-processor connected to said internal bus for executing control programs, an internal memory connected to said internal bus for storing data and the control programs, an interrupt control peripheral connected to said inter-nal bus and to said microprocessor for controlling acti-vation and de-activation of said microprocessor, a bus control peripheral connected between said internal bus and said shared communication bus for establishing com-munication between said control unit and said shared communication bus, and from 1 to 40 peripheral interfaces connected to said internal bus, each of said peripheral interfaces being connected to said console for establish-ing communication between said console and said control unit.

9. A switching centre according to Claim 7, wherein each of said packet switches comprises an internal bus, a micro-processor connected to said internal bus for executing control programs, an internal memory connected to said internal bus for storing data and control programs, an interrupt control peripheral connected to said internal bus and said microprocessor for activating and de-activating said microprocessor, a bus control peripheral connected between said internal bus and said shared communication bus for establishing communication between said packet switch and said shared communication path, and from 1 to 40 line interfaces connected to said internal bus for re-ceiving and transmitting data to and from subscribers of the switching centre.

10. A switching centre according to Claim 8, wherein each of said packet switches comprises an internal bus, a microprocessor connected to said internal bus for exe-cuting control programs, an internal memory connected to said internal bus for storing data and control programs, an interrupt control peripheral connected between said internal bus and said microprocessor for activating and de-activating said microprocessor, a bus control peri-pheral connected between said internal bus and said shared communication bus for establishing communication between said packet switch and said shared communication bus, and from 1 to 40 line interfaces connected to said internal bus for receiving and transmitting data to and from subscribers of the switching centre.

11. A switching centre according to Claim 6, wherein said shared memory is modular and enlargeable, each con-trol unit having at least one interface to said shared memory, said shared memory connected to and directly controllable by each of said control units through its interface.

12. A switching centre according to Claim 10, wherein said shared memory is modular and enlargeable, said shared memory being connected to one of said peripheral interfaces of each of said control units for direct con-trol by each of said control units.

13. A switching centre according to Claim 7, including an additional shared communication bus connected to each of said two control units, said shared memory and each of said plurality of packet switches.