JPH01276742A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01276742A JPH01276742A JP10608288A JP10608288A JPH01276742A JP H01276742 A JPH01276742 A JP H01276742A JP 10608288 A JP10608288 A JP 10608288A JP 10608288 A JP10608288 A JP 10608288A JP H01276742 A JPH01276742 A JP H01276742A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- sputtered
- wiring layer
- sputtering
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000004544 sputter deposition Methods 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000000203 mixture Substances 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 16
- 238000005478 sputtering type Methods 0.000 claims description 3
- 239000007769 metal material Substances 0.000 abstract description 4
- 229910021364 Al-Si alloy Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000956 alloy Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000004043 dyeing Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路素子の製造方法にかかり、より
詳しくは金属配線層の形成技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor integrated circuit element, and more particularly to a technique for forming a metal wiring layer.
現在、半導体装置の金属配線層は広くスパッタリング技
術により形成されている。特にアルミニウムは堆積・パ
ターン形成の容易なこと、シリコンやシリコン酸化膜と
の密着性の良いこと、電導度か大きくシリコン基板との
オーミック性の良いこと、さらに手に入り易く安価なこ
となどの理由により半導体装置の電極配線材料として現
在もっとも一般的に用いられている。Currently, metal wiring layers of semiconductor devices are widely formed by sputtering technology. In particular, aluminum is easy to deposit and pattern, has good adhesion to silicon and silicon oxide films, has high conductivity and good ohmic properties with silicon substrates, and is easily available and inexpensive. It is currently most commonly used as an electrode wiring material for semiconductor devices.
しかし、半導体技術の進歩は素子のＷ１細化、高集積化
をおし進め、その結果アルミニウム配線に対する要求も
年々厳しくなってきている。However, advances in semiconductor technology have led to smaller W1 and higher integration of devices, and as a result, requirements for aluminum wiring have become stricter year by year.
まず問題として段差構造に対するＡ１のつきまわり（ス
テップ力バレッヂ）か挙げられる。第２図に示すように
Ａ」か段差をのり越える部分で大きくくびれを生じ、配
線抵抗の増大や断線の原因となることかある。しかしこ
れは第４［２に示すようにスパッタ前のウェーハ温度に
依存し、温度が高い程ステップ力バレヅヂが良くなる傾
向にあるため、ウェーハに予備加熱を与えてスバ・ｌタ
リングする方法（加熱スパッタ）が用いられる場合があ
る。First, there is a problem with the throwing power of A1 (step force ledge) for the stepped structure. As shown in FIG. 2, a large constriction occurs at the part where the wire goes over the step, which may cause an increase in wiring resistance or a wire breakage. However, as shown in Section 4 [2], this depends on the wafer temperature before sputtering, and the higher the temperature, the better the step force variation tends to be. sputtering) may be used.
（５発明か解決しようとする課題〕
ところか、第３図に示すようにこの加熱スパッタはステ
ップ力バレヅヂを向上させる反面、アルミニウムの結晶
粒の成長やヒロックの発生による表面の鏡面反射率の低
下にともない外観を悪化させたり、多層配線の場合には
配線間のショートや電流リークの原因となり易い。近年
、浅い接合の突きぬけを防止するためにシリコンを添加
したＡＪ−３ｌ合金膜やエレクトロマイグレーションを
抑えるために銅を添加した合金膜が使用されているが、
第５図に示すようにシリコンや銅を添加したＡ（合金膜
はスパッタ前のウェーハ予備加熱によってヒロックなど
の発生を著しく増大させている。さらに第６図に示すよ
うに加熱スパッタした膜や合金膜では、スパッタの後工
程での熱処理によっても一層ヒロックなどの発生が促進
されている。(5) Problems to be Solved by the Invention However, as shown in Figure 3, although this heated sputtering improves the step force variation, it also reduces the specular reflectance of the surface due to the growth of aluminum crystal grains and the formation of hillocks. In the case of multi-layer wiring, short circuits between wirings and current leakage are likely to occur. An alloy film containing copper is used to suppress
As shown in Figure 5, the occurrence of hillocks in A (alloy film) doped with silicon or copper is significantly increased due to preheating of the wafer before sputtering. In the film, the occurrence of hillocks is further promoted by heat treatment in the post-sputtering process.
以上述べてきたように、ステップ力バレッヂを向上させ
る加熱スパッタや素子の特性、（＠顆性を向上させる合
金膜はその反面ヒロックなどの発生を顕著にする。As described above, heating sputtering and element characteristics that improve the stepping force ledge (@alloy film that improves condylarity), on the other hand, make the occurrence of hillocks more noticeable.
そこで、本発明の目的は、ステップ力バレッヂや素子の
特性・信頼性を損なわずにヒロックなどの発生を抑え層
間ショート、層間リークなどによる不良を減少できる半
導体装置の製造方法を提供することである。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that can suppress the occurrence of hillocks and reduce defects due to interlayer short circuits, interlayer leakage, etc. without impairing the step force barrier or the characteristics and reliability of the device. .
本発明の半導体装置の製造方法は、ある一層の金属配線
層を形成するために条件の異なる二種類以上のスパッタ
リング方法を用いることを特徴とする。この場合基板の
予備加熱温度やスパッタする金属材料の組成などの条件
を変更させることが好ましい。The method for manufacturing a semiconductor device according to the present invention is characterized in that two or more types of sputtering methods with different conditions are used to form a certain metal wiring layer. In this case, it is preferable to change conditions such as the preheating temperature of the substrate and the composition of the metal material to be sputtered.
第１図に本発明の半導体装置の製造方法における一実施
例を断面図を示す。FIG. 1 shows a cross-sectional view of an embodiment of the method for manufacturing a semiconductor device of the present invention.
第１図においては、素子形成のなされた半導体基板上に
、まず第１の条件として３００℃にウェーハを予備加熱
し膜厚５０００ＡのＡ、１ｌ−１％５ｉ１０３をスパッ
タリングし、さらにその上に第２の条件として予備加熱
無しで膜厚５０００ＡのＰｕｒｅＡ、Ｇ １０４をスパ
ッタリングしている。In FIG. 1, the first condition is to preheat the wafer to 300°C and sputter A, 1l-1% 5i103 to a thickness of 5000A on a semiconductor substrate on which elements have been formed. As condition 2, Pure A, G 104 with a film thickness of 5000 Å was sputtered without preheating.
第１図に示す本発明の実施例における方法によれば金属
配線がシリコン基板１０１と絶縁膜１０２により生じた
段差部をのり越える部分でのステップ力バレッヂか第２
図に示す予備加熱無しのスパッタリングによる場合のも
のに比べ著しく改善されていることかわかる。また、第
３図の加熱スパッタによるものに比ベヒロックなどが著
しく少なく表面状態が改善されている。According to the method according to the embodiment of the present invention shown in FIG.
It can be seen that this is significantly improved compared to the case of sputtering without preheating as shown in the figure. Furthermore, the surface condition is improved with significantly less vehicle locking than that produced by heating sputtering in FIG. 3.
以上は本発明の一実施例であり、ここに述べた２種類の
染作のスパッタリング方法だけでなく、３種類以上の条
件を用いても同様の効果を得ることかできる。また、ウ
ェーハの予備加熱温度やその組み合わせ方およびスパッ
タリングに用いる金属材料の組成や組み合わせ方および
膜厚らこの限りではなく予備加熱温度は〜５００°Ｃ程
度までは可能であり、金属材料もＡｊ 、Ａ、１ｌ−３
ｉに限らすエレクトロマイグレーションに強いＡＪＩ−
３ｉ−Ｃｕやその池の合金でも良い。The above is an embodiment of the present invention, and the same effect can be obtained not only by using the two types of sputtering methods for dyeing described herein but also by using three or more types of conditions. In addition, the preheating temperature of the wafer, the combination thereof, the composition and combination of metal materials used for sputtering, the film thickness, etc. are not limited to these, and the preheating temperature can be up to about 500°C, and the metal materials can also be heated to Aj, A, 1l-3
AJI- which is strong against electromigration limited to i
3i-Cu or its alloy may also be used.
以上述べた本発明の半導体装置の製造方法によれば、金
属配線のステップ力バレッヂを保ち且つヒロックの発生
を抑えるため、配線抵抗の増大、断線、眉間ショート、
層間リーク、外観の悪化など様々な不良要因を解消する
ことができる。According to the method for manufacturing a semiconductor device of the present invention described above, in order to maintain the stepping force barrier of the metal wiring and suppress the occurrence of hillocks, increase in wiring resistance, disconnection, short between the eyebrows,
Various causes of defects such as interlayer leakage and deterioration of appearance can be eliminated.
第１図は本発明の半導体装置の製造方法における一実施
例の断面図。
第２図および第３図は従来の半導体装置の製造方法によ
るものの断面図。
第４図はステップ力バレッチをスパッタリング前ウェー
ハ温度の関係を示す図。
第５図は鏡面反射率とウェーハ予備加熱温度のＩＳＯ係
を示す図。
第６図はスパッタ後工程での熱処理による鏡面反射率の
低下を示す図。
１０１．２０１．３０１・・・シリコン基板１０２．２
０２．３０２・・・絶縁膜
１０３・・・第１の条件により形成された金属配線層
１０４・・・第２の条件により形成された金属配線層
２０３．３０３・・・金属配線層
以上
出願人 セイコーエプソン株式会社
代理人 弁理士 上 柳 雅 誉（池１名）高 １ 図
第 ２１￥１
島 ３ ロ
スＩｔ” Ｎ／ ９前つｚ−ｔいｊＬＩＩＬ じＣ１
第 ４ 図FIG. 1 is a sectional view of one embodiment of the method for manufacturing a semiconductor device of the present invention. FIGS. 2 and 3 are cross-sectional views of a conventional semiconductor device manufacturing method. FIG. 4 is a diagram showing the relationship between step force bulleting and wafer temperature before sputtering. FIG. 5 is a diagram showing the ISO relationship between specular reflectance and wafer preheating temperature. FIG. 6 is a diagram showing a decrease in specular reflectance due to heat treatment in a post-sputtering process. 101.201.301...Silicon substrate 102.2
02.302...Insulating film 103...Metal wiring layer 104 formed under the first condition...Metal wiring layer formed under the second condition 203.303...Metal wiring layer and above Applicant Seiko Epson Co., Ltd. Representative Patent Attorney Masaharu Kamiyanagi (1 person) High School 1 Figure No. 21 ¥ 1 Island 3 Loss It” N/ 9 years ago
Figure 4
Claims (3)
異なる二種類以上のスパッタリング方法を用いることを
特徴とする半導体装置の製造方法。(1) A method for manufacturing a semiconductor device, characterized in that two or more types of sputtering methods with different conditions are used to form a certain metal wiring layer.
法の中に、基板の予備加熱温度の異なる条件を含むこと
を特徴とする請求項１記載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the two or more sputtering methods having different conditions include conditions in which the preheating temperature of the substrate is different.
法の中に、膜の組成が異なる条件を含むことを特徴とす
る請求項１記載の半導体装置の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1, wherein the two or more sputtering methods having different conditions include conditions in which the composition of the film is different.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10608288A JPH01276742A (en) | 1988-04-28 | 1988-04-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10608288A JPH01276742A (en) | 1988-04-28 | 1988-04-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01276742A true JPH01276742A (en) | 1989-11-07 |
Family
ID=14424647
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10608288A Pending JPH01276742A (en) | 1988-04-28 | 1988-04-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01276742A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6194311B1 (en) | 1998-06-26 | 2001-02-27 | Nec Corporation | Method for manufacturing semiconductor device capable of effectively carrying out hydrogen passivation |
| JP2007123296A (en) * | 2005-10-24 | 2007-05-17 | Oki Electric Ind Co Ltd | Process for fabricating semiconductor device |
-
1988
- 1988-04-28 JP JP10608288A patent/JPH01276742A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6194311B1 (en) | 1998-06-26 | 2001-02-27 | Nec Corporation | Method for manufacturing semiconductor device capable of effectively carrying out hydrogen passivation |
| JP2007123296A (en) * | 2005-10-24 | 2007-05-17 | Oki Electric Ind Co Ltd | Process for fabricating semiconductor device |
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