JPS6012770A - Thin film field effect transistor - Google Patents

Thin film field effect transistor

Info

Publication number
JPS6012770A
JPS6012770A JP58120508A JP12050883A JPS6012770A JP S6012770 A JPS6012770 A JP S6012770A JP 58120508 A JP58120508 A JP 58120508A JP 12050883 A JP12050883 A JP 12050883A JP S6012770 A JPS6012770 A JP S6012770A
Authority
JP
Japan
Prior art keywords
metal
thin film
layer
metal layer
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58120508A
Other languages
Japanese (ja)
Other versions
JPH0546107B2 (en
Inventor
Ikunori Kobayashi
郁典 小林
Sadakichi Hotta
定吉 堀田
Kiyohiro Kawasaki
清弘 川崎
Shigenobu Shirai
白井 繁信
Hiroki Saito
弘樹 斉藤
Seiichi Nagata
清一 永田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58120508A priority Critical patent/JPS6012770A/en
Publication of JPS6012770A publication Critical patent/JPS6012770A/en
Publication of JPH0546107B2 publication Critical patent/JPH0546107B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/456Ohmic electrodes on silicon
    • H01L29/458Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/7866Non-monocrystalline silicon transistors
    • H01L29/78663Amorphous silicon transistors
    • H01L29/78669Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate

Abstract

PURPOSE:To enable to protect the transistor made of polyimide, etc. by the guarantee of the transistor in heat insulating temperatures up to over 200 deg.C by a method wherein the electrode provided to the semiconductor thin film transistor constituting a picture display by being combined with a liquid crystal, etc. is composed of the laminated body of a heat insulating metal and a low reflectance metal. CONSTITUTION:The first metal 2 serving as the gate electrode is formed on an insulation substrate 1 of glass, etc., and an amorphous Si layer 4 is deposited over the entire surface including the metal via insulation layer 3. Next, the source electrode 7 and the drain electrode 8 opened are formed at the part opposed to the metal 2, with amorphous Si layers 9 and 10 containing phosphorus underlying the electrodes, and a polyimide 11 for transistor protection is adhered from inside the aperture to the ends of the electrodes 7 and 8. In this construction, the electrode 7 is put in a three-layer structure composed, from the substrate side, of the heat insulating metal 7a such as Cr, the low reflectance metal 7b such as Al, and the metal 7C such as Cr again, and the electrode 8 is also put in a three-layer structure of the same metals 8a, 8b, and 8c.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は薄膜電界効果トランジスタおよびその製造方法
に係シ、特に液晶等と組合せて画像表示装置を構成する
ためのシリコンを主成分とする非単結晶半導体薄膜電界
効果トランジスタ(以後TPTと呼ぶ)に関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a thin film field effect transistor and a method for manufacturing the same, and in particular to a non-single crystal thin film field effect transistor mainly composed of silicon for constructing an image display device in combination with a liquid crystal or the like. The present invention relates to a semiconductor thin film field effect transistor (hereinafter referred to as TPT).

シリコンを主成分とする非単結晶シリコン半導体TFT
はCdSe、CdTeなどを用いたTPTよシも安定性
がよく、また単結晶シリコンに比べてオン−オフ比が大
きいという利点を有する。しかしながらシリコンを主成
分とする非単結晶シリコン半導体TPTを利用して画像
表示装置を構成する場合にはより安定性を増し、画像(
コントラスト比)を改善するための工夫が必要である。
Non-single crystal silicon semiconductor TFT whose main component is silicon
TPT using CdSe, CdTe, etc. has better stability and also has the advantage of having a larger on-off ratio than single crystal silicon. However, when an image display device is constructed using a non-single-crystal silicon semiconductor TPT whose main component is silicon, stability increases and the image (
It is necessary to take measures to improve the contrast ratio.

以下、シリコンを主成分とする非単結晶半導体を代表し
て非晶質シリコン半導体を用いたTPTについて詳細に
説明する。
Hereinafter, a TPT using an amorphous silicon semiconductor as a representative non-single crystal semiconductor mainly composed of silicon will be described in detail.

従来例の構成とその問題点 第1図に従来例のひとつであるTPTの断面図を示す、
これは例えばガラスのような基板1上にゲート電極なる
第1の金属2が被着形成され、絶縁層3を介して非晶質
シリコン半導体層4が形成され、前記半導体層上にソー
ス、ドレイン電極なる第2の金属層6,6が被着形成さ
れた逆スタガー型TPT−(ある。
Structure of conventional example and its problems Figure 1 shows a cross-sectional view of TPT, which is one of the conventional examples.
For example, a first metal 2 serving as a gate electrode is deposited on a substrate 1 such as glass, an amorphous silicon semiconductor layer 4 is formed via an insulating layer 3, and a source and a drain are formed on the semiconductor layer. An inverted staggered TPT-type on which a second metal layer 6, 6 serving as an electrode is deposited.

画像表示装置は上述のようなTPTを多数配置した基板
と液晶とを組合せて構成され、TPTにより液晶をスイ
ッチングすることによって高密度の液晶画像表示装置が
得られる。
An image display device is constructed by combining a substrate on which a large number of TPTs as described above are arranged and a liquid crystal, and a high-density liquid crystal image display device can be obtained by switching the liquid crystal using the TPTs.

このような画像表示装置を構成するためのスイッチング
素子として用いられるTPTに要求される性能としては
、安定性、信頼性があげられる。
Stability and reliability are required performances of the TPT used as a switching element for configuring such an image display device.

しかしながら、例えば第1図に示されるような逆スタガ
ー型TPTではチャンネルを構成する非晶質シリコン半
導体層が露出しているために、前記チャンネル部に水分
等が吸着しトランジスタ特性が変動して安定な動作に支
障をきたす。このような現象を防止するためにはポリイ
ミド等の有機薄膜や窒化シリコン、酸化シリコン等の無
機薄膜等でチャンネル部を保蝕する必要がある。
However, in the case of an inverted staggered TPT as shown in FIG. 1, for example, since the amorphous silicon semiconductor layer constituting the channel is exposed, moisture etc. are adsorbed to the channel part, causing the transistor characteristics to fluctuate and become unstable. This may interfere with certain movements. In order to prevent such a phenomenon, it is necessary to protect the channel portion with an organic thin film such as polyimide or an inorganic thin film such as silicon nitride or silicon oxide.

ところが、これらの薄膜はいずれも形成時の温度が20
0C以上必要で、それ以下で形成された薄膜は劣悪で密
着性も悪く保霞膜として機能口ない。
However, all of these thin films were formed at a temperature of 20
A temperature of 0C or higher is required, and a thin film formed at a temperature lower than that is inferior and has poor adhesion and cannot function as a haze barrier film.

一方、従来のソース、ドレイン電極6.6がアルミニウ
ムであるTPTは加熱処理が行なわれるとその特性が鼻
下してしまう。第2図はTPTの主要要素であるM I
 S、 (金属−絶縁膜一半導体)構造の容量−電圧測
定の結果得られるディプレッション状態の容量値Cm 
i nとアキュムレーション状態の容量値Ciの平均値
(Dmin+Ci)/2になる時の電圧vμ(TPTの
オフ状態を示すゲート電圧値に相当する)とディプレッ
ション状態からアキ−ムレ−ジョン状態に移行するのに
要する電圧ΔV(TPTのスイッチングに必要な電圧に
相当する)とを各熱処理温度に対してプロットした結果
を示す。第1図における金属層5,6がアルミニウムの
場合、曲線I、Illで示されるように2ooC程度の
熱処理で■V2(o−o−o、 ) 、Δ■(−一−−
−)ともに大きく変化した。
On the other hand, the characteristics of a conventional TPT whose source and drain electrodes 6.6 are made of aluminum deteriorate when heat treatment is performed. Figure 2 shows the main elements of TPT.
S, capacitance value Cm in depletion state obtained as a result of capacitance-voltage measurement of (metal-insulating film-semiconductor) structure
When the voltage vμ (corresponds to the gate voltage value indicating the TPT off state) is reached when the average value of the capacitance value Ci in the accumulation state becomes (Dmin+Ci)/2, the depletion state shifts to the accumulation state. The results are shown in which the voltage ΔV (corresponding to the voltage required for TPT switching) required for this is plotted against each heat treatment temperature. When the metal layers 5 and 6 in FIG.
−) both changed significantly.

第2図の曲線I、IIlに示すような■w、ΔVの 1
変化はTPTのトレイン電流の立ち上り特性が劣化した
りTPTのスイッチオン状態とオフ状態におけるドレイ
ン電流の比(オン−オフ比)が小さくなることに関連す
る。このようにTETの特性が劣化した画像表示装置の
画質は劣悪であること (は言うまでもない。
1 of ■w, ΔV as shown in curves I and IIl in Figure 2
The change is related to a deterioration in the rise characteristics of the TPT's train current and a decrease in the ratio of the drain current in the switched-on state and the switched-off state (on-off ratio) of the TPT. It goes without saying that the image quality of an image display device with degraded TET characteristics is poor.

この原因を探るために熱処理前と熱処理後のシ シリコ
ンとアルミニウムの深さ方向の分布をオージェ電子分光
法により測定した。第3図はその結果を示し、熱処理前
(実線)に比べ200Cで1時間装処理を行なった後(
破線)では、アルミニウム(O印)とシリコン(・印)
が相互に拡散していることがわかる。このことが第1図
のソース。
To investigate the cause of this, we used Auger electron spectroscopy to measure the depth distribution of silicon and aluminum before and after heat treatment. Figure 3 shows the results. Compared to before heat treatment (solid line), after heating at 200C for 1 hour (
(dashed line), aluminum (marked with O) and silicon (marked with *)
It can be seen that they are mutually diffused. This is the source of Figure 1.

ドレイン電極5,6にアルミニウムを用いたTPTの特
性の熱処理による劣下に起因していると考えられる。
This is thought to be due to deterioration of the characteristics of TPT using aluminum for the drain electrodes 5 and 6 due to heat treatment.

以上従来のソース、ドレイン電極5.6にアルミニウム
を用いた非晶質シリコンTPTは耐熱性に劣り、ポリイ
ミド等によりTETを保護できないことから画像表示装
置を構成するためにこのTETを用いた場合安定性の面
で問題となる。
As mentioned above, the conventional amorphous silicon TPT using aluminum for the source and drain electrodes 5.6 has poor heat resistance and cannot be protected by polyimide or the like, so it is stable when used to construct an image display device. This is a problem in terms of sexuality.

このような耐熱性に関する問題点を解決するためにソー
ス、ドレイン電極を構成する金属をアルミニウムとアル
ミニウム以外の非晶質シリコン層て対して耐熱性の優れ
た金属(熱処理によりシリコン中へ拡散しない金属を意
味し、耐熱性金属と亦す)との二層構造にすることが、
たとえば本出願人の出願である特願昭67−17942
3号にて提案されている。
In order to solve this problem regarding heat resistance, the metal constituting the source and drain electrodes should be selected from aluminum and a metal other than aluminum that has excellent heat resistance (a metal that does not diffuse into the silicon during heat treatment). (meaning heat-resistant metal)
For example, patent application No. 67-17942 filed by the present applicant.
It is proposed in No. 3.

ところが、配線抵抗を下げたり基板上の段差のカバレー
ジをよくするために耐熱性金属とアルミニウムを用いる
ことは有効であるが、アルミニウムはその光反射率が約
90%と大きいために、前述の二層構造をソース、ドレ
イン電極およびそのバス配線に用いたTPTにょシ画像
表示装置を構成した場合、画像のコントラスト比が非常
に大きく劣化した。
However, although it is effective to use heat-resistant metals and aluminum to lower wiring resistance and improve coverage of steps on the board, aluminum has a high light reflectance of approximately 90%, so When a TPT image display device was constructed using a layered structure for the source and drain electrodes and their bus wiring, the contrast ratio of the image deteriorated significantly.

発明の目的 本発明はこのような問題点に鑑みなされたもので、TP
Tの耐熱温度を2ooC以上まで保証しポリイシド等に
よりTETを保論することを可能ならしめてTPT特性
の安定化を図シ、かつ良好な画像表示特性を保つために
ソース、ドレイン電極およびバス配線の反射率を低減し
たシリコンを主成分とする非単結晶半導体TPTを得ん
とするものである。
Purpose of the Invention The present invention has been made in view of the above problems.
In order to stabilize the TPT characteristics by guaranteeing the heat resistance temperature of T to 2ooC or higher and to ensure TET by using polyamide, etc., and to maintain good image display characteristics, the source, drain electrodes and bus wiring are The present invention aims to obtain a non-single-crystal semiconductor TPT whose main component is silicon and whose reflectance is reduced.

発明の構成 本発明は、シリコンを主成分とする非晶質半導体但の電
極として、半導体層に接する耐熱性金属アルミニウム金
属、低反射率金属の多層構造を用いたものである。すな
わち、耐熱性金属として+リフテン、タングステン、ク
ロム、ニクロム、タンタル、パラジウム、プラチナ、シ
リコン−金属石 化合物等を用い、低反射率金属として令すプデン。
Structure of the Invention The present invention uses a multilayer structure of a heat-resistant aluminum metal and a low reflectance metal in contact with a semiconductor layer as an electrode of an amorphous semiconductor mainly composed of silicon. That is, riften, tungsten, chromium, nichrome, tantalum, palladium, platinum, silicon-metallic compound, etc. are used as heat-resistant metals, and low reflectance metals are used.

クロム、ニクロム、シリコン−金属化合物等の光反射率
が60%以下の低反射金属を用いるのが望ましい。
It is desirable to use a low-reflection metal with a light reflectance of 60% or less, such as chromium, nichrome, or a silicon-metal compound.

実施例の説明 以下、図面を用いて本発明の詳細な説明する。Description of examples Hereinafter, the present invention will be explained in detail using the drawings.

本発明の構成は第4図に示すようにソースドレイン電極
7,8を、TPTの耐熱性向上のための半導体層に接す
る第1層7a 、8aと配線金属の反射を低減するため
の半導体層から遠い位置にある第3層7c、8cと、主
に配線抵抗を下げ、かつ配線の基板上の段差カバレージ
をよくし段差部に於ける断線率を低減するための第2層
7b、8bにアルミニウムを使用した三層構造にするも
のである。すなわち、本発明の一実施例では第4図に示
すごとく例えばソース、ドレイン電極7.8を半導体層
に接する第1層−7a 、8aおよび半導体層に対して
最も遠い位置にある第3層7c、8c第2層7b、sb
をアルミニウムにするというものである。
As shown in FIG. 4, the structure of the present invention is such that source and drain electrodes 7 and 8 are connected to first layers 7a and 8a in contact with a semiconductor layer for improving the heat resistance of TPT, and a semiconductor layer for reducing reflection of wiring metal. The third layers 7c and 8c are located far from the second layer 7c and 8c, and the second layers 7b and 8b are mainly used to lower the wiring resistance, improve the step coverage of the wiring on the substrate, and reduce the disconnection rate at the step portion. It has a three-layer structure using aluminum. That is, in one embodiment of the present invention, as shown in FIG. 4, for example, the source and drain electrodes 7.8 are placed in the first layers 7a and 8a in contact with the semiconductor layer and in the third layer 7c located farthest from the semiconductor layer. , 8c second layer 7b, sb
The idea is to use aluminum.

第6図はシリコンとクロムの深さ方向の分布を熱処理前
と3oOC91時間の熱処理後とにオージェ弟子分光法
によシ測定した結果を示すが、この図よりクロムは5o
oC,1時間熱処理されてもシリコン中へ拡散しないこ
とがわかる。従って第1層7a、8aにクロムを用いた
ことによシ、TPTの耐熱性は向上する。例えば第2図
の曲線■、■に示すように、MIS構造の容量−電圧測
定におけるVV2(さ含ム)、ΔV(、a−漬L)は各
熱処理温度対してほとんど変化していない。従ってクロ
ムをソース、ドレイン電極として用いることはTPTの
耐熱性の点で有望であるが、クロムは内部応力が大きい
ことから2000Å以上蒸着できないために、クロムの
みでソース、ドレイン電極を形成し配線することは段差
切れを生じたり配線抵抗が大きくなってしまい、電極と
しては不適当である。
Figure 6 shows the results of measuring the distribution of silicon and chromium in the depth direction before heat treatment and after heat treatment for 91 hours at 3oC using Auger Disciple spectroscopy.
It can be seen that it does not diffuse into silicon even after heat treatment at oC for 1 hour. Therefore, by using chromium in the first layers 7a and 8a, the heat resistance of TPT is improved. For example, as shown in the curves (1) and (2) in FIG. 2, VV2 (S) and ΔV (, A-L) in the capacitance-voltage measurement of the MIS structure hardly change with respect to each heat treatment temperature. Therefore, using chromium as source and drain electrodes is promising in terms of heat resistance of TPT, but because chromium has a large internal stress and cannot be deposited to a thickness of 2000 Å or more, it is necessary to form source and drain electrodes and wires using only chromium. This results in step cuts and increased wiring resistance, making it unsuitable for use as an electrode.

このことを防止するために第4図の様に第1層7a、8
aにクロムを用い、第2/脅7b、8bおよびバス配線
にアルミニウムを使用する。しかしこのま捷ではアルミ
ニウムの反射率が大きいため液晶とTPTを組合せた画
像表示装置のコントラスト比がとれず劣悪な画像となっ
てしまう。従って第4図におけるソース、ドレイン電極
7,8の第2層7b、abのアルミニウムの上に更に7
c。
In order to prevent this, first layers 7a and 8 are formed as shown in FIG.
Chromium is used for a, and aluminum is used for the second/threat 7b, 8b and the bus wiring. However, in this case, since the reflectance of aluminum is high, the contrast ratio of the image display device that combines liquid crystal and TPT cannot be maintained, resulting in poor images. Therefore, on the second layer 7b, ab of the source and drain electrodes 7 and 8 in FIG.
c.

8Cの光反射率がたとえば50%以下である金属例えば
クロムを500八被着形成する。
A metal such as chromium having a light reflectance of 50% or less of 8C is deposited.

ちなみにアルミニウムの反射率は9a%以上あるために
ソース、ドレイン電極およびバス配線にアルミニウムを
用いたTPTを利用した画像表示装置のコントラスト比
はバス配線等がない時のそれに比べ%8度である。しか
し例えばクロムの反射率が40係程度であることから、
第3層7c。
Incidentally, since the reflectance of aluminum is 9a% or more, the contrast ratio of an image display device using TPT that uses aluminum for the source, drain electrodes, and bus wiring is 8% compared to that without bus wiring. However, for example, since the reflectance of chromium is about a factor of 40,
Third layer 7c.

8Cとしてクロムが被着形成された金属層をン−ス、ド
レイン電極およびバス配線として用いたTPTより構成
された画像表示装置のコントラスト比は、アルミニウム
を配線金属として用いている場合のコントラスト比の約
4倍を得ることができ非常に有効であった。
The contrast ratio of an image display device constructed from TPT using a metal layer coated with chromium as 8C as the base, drain electrode, and bus wiring is the same as that when aluminum is used as the wiring metal. It was very effective as it was possible to obtain about 4 times the amount.

以上、三層構造のソース、ドレイン電極の第1層および
第3層をクロムで実施した場′@全代表例として説明し
たが、第1層、第3層をそれぞれモリブデン、タンタル
、タングステン、パラジウム。
Above, we have explained the case in which the first and third layers of the source and drain electrodes in the three-layer structure are made of chrome, but the first and third layers are made of molybdenum, tantalum, tungsten, palladium, respectively. .

フラf f sニッケル、クロム、ニクロム、シリコン
およびシリコン合金等とした場合でもクロムと同様の効
果が得られた。
Effects similar to those of chromium were obtained even when nickel, chromium, nichrome, silicon, and silicon alloys were used.

本発明の別の実施例では第6図に示すように、例えば前
述の第1層のクロム7a 、8aがリンを含む非晶質シ
リコン半導体層9,10を介して被着形成される。耐熱
性向上のために第1層7a。
In another embodiment of the present invention, as shown in FIG. 6, for example, the first layer of chromium 7a, 8a described above is deposited via amorphous silicon semiconductor layers 9, 10 containing phosphorus. First layer 7a for improving heat resistance.

8bに使用する金属とシリコンの間には良好なオーミッ
ク接触は得難いが不純物を含む非晶質シリコン半導体層
を介在させることは良好なオーミック接触を得るのに有
効であった。
Although it is difficult to obtain good ohmic contact between the metal used in 8b and silicon, interposing an amorphous silicon semiconductor layer containing impurities was effective in obtaining good ohmic contact.

本発明のさらに他の実施例では第7図に示すように三層
構造のソース、ドレイン電極7,8を被着形成した後に
例えばポリイミドの絶縁薄膜層11をTPTチャンネル
部に260Cで被着形成する。
In still another embodiment of the present invention, as shown in FIG. 7, after the three-layer source and drain electrodes 7 and 8 are deposited, an insulating thin film layer 11 of, for example, polyimide is deposited on the TPT channel portion at 260C. do.

260Cで被着形成されたポリイミド絶縁薄膜層は密着
性もよくまたその膜質も良好で、TPTのチャンネル部
を汚染雰囲気から十分に保護できるために、TPTの信
頼性、安定性を向上させるのに有効である。もちろんソ
ース、ドレイン電極が本発明の三層構造であることから
、260Cの工程を経ても、ソース、ドレイン電極がア
ルミニウムのTPTのように(アルミニウムの場合は2
00tl’以下の熱処理でTPT特性は劣化した)TP
T特性が劣化しないことは言うまでもない。
The polyimide insulating thin film layer deposited with 260C has good adhesion and good film quality, and can sufficiently protect the channel part of the TPT from contaminated atmosphere, so it is useful for improving the reliability and stability of the TPT. It is valid. Of course, since the source and drain electrodes have the three-layer structure of the present invention, even after going through the 260C process, the source and drain electrodes can be made of aluminum like TPT (in the case of aluminum, two layers are used).
TPT characteristics deteriorated due to heat treatment below 00tl') TP
Needless to say, the T characteristic does not deteriorate.

本発明のその他の実施例では例えばンース:ドレイン電
極の第1層のクロム7a、8aを電子ビーム蒸着法で被
着形成した後に、バス配線を含む第2層のアルミニウム
7b、ab、第3層のクロム7c 、scを電子ビーム
蒸着法により連続的に被着形成する。このように金属層
を電子ビーム蒸着法によシ被着形成すればスパッタ蒸着
法を用いた時のようなTPTに対するダメージはさけら
れ、また連続的に被着形成することによシ量産性の向□
 上につながる。
In another embodiment of the present invention, for example, after the first layer of chromium 7a, 8a of the drain electrode is deposited by electron beam evaporation, the second layer of aluminum 7b, ab, including the bus wiring, and the third layer of aluminum 7a, 8a of the drain electrode are formed. Chromium 7c and sc are continuously deposited by electron beam evaporation. If the metal layer is deposited by electron beam evaporation in this way, the damage to TPT that occurs when using sputter evaporation can be avoided, and the continuous deposition makes it easier to mass-produce. Direction□
leads to the top.

発明の効果 以上述べたように本発明では第2の金属層を三層構造に
することにより、TPTが加熱処理を受けても金属層が
シリコン中に拡散していくことなく、トランジスタ特性
が劣下しないことから、ポリイミド等の絶縁薄膜層によ
るTPTの保護を行なうことができるためにTPTの信
頼性、安定性を向上させる効果を有する。またソース、
ドレインおよびバス配線金属からの光の反射を低減する
効果を有すし、これを用いた画像表示装置は非常に安定
で良好な画質を示す。以上非晶質シリコン半導体を代表
例として述べたが、これに限るものではなく本発明はシ
リコンを主成分とする非単結晶半導体すべてに適用でき
ることは言うまでもない。
Effects of the Invention As described above, in the present invention, by forming the second metal layer into a three-layer structure, even when TPT is subjected to heat treatment, the metal layer does not diffuse into silicon, and the transistor characteristics are reduced. Since the TPT does not deteriorate, the TPT can be protected by an insulating thin film layer such as polyimide, which has the effect of improving the reliability and stability of the TPT. Also sauce,
It has the effect of reducing the reflection of light from the drain and bus wiring metals, and image display devices using it exhibit very stable and good image quality. Although the amorphous silicon semiconductor has been described above as a representative example, it goes without saying that the present invention is not limited to this and can be applied to all non-single crystal semiconductors whose main component is silicon.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は非晶質シリコン車導体薄膜電界効果トエ ランジスタの構造断面図、第2図はM4.8構造の容量
−電圧測定におけるΔV 、 V、の熱処理温度に対す
る変化を示す図、第31図および第6図はオージェ電子
分光法による測定結果を示す図、第4図、第6図および
第7図は本発明のす実施例のTPTの概略構造断面図で
ある。 1・・・・・・基板、2・・・・・・ゲート金属、3・
・・・・・ゲート絶縁膜、4・・・・・・非晶質シリコ
ン、5,6,7.8・・・・・・ソース、ドレイン電極
、7a 、8a 、7c 。 8C・・・・・・クロム、7b、8b・・・・・・アル
ミニウム、9.10・・・・・・リンを含む非晶質シリ
コン、11・・・・・・ポリイミド。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第2
図 憔双理JL度(・C) 第3図 スハ゛・ソゲB今几ゴ (永ン 第4図 ? 第5図 スフ1゜ツタ侍閣(例 第6図 ど 第7図
Fig. 1 is a cross-sectional view of the structure of an amorphous silicon conductor thin film field effect transistor, Fig. 2 is a diagram showing changes in ΔV and V with respect to heat treatment temperature in capacitance-voltage measurement of an M4.8 structure, Fig. 31, and FIG. 6 is a diagram showing measurement results by Auger electron spectroscopy, and FIGS. 4, 6, and 7 are schematic cross-sectional views of a TPT according to an embodiment of the present invention. 1...Substrate, 2...Gate metal, 3.
...Gate insulating film, 4...Amorphous silicon, 5, 6, 7.8... Source, drain electrode, 7a, 8a, 7c. 8C...Chromium, 7b, 8b...Aluminum, 9.10...Amorphous silicon containing phosphorus, 11...Polyimide. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 3 Suha Sogae B now 几go (Engine Figure 4?

Claims (4)

【特許請求の範囲】[Claims] (1)基板の一主面上に第1の金属層が・選択的に被着
形成され、絶縁薄膜層を介してシリコンを主成分とする
非単結晶半導体層が前記第1の金属層と一部重シ合う様
に形成され、第2の金属層が前記半導体層と一部重シ合
う様に被着形成され、前記第2の金属層が多層構造を有
し、更に前記第2の金属層が主にアルミニウム層から成
ると共に前記半導体層と接する領域に耐熱性金属層を配
置しかつ前記アルミニウム層の前記耐熱性金属層に接し
ていない側に低反射率金属を配置した多層構造であるこ
とを特徴とする薄膜電界効果トランジスタ。
(1) A first metal layer is selectively deposited on one main surface of the substrate, and a non-single-crystal semiconductor layer mainly composed of silicon is connected to the first metal layer via an insulating thin film layer. a second metal layer is formed so as to partially overlap the semiconductor layer, the second metal layer has a multilayer structure, and the second metal layer is formed so as to partially overlap the semiconductor layer; A multilayer structure in which the metal layer mainly consists of an aluminum layer, a heat-resistant metal layer is arranged in a region in contact with the semiconductor layer, and a low reflectance metal is arranged in a side of the aluminum layer that is not in contact with the heat-resistant metal layer. A thin film field effect transistor characterized by the following.
(2)多層構造を有する第2金属層と非単結晶半導体層
とが不純物を含むシリコンを主成分とする第2の非単結
晶半導体層を介して被着形成されるこ。 とを特徴とする特許請求の範囲第1項記載の薄膜電界効
果トランジスタ。
(2) A second metal layer having a multilayer structure and a non-single-crystal semiconductor layer are deposited via a second non-single-crystal semiconductor layer whose main component is silicon containing impurities. A thin film field effect transistor according to claim 1, characterized in that:
(3)薄膜電界効果トランジスタの一部または全部が絶
縁薄膜で保護されることを特徴とする特許請求の範囲第
1項記載の薄膜電界効果トランジスタ。 ミ
(3) The thin film field effect transistor according to claim 1, wherein part or all of the thin film field effect transistor is protected by an insulating thin film. Mi
(4)絶縁薄膜がボリイヤド、窒化シリコン、酸化シリ
コンのいずれかであることを特徴とし、前記絶縁薄膜が
200C以上で形成されてなる特許請求の範囲第3項記
載の薄膜電界効果トランジスタ。 (6ン 多層構造の第2の金属層の内少なくとも2つの
金属層が電子ビーム蒸着法で連続的に形成されてなる特
許請求の範囲第1項記載の薄膜電界効果 ′トランジス
タ。
(4) The thin film field effect transistor according to claim 3, wherein the insulating thin film is made of bolyard, silicon nitride, or silicon oxide, and the insulating thin film is formed at a temperature of 200C or higher. (6) The thin film field effect transistor according to claim 1, wherein at least two metal layers of the second metal layer of the multilayer structure are successively formed by electron beam evaporation.
JP58120508A 1983-07-01 1983-07-01 Thin film field effect transistor Granted JPS6012770A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58120508A JPS6012770A (en) 1983-07-01 1983-07-01 Thin film field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58120508A JPS6012770A (en) 1983-07-01 1983-07-01 Thin film field effect transistor

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP22876195A Division JP2636815B2 (en) 1995-09-06 1995-09-06 Transmissive liquid crystal display

Publications (2)

Publication Number Publication Date
JPS6012770A true JPS6012770A (en) 1985-01-23
JPH0546107B2 JPH0546107B2 (en) 1993-07-13

Family

ID=14787938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58120508A Granted JPS6012770A (en) 1983-07-01 1983-07-01 Thin film field effect transistor

Country Status (1)

Country Link
JP (1) JPS6012770A (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63287052A (en) * 1987-05-19 1988-11-24 Nec Corp Semiconductor integrated circuit device
JPH01228175A (en) * 1988-03-08 1989-09-12 Fujitsu Ltd Thin film transistor matrix
JPH01283517A (en) * 1988-05-10 1989-11-15 Matsushita Electric Ind Co Ltd Semiconductor device for matrix type image display device and its manufacture
US5065202A (en) * 1988-02-26 1991-11-12 Seikosha Co., Ltd. Amorphous silicon thin film transistor array substrate and method for producing the same
US5071779A (en) * 1988-07-13 1991-12-10 Seikosha Co., Ltd. Method for producing a silicon thin film transistor
US5075674A (en) * 1987-11-19 1991-12-24 Sharp Kabushiki Kaisha Active matrix substrate for liquid crystal display
US5153754A (en) * 1989-06-30 1992-10-06 General Electric Company Multi-layer address lines for amorphous silicon liquid crystal display devices
JPH06177388A (en) * 1992-12-04 1994-06-24 Toshiba Corp Semiconductor integrated circuit
US5366912A (en) * 1988-09-21 1994-11-22 Fuji Xerox Co., Ltd. Fabrication method of thin-film transistor
JP2007273545A (en) * 2006-03-30 2007-10-18 Fujitsu Ltd Semiconductor device and its manufacturing method
JP2013254931A (en) * 2012-06-05 2013-12-19 Samsung Display Co Ltd Thin film transistor substrate
CN108172629A (en) * 2017-12-22 2018-06-15 信利(惠州)智能显示有限公司 Low-temperature polysilicon film transistor and preparation method thereof and display device
WO2020170925A1 (en) * 2019-02-21 2020-08-27 東レ株式会社 Field-effect transistor, method for manufacturing same, and wireless communication device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5272570A (en) * 1975-12-15 1977-06-17 Fujitsu Ltd Formation of electrode of semiconductor deviced
JPS5683782A (en) * 1979-12-11 1981-07-08 Tokyo Shibaura Electric Co Liquid crystal matrix device
JPS56161670A (en) * 1980-05-16 1981-12-12 Hitachi Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5272570A (en) * 1975-12-15 1977-06-17 Fujitsu Ltd Formation of electrode of semiconductor deviced
JPS5683782A (en) * 1979-12-11 1981-07-08 Tokyo Shibaura Electric Co Liquid crystal matrix device
JPS56161670A (en) * 1980-05-16 1981-12-12 Hitachi Ltd Semiconductor device

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63287052A (en) * 1987-05-19 1988-11-24 Nec Corp Semiconductor integrated circuit device
US5075674A (en) * 1987-11-19 1991-12-24 Sharp Kabushiki Kaisha Active matrix substrate for liquid crystal display
US5065202A (en) * 1988-02-26 1991-11-12 Seikosha Co., Ltd. Amorphous silicon thin film transistor array substrate and method for producing the same
JPH01228175A (en) * 1988-03-08 1989-09-12 Fujitsu Ltd Thin film transistor matrix
JPH01283517A (en) * 1988-05-10 1989-11-15 Matsushita Electric Ind Co Ltd Semiconductor device for matrix type image display device and its manufacture
US5071779A (en) * 1988-07-13 1991-12-10 Seikosha Co., Ltd. Method for producing a silicon thin film transistor
US5366912A (en) * 1988-09-21 1994-11-22 Fuji Xerox Co., Ltd. Fabrication method of thin-film transistor
US5153754A (en) * 1989-06-30 1992-10-06 General Electric Company Multi-layer address lines for amorphous silicon liquid crystal display devices
JPH06177388A (en) * 1992-12-04 1994-06-24 Toshiba Corp Semiconductor integrated circuit
JP2007273545A (en) * 2006-03-30 2007-10-18 Fujitsu Ltd Semiconductor device and its manufacturing method
US8222672B2 (en) 2006-03-30 2012-07-17 Fujitsu Limited Semiconductor device and manufacturing method thereof
JP2013254931A (en) * 2012-06-05 2013-12-19 Samsung Display Co Ltd Thin film transistor substrate
CN108172629A (en) * 2017-12-22 2018-06-15 信利(惠州)智能显示有限公司 Low-temperature polysilicon film transistor and preparation method thereof and display device
WO2020170925A1 (en) * 2019-02-21 2020-08-27 東レ株式会社 Field-effect transistor, method for manufacturing same, and wireless communication device
JP6809645B1 (en) * 2019-02-21 2021-01-06 東レ株式会社 Field-effect transistor, its manufacturing method, and wireless communication equipment using it
US11711929B2 (en) 2019-02-21 2023-07-25 Toray Industries, Inc. Field-effect transistor, method for manufacturing same, and wireless communication device

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