JP3430097B2 - Method of manufacturing thin film transistor array substrate - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor array substrate, and more particularly, an ITO which is a transparent conductive film.
(Abbreviated name of Indium Tin Oxide.
A silicon nitride film (SiN) is formed on the wiring including the TO.
x) relates to a manufacturing process for depositing a protective insulating film.

[0002]

2. Description of the Related Art It has been conventionally known that there is a problem that abnormal etching occurs at the interface between an ITO film and a SiNx film.

In order to prevent this abnormal etching, as a first conventional example, a method of controlling the deposition rate of a SiNx film is disclosed in Japanese Patent Laid-Open No. 10-41022. In this document, an insulating film made of a SiNx film is formed on ITO by a plasma CVD method, and in a method for manufacturing a TFT array substrate having an opening formed in the insulating film by etching, the SiNx film is formed by a plasma CVD method. It is characterized in that the upper layer film is formed at a speed higher than that of the lower layer film by performing it at 10 nm / min to 50 nm / min.

In the horizontal electric field type liquid crystal display device,
In the structure of the comb-teeth-shaped common electrode and the pixel electrode that generate the lateral electric field, when a SiNx film equivalent to that of the TN liquid crystal display device is formed, light leakage mainly occurs from the pixel electrode portion,
Black brightness deteriorates.

This is because there is a correlation between the step coverage of the insulating film on the pixel electrode and the orientation of the liquid crystal. If the coverage shape is poor, the orientation will be poor, and light will leak from the pixel electrode portion.

In order to solve this, for example, a method of etching the pixel electrode in a tapered shape can be considered, but it is difficult to obtain pattern accuracy and controllability of the process is poor.

Therefore, as a second conventional example, when a SiNx film as a passivation film is formed to be thick, a black luminance with no light leakage is obtained regardless of the etching shape of the pixel electrode (taper shape to vertical shape). A stable liquid crystal display device was obtained.

[0008]

However, as in the case of the above-mentioned first conventional example, the film formation rate is controlled so that SiH ₄
It was found that when the flow rate ratio of / NH ₃ is changed to increase the ratio, abnormal etching occurs at the interface.

Further, if the SiNx film as the passivation film is thickened as in the second conventional example, a new problem arises that the film stress causes frequent disconnection of the drain wiring despite the redundant wiring with the ITO. did.

It is an object of the present invention to manufacture a thin film transistor array substrate, particularly in a manufacturing process in which a protective insulating film made of a silicon nitride film (SiNx) is deposited on a wiring containing ITO which is a transparent conductive film. An object of the present invention is to provide a method of manufacturing a thin film transistor array substrate, which can prevent abnormal etching with a nitride film (SiNx) and reduce disconnection of wiring.

[0011]

A first method of manufacturing a thin film transistor array substrate according to the present invention is an ITO (Indiu) method.
(m Tin Oxide) film is formed on the substrate, and a protective insulating film made of a silicon nitride film (SiNx) is deposited on the substrate including the wiring.
A predetermined area of the protective insulating film is removed to allow the transparent insulating film to pass through the transparent insulating film.
A method of manufacturing a thin film transistor array substrate comprising at least a manufacturing step of forming an opening for exposing a bright conductive film , wherein at least a portion of the protective insulating film, which is in contact with a surface of the wiring, is the silicon nitride film. When the number of atoms in which a silicon atom that constitutes the nitride film is bonded to a hydrogen atom is represented by Si-H and the number of atoms in which a nitrogen atom is bonded to a hydrogen atom is represented by N-H, respectively, Si-H of N-H
In the first application mode of the first manufacturing method, the protective insulating film is a single-layer silicon layer composed of one layer. The single-layer silicon nitride film is formed by depositing a nitride film, and the single-layer silicon nitride film is formed to have a film quality such that NH / Si-H is 5 or more. It is to be deposited.

According to a second application mode of the first manufacturing method, the protective insulating film is a laminated silicon nitride film formed by sequentially depositing two or more layers of silicon nitride films. The lower silicon nitride film forming the first layer of the film is formed to have a film quality such that N—H / Si—H is 5 or more.
The upper silicon nitride film formed of the silicon nitride film above the second layer has an absolute film stress of 0.3 GPa (0.3
The thickness of the lower silicon nitride film is not more than × 10 ⁹ Pa), and the lower silicon nitride film is deposited to a film thickness of 200 nm or less.

Next, in a second method of manufacturing a thin film transistor array substrate of the present invention, a wiring made of an ITO film is formed above the substrate, and a silicon nitride film (SiNx) is made on the substrate including the wiring. Protective insulation film is deposited and
Before removing the specified area of the protective insulation film,
A method of manufacturing a thin film transistor array substrate comprising at least a manufacturing step of forming an opening exposing a transparent conductive film , wherein the protective insulating film is formed by subjecting the surface of the substrate including the wiring to a nitrogen plasma treatment before its deposition. The silicon nitride film, which is deposited later and is in contact with the surface of the wiring in at least the protective insulating film, has the number of atoms in which silicon atoms forming the silicon nitride film are combined with hydrogen atoms as Si-H and nitrogen atoms. Represents the number of atoms bonded to hydrogen atoms as N-H, and the film quality should be such that N-H / Si-H, which is the ratio of N-H to Si-H, is 3.5 or more. In the first application mode of the second manufacturing method, the protective insulating film is formed by depositing a single-layer silicon nitride film consisting of one layer, and the single-layer silicon nitride film is N H / Si-H is formed on the film quality becomes 3.5 or more, the film thickness of the single-layer silicon nitride film 300n
The film is deposited to a film thickness of m or less.

In a second application mode of the second manufacturing method, the protective insulating film is a laminated silicon nitride film formed by sequentially depositing two or more layers of silicon nitride films. The lower silicon nitride film forming the first layer of the film is formed to have a film quality such that N—H / Si—H is 3.5 or more, and above the second layer of the laminated silicon nitride film. The upper silicon nitride film formed of the silicon nitride film has an absolute film stress of 0.3 GPa.
It is formed to (0.3 × 10 ⁹ Pa) or less and the lower silicon nitride film is deposited to a film thickness of 300 nm or less.

In the second application mode of the first and second manufacturing methods, the laminated silicon nitride film is 400 nm thick.
At least the lower silicon nitride film is deposited by the plasma CVD method, or all the silicon nitride films forming the laminated silicon nitride film are deposited by the plasma CVD method. Particularly, in the latter case, the laminated silicon nitride films are all deposited in the same chamber.

Furthermore, the thin film transistor array substrate obtained by the second application mode of the first and second manufacturing methods is used for a lateral electric field type liquid crystal display device.

Finally, in the first and second manufacturing methods, after a step of depositing a protective insulating film made of a silicon nitride film on the substrate including the wiring, a predetermined region of the protective insulating film is formed. There is a step of forming an opening in the protective insulating film by removing, a predetermined region of the protective insulating film is removed by wet etching using buffered hydrofluoric acid, At least the transparent conductive film may be exposed in the opening.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Before describing the embodiments of the present invention, the features of the present invention will be briefly described.

In order to solve the problem of the first conventional example already described in the section of the prior art, S forming an interface with ITO is used.
As a result of measuring the film quality of the iNx film by FT-IR, N-H /
It was found that the formation can be prevented by forming a film having Si-H of 5 or more. This can solve the abnormal etching of the SiNx film on the ITO in the TN type liquid crystal display device.

To solve the problem of the second conventional example,
SiNx as a passivation film has a two-layer structure, and the first layer is a film with N-H / Si-H≥5 nm of 50 nm.
When a 350 nm SiNx film having an absolute stress value of 0.3 GPa or less was formed on the second layer, disconnection of the drain wiring could be made equal to that of the TN liquid crystal display device. . Here, when only the second-layer SiNx film was used, it was confirmed that abnormal etching occurred, for example, in SiNx on the ITO of the terminal portion.

In the above, further, by performing N ₂ plasma treatment before forming the SiNx film on the ITO film, it is possible to form a film satisfying N−H / Si—H ≧ 3.5. It was found that there is an effect that can suppress. By performing the N ₂ plasma treatment, there is also a secondary effect that the off current of the transistor can be suppressed.

Next, a plan view and a circuit diagram in the vicinity of a thin film transistor common to the embodiments of the present invention will be described with reference to the drawings.

First, the thin film transistor array of the present invention will be described with reference to FIGS. 12 (plan view) and 13 (circuit diagram).

In FIG. 13, a gate terminal 370 and a drain terminal 380 are provided on the transparent insulating substrate 301, and a gate bus line 374 and a drain bus line 379 are led out to the respective terminals. The gate bus line 374 is connected to the gate electrode as the gate wiring 333. Further, the drain bus line 379 is orthogonal to the gate bus line 374 and is connected to the drain electrode 339 as the drain wiring 369. In addition, the common electrode 302,
The common wiring 332 is formed, and the thin film transistor 320 is formed near each intersection of the gate wiring 333 and the drain wiring 369.
Are formed.

In FIG. 12, the pixel portion is provided with a comb-teeth-shaped common electrode 302 and a comb-teeth-shaped pixel electrode 308 to generate a lateral electric field to drive the liquid crystal.

Next, a first embodiment of the present invention will be described with reference to FIGS.
Follow the instructions below. FIG. 1 is a sectional structure of a TFT of the present invention, FIG. 2 is a detailed sectional structure, and FIG. 3 is an example of the terminal structure.

The gate electrode 10 is formed on the transparent insulating substrate 101.
As a gate wiring also serving as 3 and a common wiring also serving as the common electrode 102, Mo is deposited to a thickness of 300 nm by sputtering,
Patterning is performed by a photoresist process. next,
Using plasma CVD, the gate insulating film 104 made of SiNx is 400 nm, and the semiconductor film 105 (hereinafter, abbreviated as a-Si of amorphous silicon is used as 200 n).
m, the ohmic contact layer 106 (hereinafter, using abbreviations n ⁺ a-Si in the n ⁺ amorphous silicon) and 30n
m, continuous film formation, and then an isolated island pattern is formed by a photoresist process (FIG. 1A). Further, the first contact hole 107 is continuously formed by a photoresist process (see FIG. 3).

Next, as the source / drain electrodes 109 and the pixel electrodes 108, 200 nm of Cr is formed by sputtering.
A film is formed and patterning is performed by a photoresist process. Next, in order to provide the drain wiring with redundancy and to obtain good conduction with the external driver at the terminal portion, a film of ITO 110 having a thickness of 50 nm is formed by sputtering and a predetermined pattern is obtained by a photoresist process (see FIG. )).

Next, using the source / drain electrodes 109 as a mask, a dry etching apparatus is used to remove the n ⁺ a-Si 106 in the channel portion to form the channel 111.

Next, two layers of SiNx films 112 and 113 having a thickness of 400 nm are formed as a passivation film for protecting the channel portion. Here, the lower first SiNx film 1
12 has a flow rate ratio of SiH ₄ , NH ₃ , and N ₂ of 1/4, for example.
/ 20, pressure 200 Pa, RF power 2000 W, film with NH / Si-H ratio of 5 and stress of 1.0 GPa at deposition rate of about 100 nm / min.
The upper second SiNx film 113 is formed to a film thickness of 0 nm, and for example, the flow rate ratio of SiH ₄ , NH ₃ , and N ₂ is 1/4/10 and the pressure is 2.
N / H / S under the condition of 00 Pa and RF power 1500 W
A film having an i-H ratio of 2 and a stress of 0.3 GPa was deposited to 350 nm at a deposition rate of about 230 nm / min.

As a result, the step coverage shape of the pixel electrode 108 is improved as shown in FIG.

Finally, the step of forming the second contact hole 114 for exposing the terminal is performed as shown in FIG. Here, the contact hole is formed by wet etching using a chemical solution containing HF (hydrofluoric acid) as a main component. Through the above steps, the target thin film transistor array is obtained.

Here, the cross-sectional structure of the gate terminal and the drain terminal is as shown in FIG. 3 (a), and both of them have a structure in which the oxidation resistant ITO 110 is the uppermost layer.

Regarding the gate terminal, the terminal structure is such that the first contact hole 107 is first formed in the gate insulating film 104 covering the gate wiring 133, and then the first contact hole is made of the same metal as the source / drain wiring 139. 1
07 is completely covered, and a second passivation film is formed on it.
The contact hole 114 is formed.

On the other hand, in the terminal structure of the drain terminal, only the second contact hole 114 is formed in the passivation film on the source / drain wiring 139.

3B and 3C are enlarged views of the cross-sectional structures of the gate terminal and the drain terminal, respectively.

Here, in this embodiment, Cr is deposited as the source / drain electrodes 109 and the source / drain wiring 139, and then the drain wiring is provided with redundancy, and good conduction with the external driver is obtained at the terminal portion. Therefore, although the ITO film is formed by sputtering, the steps may be reversed, and the ITO film may be first formed on the base and the Cr film may be formed on the ITO film in this order. At this time, the terminal portion needs to remove Cr on the ITO in the opening (not shown).

Regarding the terminal structure, when a metal having a weak corrosion resistance is used as the wiring material, the IT is formed in the opening.
It is also possible to adopt a structure in which only O is provided and the gate wiring and drain wiring materials are not placed in the terminal openings (not shown). The wiring metal material is not limited to this embodiment.

The characteristics of the thin film transistor array substrate obtained as described above will be described in comparison with conventional problems.

In the lateral electric field drive type liquid crystal display device, first, the relationship between the black luminance, the rate of occurrence of wire breakage, and the SiNx film thickness is shown in FIG. In the structure of the comb-teeth-shaped common electrode and the pixel electrode that generate a lateral electric field, when a SiNx film equivalent to that of a TN liquid crystal display device is formed, light leakage mainly occurs from the pixel electrode portion, and the black brightness deteriorates. To do. This is because there is a correlation between the step coverage of the insulating film on the pixel electrode and the orientation of the liquid crystal, and if the coverage shape is poor, the orientation is also poor, and light leaks from the pixel electrode portion (see FIGS. 4 and 5).

In order to solve this, for example, a method of etching the pixel electrode in a tapered shape can be considered, but it is difficult to obtain pattern accuracy and the process controllability is poor.
Therefore, there is a problem that the brightness of the panel varies.

Therefore, Si as a passivation film is used.
When the Nx film is formed thickly, the liquid crystal display device has stable black luminance without light leakage regardless of the etching shape of the pixel electrode (even if the cross-sectional shape of the pixel electrode is changed from the tapered shape to the vertical shape). was gotten.

However, S as a passivation film
When the iNx film is particularly thickened to 400 nm or more, a new problem arises that the film stress causes frequent disconnection of the drain wiring despite the redundant wiring with the ITO.

Therefore, SiN is used as a passivation film.
x has a two-layer structure, the first layer has a film of N-H / Si-H≥5 having a thickness of 50 nm, and the second layer has a SiNx film having an absolute stress value of 0.3 GPa or less having a thickness of 350 nm. When the film was formed, the occurrence rate of disconnection could be made equal to that of the TN type liquid crystal display device. No abnormal etching was observed at the interface between ITO and SiNx.

Next, the passivation film thickness of 40 is shown in FIG.
The relation between the film thickness of the first layer SiNx and the rate of occurrence of disconnection of the drain wiring when the thickness is set to 0 nm is shown. As can be seen from this, the wire breakage occurrence rate is good up to the first SiNx film thickness of 200 nm, but the wire breakage occurrence rate increases from around 300 nm. Therefore, the first SiNx film thickness is 200 nm
The following is preferable (the film thickness of the first SiNx film needs to be 5 nm or more because there is a stabilization time of discharge in plasma CVD).

In order to find the present conditions, parameters such as the gas flow rate are kept constant, and the film characteristics (hydrogen bond number ratio, film stress, 1% HF etching rate and single film of the first SiNx film) when the RF power is changed. At a film thickness of 400 nm
The etching shape on the TO) is shown in FIG. As can be seen from the above, with respect to the RF power, by increasing the RF power, the film stress in the compression direction increases, and along with this, the 1% HF etching rate decreases, and the hydrogen bond number ratio (NH / Si-H). It can be seen that when a film having a hydrogen bond number ratio of about 5 or more is used, an abnormal etching shape at the time of wet etching at the interface between ITO and SiNx can be prevented. Although not particularly shown, it was confirmed that the film quality can be controlled by changing the flow rate ratio of the SiH ₄ gas and the NH ₃ gas used for forming the SiNx film, and the same result can be obtained.

Next, a second embodiment of the present invention will be described. The drawings are the same as those of the first embodiment except the method of manufacturing a passivation film, and therefore the drawings are the same as those of the first embodiment. 3 will be used again to explain.

The gate electrode 10 is formed on the transparent insulating substrate 101.
3, as the gate wiring 133 and the common electrode 102, Mo
Is formed by sputtering to a thickness of 300 nm and patterned by a photoresist process. Next, plasma CVD is used to form the gate insulating film 104 with a thickness of 400 nm and a-Si10.
5 and 200 nm and n ⁺ a-Si 106 of 30 nm are continuously formed, and then an isolated island pattern is formed by a photoresist process. Further, the first contact hole 107 is continuously formed by a photoresist process. Next, the source / drain electrode 109 and the source / drain wiring 1
39 and 2 as Cr for the pixel electrode 108 by sputtering
A film having a thickness of 00 nm is formed and patterned by a photoresist process.

Next, in order to make the drain wiring redundant and to obtain good conduction with the external driver at the terminal portion,
A film of ITO 110 having a thickness of 50 nm is formed by sputtering, and a predetermined pattern is obtained by a photoresist process.

Next, using the dry etching apparatus with the source / drain electrodes 109 as a mask, the n ⁺ a-Si 106 is selectively removed to form the channel 111.

Next, although this is different from the first embodiment, two layers of the first SiNx film 112 and the second Si are used as a passivation film for protecting the channel 111.
Before forming the Nx film 113, N in the same device as the device for forming the SiNx film (preferably in the same chamber).
₂ Perform plasma treatment. In this process, nitrogen adheres to the surface of the substrate, forming a very N-rich SiNx at the interface between ITO and SiNx.

The conditions at this time are, for example, N ₂ flow rate 9 L /
30 min at a pressure of 200 Pa and an RF power of 1000 w
Process for seconds.

Next, a first SiNx film 112 and a second SiN film are formed as a passivation film for protecting the channel portion.
The x film 113 is formed to a total thickness of 400 nm.

Here, the first SiNx film 112 is made of Si.
The flow rate ratio of H ₄ , NH ₃ and N ₂ is 1/4/20 and the pressure is 200.
N / H / Si-under conditions of Pa and RF power of 2000W
A film having an H ratio of 5 and a stress of 1.0 GPa is formed to a thickness of 50 nm at a deposition rate of about 100 nm / min.
The iNx film 113 has a flow rate ratio of SiH ₄ , NH ₃ , and N ₂ of 1 /
A film having an NH / Si-H ratio of 2 and a stress of 0.3 GPa was deposited to 350 nm at a deposition rate of about 230 nm / min under the conditions of 4/10, pressure of 200 Pa, and RF power of 1500 W.

Finally, a step of forming the second contact hole 114 for exposing the terminal is performed. 1st Si on ITO
A film forming flow of the Nx film 112 and the second SiNx film 113 is shown in FIG. 9 (formed by focusing on the gas flow rate of N ₂ and the RF power).

Here, the second contact hole 114 is formed by wet etching with a chemical solution containing HF as a main component. As a result, the target transistor is obtained.

Here, the SiNx film was formed under the same conditions as in the first embodiment except for the N ₂ plasma treatment, but the hydrogen bond ratio of the first SiNx film 112 and the ITO in the step of forming the second contact hole 114. Looking at the relationship of the etching shape of the upper SiNx film (film thickness 400 nm),
The relationship as shown in FIG. 10 is obtained, and the NH / Si-H ratio ≧
It was found that the same result as in the first embodiment was obtained with a film satisfying 3.5, and further improvement (expansion of process margin) was achieved.

Further, the first SiNx film 11 when the passivation film thickness is 400 nm as in the first embodiment.
When the relationship between the film thickness of 2 and the disconnection occurrence rate of the drain wiring is examined, the disconnection occurrence rate is good up to a film thickness of the first SiNx film 112 of 300 nm, but the disconnection occurrence rate increases near 400 nm. Therefore, the first SiNx film 112
The film thickness of is preferably 300 nm or less (not shown).

In addition, although the present embodiment describes a channel engraving type transistor, in this case, since a channel-etched interface is exposed to N ₂ plasma, a plasma damage layer is formed at the interface, As shown in FIG. 11, there is also a secondary effect that the Ioff characteristic of the transistor is improved (leakage current can be reduced).

In the first and second embodiments, the case where the passivation film has a two-layer structure and the example is applied to the thin film transistor array substrate for the lateral electric field type liquid crystal display device is described. However, the passivation film is a single layer. It may be three or more layers.

Needless to say, it can be applied to a thin film transistor array substrate for a TN type liquid crystal display device.

In the above embodiments, the two-layer structure of SiNx has been described as the passivation film, but when the present invention is applied to a passivation structure other than this structure, it is as follows.

First, when the passivation film is a single film,
On the thin film transistor array substrate for liquid crystal display
The passivation film is a SiNx film, and its hydrogen
The bond number ratio is N-H / Si-H≥5, and SiN
The film thickness of x is 200 nm or less (N ₂Use plasma treatment
And 300 nm or less), there is no problem of yield.
A transistor array can be obtained.

Here, in the case of the lateral electric field type thin film transistor array, light leakage occurs from the pixel electrode as described in the effect, so that it can be applied to a thin film transistor array other than the lateral electric field type (TN type). (Not shown).

Next, when the passivation film has three or more layers, a passivation film having a thickness of 400 nm is formed. Here, the first SiNx film has a flow rate ratio of SiH ₄ , NH ₃ , and N ₂ of 1/4/20, a pressure of 200 Pa, and an RF power of 2000 W.
N / H / Si-H ratio is 5 and stress is 1.0 GP
deposition rate of about 100 nm / min
With a thickness of 50 nm, and the second SiNx film is formed with SiH ₄ , NH ₃ ,
A deposition rate of about 23 is applied to a film having an N-H / Si-H ratio of 2 and a stress of 0.3 GPa under the condition that the flow rate ratio of N ₂ is 1/4/10, the pressure is 200 Pa, and the RF power is 1500 W.
300nm film is formed at 0nm / min, and the third SiN
The x film is NH under the conditions that the flow rate ratio of SiH ₄ , NH ₃ and N ₂ is 1/4/5, the pressure is 200 Pa, and the RF power is 1500 W.
By forming a film having a / Si-H ratio of 1.5 and a stress of 0.1 GPa at a deposition rate of about 150 nm / min to a thickness of 50 nm, a thin film transistor array with no yield problem can be obtained (not shown).

Finally, in the case of stacking SiNx films to form a passivation film in the above-described embodiment and its modification, the lowest SiNx film is deposited at least by plasma CVD, and the hydrogen bond number ratio of the SiNx film is increased. Is N-H / Si-H≥5, or N-H / Si-H≥
It suffices that the thickness be 3.5, and the deposition of the SiNx film above that is not limited to plasma CVD. Further, when all SiNx films are deposited by plasma CVD to form a passivation film, the deposition work can be performed in the same chamber of the same plasma CVD apparatus, which is extremely effective in terms of production efficiency.

[0067]

As described above, according to the method of manufacturing the thin film transistor array substrate of the present invention, the SiNx film as the passivation film has an N--H / Si--H ratio of 5 or more, or after the N2 plasma treatment. N on the SiNx film
By forming a SiNx film having a -H / Si-H ratio of 3.5 or more, it is possible to prevent abnormal etching of the SiNx film / ITO interface, especially in a structure having ITO as a base of the SiNx film, The effect that the disconnection of the wiring covered with the film can be reduced is exhibited.

[Brief description of drawings]

FIG. 1 is a sectional view showing a manufacturing method according to first and second embodiments of the present invention in the order of manufacturing steps.

FIG. 2 is a cross-sectional view showing a coverage state of a passivation film of a thin film transistor array substrate obtained by the manufacturing method according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of a terminal portion of the thin film transistor array substrate obtained by the manufacturing method according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a method of manufacturing a conventional thin film transistor array substrate in the order of manufacturing steps.

FIG. 5 is a cross-sectional view showing a coverage state of a passivation film of a conventional thin film transistor array substrate.

FIG. 6 is a graph showing the dependency of the black luminance and the occurrence rate of drain wire disconnection on the SiNx film thickness for explaining the effect of the first embodiment of the present invention.

FIG. 7 is an RF power dependence of SiNx film stress, HF etching rate, SiNx film etching shape, N—H / Si—H bond number ratio, and wire breakage occurrence ratio for explaining the effect of the first embodiment of the present invention. It is a graph which shows sex.

FIG. 8 is a graph showing the dependency of the drain disconnection occurrence rate on the first SiNx film thickness for explaining the effect of the first embodiment of the present invention.

FIG. 9 is a process chart during SiNx film formation for explaining the manufacturing method according to the second embodiment of the present invention.

FIG. 10 is a NH-Si-H bond number ratio, a wire breakage occurrence rate, and SiNx for explaining effects of the second embodiment of the present invention.
It is a graph which shows RF power dependence of a film etching shape.

FIG. 11 is a graph showing transistor characteristics for explaining the effect of the second embodiment of the present invention.

FIG. 12 is a plan view of a thin film transistor array substrate common to the embodiments of the present invention.

FIG. 13 is a circuit diagram of a thin film transistor array substrate common to the embodiments of the present invention.

[Explanation of symbols]

101, 201, 301 transparent insulating substrate 102, 202, 302 common electrode 103, 203 gate electrode 104, 204 gate insulating film 105, 205 a-Si 106, 206 n ⁺ a-Si 107 first contact hole 108, 208, 308 pixel electrode 109, 209 source / drain electrode 110, 210 ITO 111, 211 channel 112 first SiNx film 113 second SiNx film 114 second contact hole 133, 333 gate wiring 139 source / drain wiring 242 SiNx film 305 semiconductor layer 309 source electrode 320 thin film transistor 330 liquid crystal layer 332 common wiring 339 drain electrode 369 drain wiring 370 gate terminal 374 gate bus line 379 drain bus line 380 drain terminal

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-3-34465 (JP, A) JP-A-8-43853 (JP, A) JP-A-6-95145 (JP, A) JP-A-10- 260431 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G02F 1/1368 G02F 1/1333 505 H01L 21/318 H01L 29/786

Claims (18)

(57) [Claims] 1. An ITO (Indium Tin Oxi)
de) a wiring formed of a film is formed above the substrate, a protective insulating film made of a silicon nitride film (SiNx) is deposited on the substrate including the wiring, and a predetermined region of the protective insulating film is formed.
To remove the transparent conductive film on the protective insulating film.
A method of manufacturing a thin film transistor array substrate, comprising at least a manufacturing step of forming an opening , wherein at least a portion of the protective insulating film in contact with a surface of the wiring forms the silicon nitride film. The number of silicon atoms bonded to hydrogen atoms is Si-H,
When the number of atoms in which a nitrogen atom is bonded to a hydrogen atom is expressed as N-H, N is the ratio of N-H to Si-H.
A method of manufacturing a thin film transistor array substrate, which is formed in a film quality of -H / Si-H of 5 or more. 2. The protective insulating film is formed by depositing a single layer silicon nitride film, and the single layer silicon nitride film is formed to have a film quality of N—H / Si—H of 5 or more. A method of manufacturing a thin film transistor array substrate according to claim 1. 3. The single-layer silicon nitride film having a film thickness of 200 n
The method for manufacturing a thin film transistor array substrate according to claim 2, wherein the thin film transistor array substrate is deposited to a film thickness of m or less. 4. The protective insulating film is composed of a laminated silicon nitride film formed by sequentially depositing two or more layers of silicon nitride film.
The lower silicon nitride film forming the layer is N--H / Si--
The method for manufacturing a thin film transistor array substrate according to claim 1, wherein the film quality is such that H is 5 or more. 5. The absolute value of the film stress of the upper silicon nitride film formed of the silicon nitride film above the second layer of the laminated silicon nitride films is 0.3 GPa (0.3 × 1).
0 9 ^Pa) method of manufacturing a thin film transistor array substrate according to claim 4, wherein the formed below. 6. The lower silicon nitride film is formed to a film thickness of 200 n.
The method for manufacturing a thin film transistor array substrate according to claim 5, wherein the thin film transistor array substrate is deposited to a film thickness of m or less. 7. A protection insulating film made of a silicon nitride film (SiNx) is formed on the substrate including the wiring by forming a wiring made of an ITO film on the substrate, and the protection is performed.
By removing a predetermined area of the insulating film, the protective insulating film is transparent.
A method of manufacturing a thin film transistor array substrate comprising at least a manufacturing step of forming an opening for exposing a conductive film , wherein the protective insulating film is deposited after nitrogen plasma treatment of a surface of the substrate including the wiring before deposition thereof. However, in at least the portion of the protective insulating film that is in contact with the surface of the wiring, the silicon nitride film has a number of atoms in which the silicon atoms forming the silicon nitride film are bonded to hydrogen atoms.
i-H, the number of atoms in which a nitrogen atom is bonded to a hydrogen atom is N-
A method of manufacturing a thin film transistor array substrate, characterized in that the film quality is such that N / H / Si-H, which is the ratio of N-H to Si-H, is 3.5 or more when expressed as H. 8. The protective insulating film is formed by depositing a single-layer silicon nitride film having a single layer, and the single-layer silicon nitride film has a film quality such that N / H / Si-H is 3.5 or more. The method for manufacturing a thin film transistor array substrate according to claim 7, which is formed on the substrate. 9. The single-layer silicon nitride film having a film thickness of 300 n
The method for manufacturing a thin film transistor array substrate according to claim 8, wherein the thin film transistor array substrate is deposited to a film thickness of m or less. 10. The protective insulating film comprises a laminated silicon nitride film formed by sequentially depositing two or more layers of silicon nitride films, and the lower layer silicon constituting the first layer of the laminated silicon nitride film. Nitride film is NH / Si
The method for manufacturing a thin film transistor array substrate according to claim 7, wherein the film quality is such that -H is 3.5 or more. 11. The absolute value of the film stress of the upper silicon nitride film formed of the silicon nitride film above the second layer of the laminated silicon nitride film is 0.3 GPa (0.3 ×).
The method for manufacturing a thin film transistor array substrate according to claim 10, wherein the thin film transistor array substrate is formed at 10 ⁹ Pa or less. 12. The thickness of the lower silicon nitride film is 300.
The method of manufacturing a thin film transistor array substrate according to claim 11, wherein the thin film transistor array substrate is deposited to a film thickness of not more than nm. 13. The laminated silicon nitride film having a film thickness of 400.
6. Depositing to a film thickness of nm or more.
13. The method for manufacturing a thin film transistor array substrate according to 1 or 12. 14. The method according to claim 4, wherein at least the lower silicon nitride film is deposited by a plasma CVD method.
6. A method of manufacturing a thin film transistor array substrate according to 6, 10, 11, 12 or 13. 15. The method of manufacturing a thin film transistor array substrate according to claim 4, wherein all the silicon nitride films forming the laminated silicon nitride film are deposited by a plasma CVD method. 16. The stacked silicon nitride films are all deposited in the same chamber.
12. A method of manufacturing a thin film transistor array substrate according to 12, 13, or 15. 17. The thin film transistor array substrate is used in a lateral electric field type liquid crystal display device.
5, 6, 10, 11, 12, 13, 14, 15 or 16
A method for manufacturing the thin film transistor array substrate described. , 18. A predetermined region of the protective insulating film is removed
The step of forming an opening in the protective insulating film , wherein a predetermined region of the protective insulating film is removed by wet etching using buffered hydrofluoric acid.
3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1
A method of manufacturing a thin film transistor array substrate according to 3, 14, 15, 16 or 17.