JPH01274587A - Picture storage device - Google Patents

Abstract

PURPOSE:To attain effective utilization by providing a picture memory and using a digital signal so as to process line sequencing to a line sequential color signal and reducing the number of circuit elements. CONSTITUTION:A video signal is inputted to an input terminal 210 and a color difference signal is separated by a decoder 212. The color difference signal is switched in synchronism with the horizontal synchronizing signal from the decoder 212 by a switch 214 to obtain a line sequential color difference signal of two color difference signals R-Y, B-Y. The line sequential color difference signal is inputted to memories 228, 230. Then the signal is stored in the memories 228, 230 from the color difference component in line sequential way. Moreover, the memories 228, 230 have an A/D converter, where digital processing is applied to obtain a picture signal from an output port of the memories 228, 230. The picture signal is subjected to arithmetic mean by a proper timing at an adder means and a line sequential color difference signal is also obtained. Then the line sequencing of the line sequential color difference signal is attained by digital processing and the number of circuit elements is reduced, then the device is utilizing effectively.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an image storage device.

[Conventional technology]

FIGS. 8A and 8B are block diagrams of conventional examples of signal processing circuits in still video systems,
One for luminance signal and one for color difference signal are shown, respectively. In FIG. 8A, 800 is an input terminal for a reproduced luminance signal reproduced from a magnetic sheet which is a magnetic recording medium, 802 is an IH (one horizontal scanning period) delay line, and 804 is a reproduced luminance signal or delay line of the input terminal 800. A switch 802 selects the delayed signal, and 806 connects the output of the switch 804 and the delay line 802.
An adder 808 adds and averages the output of
810 is a switch for selecting the output of the delay lines 802 to 808, and 812 is an output terminal for a selection signal from the switch 810. In FIG. 8B, 814 is an input terminal for the reproduction line sequential color difference signal reproduced from the magnetic sheet;
6 is a 1/2H delay line, 818 is a switch for selecting the reproduction line sequential color difference signal of the input terminal 814 or the output of the delay line 816, 820.822 is an IH delay line, 824 is the output of the switch 818 or the delay line 822 A switch 826 selects the output of the switch 824 and the delay 'fa82
Adder for adding and averaging the outputs of 2 and 828, 83
0 is a switch that selects the output of the delay line 820 or the output of the adder 826, 832.834 is the switch 828, 83
This is the output terminal for the signal selected by 0.

The reproduced luminance signal input to the input terminal 800 is sequentially input to Y111Y11Y! for each rask. 1Y31Y41Ys+・
It is assumed that it is written as -・. The switch 804 normally selects the input terminal 800 side, and switches to the output side of the delay line 802 when a dropout occurs in the reproduced signal. Further, an adder 806 adds and averages the output of the switch 804 and the output of the delay line 802, and (Yo+
Y+)/2. (y++yz)/2. (Yz+Ys)
/2. (Y3+Y4)/21 (y4+ys)/2.
Output -・-. When reproducing the frame image on the magnetic sheet, the switch 810 is always connected to the delay line 802.
When selecting the output and reproducing a field image, the switch 810 is switched for each field.

The reproduction line sequential color difference signals input to the input terminal 814 are sequentially inputted for each rask: RYo, BYI, RYz, BYs, BY.
s, BYS, RY&, BY? , −・−. Switch 824 is normally switch 81
8 output is selected, but when a dropout occurs,
Select the output of delay line 822. An adder 826 adds and averages the output of the delay line 822 and the output of the switch 824 to obtain (RYo+RYz)/2. (BY I +B
Y3) /2. (RYz+RY*)/2. (BYi+
BYs)/2. (RY4+RYi)/2. (BYs+B
Yt)/2. Output -. By switching switches 828 and 830, RYO9 (RYO+
RY2)/2. Rh+(RYz+RYn)/2. BY4
．． (RY4+RY&)/2. RYI-.- is output, and the output terminal 834 is delayed by IH, BYI,
(BY l + BY3) /2t BY s + (B
Y! +BYS) /2. BYs, (BYs+B
Yt) /2. BYl, .- is output. When reproducing a frame image on a magnetic sheet, the switch 818 always selects the input terminal 814 side, and when reproducing a field image, the switch 818 is switched for each field.

[Problem to be solved by the invention]

However, in the above conventional example, the delay lines 802, 808, 81
Since a large number of 6,820,822 are installed, there are many adjustment points during product manufacture and assembly, and over time, the temperature characteristics, frequency characteristics, S/N ratio, etc. of these delay lines may fluctuate or deteriorate. There are problems such as. In addition, considering a system configuration that includes an image memory, the circuit scale becomes considerably large.

Therefore, the present invention provides the above delay line or a line replacing it.
It is an object of the present invention to present an image storage device that effectively uses the image memory instead of a memory.

[Means to solve the problem]

The image storage device according to the present invention has at least two output ports for which readout addresses can be specified individually, and includes an image memory into which line-sequential color difference signals are input, and a signal from the output port of the image memory as appropriate. It is characterized by comprising an adding means for averaging at the timing of , and obtaining a line-synchronized color difference signal from the signal of one output port of the image memory and the output of the adding means.

[Effect]

To convert line-sequential color difference signals to line-to-line time, delay lines and line/line signals are used.
Since there is no need to use memory, the number of circuit elements and circuit adjustment locations are reduced, and the factors that cause deterioration over time are also reduced.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 shows a block diagram of the overall configuration of a still image recording and reproducing apparatus to which the present invention is applied. 210 is a video input terminal for inputting a video signal from the outside; 212 is a decoder that separates the video signal into a luminance signal and a color difference signal; 214 is a switch that is switched in synchronization with the horizontal synchronization signal H1lfic from the decoder 212; The two color difference signals R-Y and B-Y output from the decoder 212 are converted into line-sequential color difference signals. 216 and 217 are magnetic heads that reproduce video signals recorded on the magnetic sheet 215, which is a magnetic recording medium; 218 is a switch that selects the magnetic head 216 or 217; and 220 is a switching control circuit that controls switching of the switch 218. , 222 are magnetic heads 216, 217
224 is a switch that selects the luminance signal from the decoder 212 or the luminance signal from the reproduction circuit 222; 226 is the line from the decoder 212; This is a switch for selecting the sequential color difference signal or the line sequential color difference signal from the reproduction circuit 222.

228.230 is an A/D converter, image memory and D/D converter.
The image memory circuit 228 is for luminance signals, and the image memory circuit 230 is for color difference signals. The image memory circuit 230 outputs color difference signals in line-to-line time. 232 is the output of the decoder 212 (luminance signal and two color difference signals) or the image memory circuits 228, 23
A switch for selecting the output of 0, 234 is the switch 232
An encoder 236 performs modulation, synthesis, etc. on the luminance signal and color difference signal from the encoder, and 236 is an output terminal for the synthesized video signal.

A switch 238 converts the two color difference signals outputted from the image memory circuit 230 into line-sequential signals, and is switched in synchronization with the horizontal synchronization signal. 240 is a recording circuit that performs various processing for magnetic recording such as modulation on the luminance signal and color difference signal from the image memory circuit 228 and 230 (more precisely, the switch 238); 241 and 242 are magnetic sheets 243; A magnetic head 244 magnetically records signals from the recording circuit 240, and a switch 244 selects between the magnetic heads 241 and 242.

246 is a synchronization separation circuit that separates a synchronization signal from the luminance signal selected by the switch 224, and 248 is a PLL that separates a clock, horizontal synchronization signal, vertical synchronization signal, etc. synchronized with the horizontal synchronization signal output from the synchronization separation circuit 246. 250 synchronous signal generation circuit that generates various synchronous signals
is a reference synchronization signal generation circuit that generates various synchronization signals such as a clock, a horizontal synchronization signal, and a vertical synchronization signal using a crystal resonator. By turning on the reset switch 252, the reference synchronization signal generation circuit 250 is brought into a reset state by an external horizontal synchronization signal, vertical synchronization signal, or the like. A selector 254 selects the output of the synchronization signal generation circuit 248 or the reference synchronization signal generation circuit 250, and the selection signal is applied to the image memory circuits 228, 230 and the encoder 234. 256 is the circuit 248.250
This is a comparison circuit that compares the fields of synchronization signals output from the synchronous signals, and controls head switching by the switching control circuit 220 and the image memory circuits 228 and 230 depending on whether the fields match or do not match.

In FIG. 2, in the recording mode in which an input video signal from the outside is recorded on the magnetic sheet 243, the switch 224,
226 selects the side of the decoder 212. Input terminal 21
The input signal of 0 is separated into a luminance signal and a color difference signal by the decoder 212, and the luminance signal is applied to the image memory circuit 228 via the switch 224, and the color difference signal is made line sequential by the switch 214 and applied to the image memory circuit 230. . By operating a recording command key (not shown), the image memory circuit 228
．． 230.

At this time, the selector 254 has selected the synchronization signal generation circuit 248, and the image memory circuits 228, 230 and encoder 234 operate according to the synchronization signal from the circuit 248. Note that the motor (not shown) that rotates the magnetic sheet 243 always rotates in synchronization with the vertical synchronization signal output from the reference synchronization signal generation circuit 250, and by turning on the reset switch 252, It enters the reset state and synchronizes to the input video signal.

Next, the selector 254 selects the reference synchronization signal generation circuit 250, and the image memory circuits 228, 230 and encoder 234 operate according to the synchronization signal. The image memory circuits 228 and 230 are in a read state, and the zero color difference signal that outputs the luminance signal and the color difference signal is line-sequentialized by the switch 238. A recording circuit 240 performs recording processing, and its output is recorded on a magnetic sheet 243 by magnetic heads 241 and 242. The reset switch 252 is kept in the OFF state during the recording period on the magnetic sheet 243 (two vertical intervals, ie, 2■ for a frame image, and IV for a field image).

After the recording on the magnetic sheet 243 is completed, the selector 254 selects the synchronization signal generation circuit 248 again.

Then, the images stored in the image memories 228 and 230 are reduced and read out, and a signal superimposed on the input video signal is applied to the encoder 234 by switching control of the switch 232. Thereby, the video signal of the blade terminal 236 represents an image in which the recorded image of the magnetic sheet is displayed in a reduced size as a part of the image of the input video signal.

Next, a reproduction mode for reproducing the recorded signal on the magnetic sheet 215 will be explained. In the reproduction mode, the magnetic heads 216, 21
The reproduction output of No. 7 is demodulated by the reproduction circuit 232 and sent to the image memory circuits 228 and 23 via switches 224 and 226.
0 and stored. Reading is performed simultaneously with storage, and the outputs of the image memory circuits 228 and 230 are connected to the switch 23.
2 and an encoder 234 to an output terminal 236. At this time, the selector 254 selects the synchronization signal generation circuit 2.
48 is selected, and the reset switch 252 is kept in the off state.

When writing to the image memory circuits 228 and 230 is completed,
The selector 254 selects the reference synchronization signal generation circuit 250, and the image memory circuits 228 and 230 enter the read state.

FIG. 1A shows a detailed block diagram of the image memory circuit 228. 100 is an A/D converter that digitizes the input analog luminance signal; 102 is a clamp circuit; 104
is a K (0<K<1) times multiplier, 106 is (1-K)
108 is an adder that adds the outputs of the multipliers 104 and 108, 110 is a selector that selects one of the inputs of the multipliers 104 and 108 and the output of the adder 108, and 112 is a selector that selects predetermined data. 114 is a selector that selects the output of the selector 110 or the output of the latch circuit 112; 116 is a random access port (hereinafter referred to as P port) and a serial output port (hereinafter referred to as S port); A dual-port image memory 118 has a dual-port image memory 118 that ruffles the image data output from the selector 114 by three pixels and outputs it in parallel, and serially outputs the image data of three pixels output from the image memory 118. -p-s conversion circuit.

120 is 3 output from the S port of the image memory 116.
Latch circuit for temporarily storing image data for pixels, 122
124 is an adder that adds the image data from the 5-ps conversion circuit 118 and the image data from the selector 122; 126 is an adder A selector 128 selects the output of the selector 124 or the output of the selector 122, and a D/D converter 128 converts the output data of the selector 126 into an analog signal.
It is an A converter.

130 is a blanking signal generation circuit that outputs a signal indicating a blanking area, 132 and 134 are latch circuits that hold a signal that determines a blanking area, and 136 is an address signal for a random access port of the image memory 116 (hereinafter referred to as , a P address generation circuit 138 generates a P address signal (referred to as a P address signal);
Port address signal (hereinafter referred to as S address signal)
140 is a selector that selects the output of the P address generation circuit 136 or the S address generation circuit 138, and 142 is a memory control circuit that controls the image memory 116.

FIG. 1B shows a detailed block diagram of the image memory circuit 230. Note that the circuits 100 to 110 in FIG. 1B are the same as those in FIG. 1A except that the luminance signal is replaced by a line-sequential color difference signal, and the circuits 130 to 142 are the first
It has the same effect as the one in figure A. 150 is a color difference discrimination circuit that discriminates color difference signals R-Y and B-Y of line sequential color difference signals;
152.154 is a latch circuit that holds predetermined data, 1
54 is a selector that selects the output of latch circuits 152 and 154; 158 is a selector that selects the output of selector 110 or 156; and 160 is a latch that stores image data from selector 158 at a normal video rate of 173. Circuit 162 (162a, 162b) is an image memory with dual ports like the image memory 116, 164 is a latch circuit that holds two image data output from the S port of the image memory 162, and 166 is a latch. a selector, 16, for selecting two outputs of the circuit 164;
8 is a latch circuit that stores the image data output from the P port of the image memory 162 at a normal video rate of 173, and 170 and 172 are adders that add the output of the launch circuit 168 to the output of the latch circuit 164. ,174,1
76 is the output of the latch circuit 164 or the adder 1, respectively.
Selector for selecting the output of 70, 172, 178, 18
0 is a selector that selects the output of selectors 174 and 176, and 182 and 184 are D/A converters.

Clamp circuit 102 and 1B of FIGS. 1A and 1B
The detailed configuration block diagram of the color difference discrimination circuit 150 shown in the figure is shown in the third figure.
Shown in Figure A. In FIG. 3A, 300 is an A/D converter 100
302 is an adder, 304 is an input terminal for image data from
is the output data of the adder 302 as n (an integer greater than 1)
306 is a multiplier that multiplies the output of the latch circuit 304 by 1/n; 308 is a subtracter that subtracts the output data of the multiplier 306 from the input data of the input terminal 300; 310 is a subtraction circuit; A processing circuit 312 is an output terminal that outputs the output data of the processing circuit 310 and is connected to the multiplier 108 and the selector 110. In the color difference discrimination circuit 150, 31
4 is a latch circuit that holds the output of the latch circuit 304 at a specific timing; 316 is a comparison circuit that compares the output of the latch circuit 304 with the output of the latch circuit 314; 318 is a counter that counts the comparison result of the comparison circuit 316; 3
Reference numeral 20 denotes a latch circuit for notifying as a flag whether the count value of the counter 318 has exceeded a predetermined value.

The operation of FIG. 3A will be explained. When the image data input to the input terminal 300 is luminance signal data, the latch circuit 3
04 is cleared to zero during the horizontal sync period. and,
A clock is applied to the latch circuit 304 n times (an integer greater than 1) during the back porch period of input image data to perform one cumulative addition. Adder 302 adds the output of latch circuit 304 to input image data, and applies the addition result to latch circuit 304 . This loop causes the latch circuit 304 to store data during the back porch period, that is, a value obtained by adding the pedestal level value n times.

Next, the output of the latch circuit 304 is converted to 1 by the multiplier 306.
/n, and find the average value of n-time additions of the pedestal level. When the output of the multiplier 306 is subtracted from the input image data by the fIi multiplier 308, the image data at the output terminal 312 is clamped to 00□8. Note that if the output of the subtracter 30B underflows, the processing circuit 310 forcibly sets it to 00□8.

In FIG. 3A, when the input image data is line-sequential color difference signal data, OO++tx
Can be clamped to. However, since the color difference signal has positive and negative polarities, if 80□8 is determined to be 0■, 80HEx must be clamped. This means that if the input image data is RY/BY (t) and the average value of the pedestal level is n times, then in order to perform 80MEX clamp, it becomes 00) Add 80□8 to IEK clamp is equal to

Normally, there is no burst signal in the luminance signal and color difference signal output from the decoder 212 (FIG. 2), but burst signals with small amplitudes may remain due to leakage in the circuit. In such a case, when the above clamp is performed, the frequency of the clock applied to the latch circuit 304 during the back porch period (burst signal period) is set to 2mfsc (m is a positive integer, rsc is the subcarrier frequency), and the number of cumulative additions is is 2β times (l is a positive integer), and the multiplier 306
The coefficient of 1/2! shall be. Thereby, the burst signal component can be canceled. In this case, the luminance signal,
The present invention is not limited to clamping color difference signals, but can also be applied to clamping NTSC signals containing burst signals as they are.

The operation of the color difference discrimination circuit 150 will be explained. The line-sequential color difference signal B-Y recorded on the magnetic sheet has an offset value, and is higher than the signal R-Y by this amount.
Therefore, by comparing the n-times addition value of the data input during the back borch period with the data before or after IH at the time of clamping, the line-sequential color difference signals R-Y and B-Y can be determined. This will be explained in more detail with reference to FIG. 3B. Third
Figure B (al is the reproduction line sequential color difference signal input to the input terminal 300, (b) is the horizontal synchronization signal, (C) is the clock controlling the latch circuit 314, and (d) is the counter 318.
This is the clock applied to the Note that the counter 318 is cleared to zero during the vertical synchronization period. The output of the latch circuit 304 is determined during the bank porch period and is latched by the latch circuit 314 at the timing shown in FIG. 3B (C1. The output of the latch circuit 304 is newly determined during the next back porch period, and this output The output of the latch circuit 314 is the comparison circuit 3
16 to be compared. According to the comparison result of the comparison circuit 316,
Controls whether or not the counter 318 counts. This is performed for one field period, and the flag of the latch circuit 320 is determined depending on whether the count value of the counter 318 is larger than a predetermined value.

In other words, in order to reliably perform color difference discrimination even if there is noise or dropout, a counter 318 is provided to take a majority vote within one field period.
It is possible to know whether -Y and BY are even or odd rasters, respectively.

In the configuration shown in Figure 2, 1. - There is a recording mode in which the input video signal is recorded on a magnetic sheet, and a reproduction mode in which the recorded video signal is reproduced from the magnetic sheet. First, the operation in recording mode will be explained. FIG. 4A shows the flowchart, and FIG. 4B shows the time chart. In Figure 4B, 4
10 is a field signal output from the synchronization signal generation circuit 248, 250, 412 is a freeze signal, 414 is a signal indicating a recording period, 416 is a signal indicating a superimposition period of a reduced image, 4
18 is a selection signal of the selector 254, which is a signal indicating that the synchronization signal generation circuit 250 has been selected. 420
is a signal indicating a reset state in which the reset switch 252 is on.

Selector 254 selects synchronization signal generation circuit 248, and reset switch 252 is turned on. Then, switch 232 selects the input video signal side, and input terminal 2
The 10 input video signals are output as they are to the output terminal 236 (S400). Next, image memory 116.16
2 to a predetermined value (S401), image memory 11
In the case of 6, a predetermined value is latched in the launch circuit 112,
This is selected by the selector 114, and the 5-p-s conversion circuit 1
One frame is written into the image memory 116 via 18.

A value indicating a blanking area is set in the latch circuit 132 so as to titrate all of the normal image area, and a value indicating a blanking area is set in the latch circuit 134 so as to clear all the memory space of the image memory 116. Set the value. While the image memory 116 is being cleared, it operates using a blanking signal from the launch circuit 134, and at other times, it operates using a blanking signal from the latch circuit 132.

Furthermore, regarding the image memory 162, the latch circuit 320
is set to indicate the R-Y signal, and then a predetermined value is set in the latch circuits 152 and 154, and the selector 156 selects the latch circuits 152 and 154 at the timing of the horizontal synchronization signal.
This is selected by the selector 158.

Then, one frame is taken into the image memory 162 via the latch circuit 160. However, writing to the image memories 162a and 162b is switched for each raster. Further, the blanking area of the blanking signal generating circuit 1'30 is set so as to completely clear the memory space of the image memory 162, but this is the same as in the case of the image memory 116. As a result, the image memory 162a is completely cleared to the setting value of the latch circuit 152, and the image memory 162a is cleared to the set value of the latch circuit 152.
b is all cleared to the setting value of the latch circuit 154, the image memory 162a is changed to the RY memory, and the image memory 162b is changed to the RY memory.
becomes B-Y memory.

When a command to record an input video signal onto a magnetic sheet is input (3402), in FIG. 1A, the input luminance signal is
D converter ioo, clamp circuit 102, selector 110
, 114 and a 5-ps conversion circuit 118, one frame is written into the image memory 116. At this time,
It is operated by a blanking signal from a latch circuit 132 that indicates the image area of the input luminance signal.

Further, the input color difference signal is converted into a line sequential signal by a switch 214. At this time, it is optional to select which of the R-Y component and the B-Y component comes first, but since the latch circuit 320 was set to indicate R-Y at the time of clearing, in this example, the R-Y component need to be done first. This line-sequential color difference signal is written into the image memory 162 for one frame via the A/D conversion 100, the clamp circuit 102, the selectors 110 and 158, and the latch circuit 160 in FIG. 1B. At this time, the latch circuit 132 operates with a blanking signal so that the entire image area of the input line sequential color difference signal can be stored, and after the vertical blanking period ends, the first raster to be stored is The image data is taken into the image memory 162a, the image data of the second rask is taken into the image memory 162b, and thereafter, the image data is taken in alternately for each rask. As a result, the RY component of the input line sequential color difference signal data is taken into the image memory 162a, and the B-Y component is taken into the image memory 162b (
S403).

Next, selector 254 selects the output of synchronization signal generation circuit 250 and turns off reset switch 252. Then, the image memories 116 and 162 are read out and recorded on the magnetic sheet (S404). That is, in FIG. 1A, the image data stored in the image memory 116 in frames is read out from the S port and sent to the latch circuit 120 and the selector 122.
126 to a D/A converter 128. When recording frame images to be stored in the image memory 116 on a magnetic sheet, it is sufficient to record one frame of the output of the D/A converter 128. When recording as a field image, the average of image data between fields is taken and recorded. The averaging between fields corresponds to filtering between fields.

That is, the signal of the first field of the image data stored in the image memory 116 as a frame is sent to the S address generation circuit 13.
8, YO+Yl+ from S port in order from the first rask
Yl+Y'l+Y4.・Read it out like this. At the same time, the second field signal is sent to the P address generation circuit 13.
6, from the P port in order from the 1st rask Yo” + YI
The output of the D/A converter 128 is read as (YO+Y
(1°)/2. (Y++Y+')/2. (Yt+Yz
°)/2+ (Y3+Y3')/2. (Y4+Y4”
)/2. ..., and this is recorded as one field.

Further, the color difference signal is handled as follows. In FIG. 1B, the image data stored in the image memory 162 in frames is simultaneously transferred 2 rusks at a time from the S port to RYO, BY6.
RYz, RYz, BY+, RYa, RYa, RY-
BY+, BY+, BY3. BYi, BYs, BYs, B
Read out as Yt, BYt, -. The latch circuit 164 and selectors 174-180 cause the D/A converters 182 and 184 to always output R-Y and BY signals, respectively.

When recording the image stored in the image memory 162 as a frame image on a magnetic sheet, the switch 23 is alternately activated for each rask from the component (RY) indicated by the latch circuit 320.
By selecting 8 (Figure 2), RYo, BY+,
RYz, BY3. BY4. BYs, RYb, BYt, -
Line sequentialization is performed as follows. This is recorded for one frame on a magnetic sheet. Further, at this time, data may be read from the P port at the same time to perform synchronization as described later.

On the other hand, in the case of field recording, the average of image data between fields is taken and recorded. That is, one field of the image data recorded in the image memory 162 in frames is simultaneously transmitted from the S port in two rasks by RY(1, RYO, RYz, RYz, RYE, BY+
lRYRY, , -BY+, BY+, B
Y! , BYI, BYs, BYs, BYt, B
It is read out as Yt, -. At the same time, the other field is alternately rasters of R-Y and BY from the P port, RY, ", BY+", RYzo, BY,',
It is read out as follows: RY, °+BYS'+-.-. The selectors 174 and 176 both switch the human input signal every 1 rask, and the selectors 178 and 180 switch the human input signal for each rask.
2 and 184 are switched so that they always output R-Y and B-Y signals, respectively. As a result, the D/A converter 18
The output of 2 is (RYO+RYO')/21 RYOI
(RYt+RYz')/2. RYz+ (RY4+R
Y4')/2. RY41'---, and the output of the D/A converter 184 is BY+, (BY++BY+'
)/2. BYs, (BY3+BY1″)/2.BY
,.

(BY, +BYS”)/2.-.

Here, from the component (RY) indicated by the launch circuit 320, 1
By switching the switch 238 alternately for each raster, the raster becomes a raster that is constantly averaging, and the output of the switch 238 is (RYo+RYo')/2+ (BY++BY
+ ' )/2+ (RYz+RYz' )/21 (
BY3+BY! )/2+ (RY4+RY4')
/2°(BYs+BYs')/2-.-. This is recorded for one field on a magnetic sheet.

Next, selector 254 again selects the output of synchronization signal generation circuit 248 and turns on reset switch 252. Then, the image stored in the image memory 116, 162 is read out in a reduced size and superimposed on the human video signal (S405
). That is, in FIG. 1A, the image data stored in the image memory 116 in frames is read out from the S port, and data for three pixels are latched into the latch 120. Selector 12
2 selects only one pixel among them. By reading from the S port at video rate, image memory 1
The 16 stored images become 173 horizontally. Furthermore, by making the vertical address signal from the S address generation circuit 138 indicate an address every three rusks, the image memory 1
The 16 stored images are also reduced to 1/3 in the vertical direction.

Further, in FIG. 1B, two russes of image data stored in frames in the image memory 162 are simultaneously read out from the S port as RY and BY. Since the color difference signal has a narrow band, it is stored at the normal video rate of 173, so
When reading at normal video rate, image memory 1
The 62 stored images become 173 horizontally. Furthermore, by making the vertical address signal from the S address generation circuit 138 indicate an address every three steps, two rusks are simultaneously generated from the S port: RYo, RYz, RYi, RYalRYtz, BY+9.
．． −・−・BY+, BYs, BYt, BY+, BY+z
, BY+s, ---, and the image stored in the image memory 162 is also reduced to 1/3 in the vertical direction.

In Figure 5A, if the area other than the image out of the entire space of the image memo 17116.162 is read out in duplicate in both the horizontal and vertical directions, it is easy to create a frame on the image reduced to 1/3 Xi/3. Can be attached. That is, the S address generation circuit 138 normally outputs the horizontal address as Xo-x1, but here it outputs as X+-4Xz("Xo)-X1→x, and the vertical address normally outputs as V6→y.

However, here V+-Vz(Qo) -Vt→y2
Output with . As a result, a frame can be formed as shown in FIG. 5B. Switch 2 to display a reduced image
32 to the output sides of the image memory circuits 228, 230, and otherwise connected to the input video signal (decoder 212) side, the reduced image can be superimposed on the input image as shown in FIG. 5C. Can be displayed.

The control signal of the switch 232 is equal to the blanking signal of the blanking signal generation circuit 130, and the superimposition position of the reduced image can be moved by changing the blanking signal. Here, a new value is set in the latch circuit 134, and the latch circuit 134 is operated by the blanking signal.

Next, move the recording heads 241 and 242 (5406),
It will be in standby mode until the next recording command is input, and the following will be done.
Repeat the above action.

Incidentally, FIG. 4A is a time chart in the case of frame recording of the input video signal on the magnetic sheet, and
16.162 is cleared and recorded on the magnetic sheet twice.

Next, the playback mode will be explained. FIG. 6A shows the flowchart, and FIGS. 6B and 6C show the time charts. 610 and 612 are synchronization signal generation circuits 24
8.250 is a generated field signal, 614 is a signal indicating the color difference discrimination period of the reproduction line sequential color difference signal, 616 is a freeze signal, and 618 is a selection control signal of the selector 254, which indicates that the synchronization signal generation circuit 250 has been selected. A signal 620 indicates state B of the reset switch 252 (reset when on).

The synchronizing signal generating circuit 248 is synchronized with the horizontal synchronizing signal of the reproduced video signal reproduced from the magnetic sheet 215, and is reset by the vertical synchronizing signal, so that it outputs the same synchronizing signal as the synchronizing signal of the reproduced video signal. In addition, the magnetic sheet 21
5 rotates in synchronization with the vertical synchronization signal output from the reference synchronization signal generation circuit 250, and since the reset switch 252 is off, the reproduction reproduced from the magnetic sheet 215 The vertical synchronization signal of the video signal is synchronized with the vertical synchronization signal output from the reference synchronization signal generation circuit 250. In the case of a field image, the fields match every field, but if the reproduced image is a frame image, the resynchronization signal generation circuit 248.2
50, the fields may not match. When the signal recorded on the magnetic sheet 215 is a frame, when switching between the various synchronous signals generated by the synchronous signal generation circuit 248 and the various synchronous signals generated by the reference synchronous signal generation circuit 250, the above-mentioned If the fields do not match, a skew will occur when switching the synchronization signal.

Therefore, first, the fields are matched (5600). That is, 2. of the magnetic sheet 215. Frame reproduction is performed by alternately reproducing video signals recorded as two fields on a track using a switch 218. If the comparator circuit 256 detects that the fields do not match as described above, this Alternate playback is stopped for a period of 1■. By stopping the switching of the switch 218 for a period of 1, the mutual fields are made to match. After this,
The color difference discrimination circuit 150 discriminates each of the two fields and stores this in the latch circuit 320 (S601). Here, the selector 254 selects the synchronization signal generation circuit 248 and turns off the reset switch 252. , freeze the playback video signal.

When the signal recorded on the magnetic sheet 215 is a field image, the reproduced video signal is always one field, whereas the reference synchronization signal generation circuit 250 generates a frame image synchronization signal when the reset switch 252 is off. Therefore, the fields will match for each field,
If the synchronization signals of the synchronization signal generation circuits 248 and 250 are switched when they do not match, a skew will occur. Therefore, first, the fields are matched (S600). That is, when the comparison circuit 256 detects that the fields do not match as described above, the image memory circuits 228, 2
The fields can be aligned by controlling 30 and waiting for a period of 1v.

Thereafter, the color difference discrimination circuit 150 performs discrimination in the next 1V period, and the discrimination result is stored in the latch circuit 320.

At this time, the fields do not match (S6
01). Here, the selector 254 is the synchronizing signal generating circuit 2
48 is selected, and the reproduced video signal is frozen in the next 1v period. Note that at this time, the fields will match.

Now, in FIG. 1A, the reproduced luminance signal is transmitted to the A/D converter 100, the clamp circuit 102, and the selectors 110 and 114.
And via the 5-ps conversion circuit 118, one frame or one field is written into the image memo IJ 116 from the P port as Ya+Y++Yz+Yz+Ya+Ys+-.-. This signal is simultaneously sent from the S port to Y6+ Yo+ Yl + YZ+ Yl, Y#+'
-, selector 126 and D/A
Converter 128 and switch 232 and encoder 2
34 to the output terminal 236. On the other hand, the output of the selector 122 is also applied to the selector 110, and this is the image data one rast before the input reproduced luminance signal, and if there is a dropout in the reproduced video signal, the output is applied to the selector 110. During the period, the selector 110 selects the image data one raster before this and performs dropout compensation.

In FIG. 1B, the reproduction line sequential color difference signal is transmitted through the A/D converter 100, the clamp circuit 102, and the selectors 110 and 158.
and R to the image memory 162 via the launch circuit 160.
Yo, BY+, RYz, BYz, RYa, BYs,
Assume that the RY components are input in order, such as RYbIBY71... This image data for one frame or one field is taken into the image memories 162a and 162b from the P port alternately every 1 rask, and from the S port 2 rusks at a time at the same time: RYo, RYo, RYo, RYo, RYz, RYz, B
Y4. RY4I'-'-'BY+, BY+, BY+, B
It is read out as Y+, BYE, BYi, BYs, BYsI-. And this image data is selector 1
74,176.178,180, D/A converter 1
82 and 184 are distributed to D/A converters 182 and 184 so as to always output R-Y and BY components, respectively. On the other hand, the selector 166 selects RYo, BYE, RY
o, BYE, RYz, BYs, RYs, BY51 RY
I, +BYt, . . . - are selected in this order, and this output is also applied to the selector 110. In other words, this is the image data two rasters earlier than the input reproduction line sequential color difference signal, and if there is a dropout in the reproduced video signal, the selector 110 selects the image data two rasters earlier during that period. , performs dropout compensation (S602).

Next, in FIG. 1A, the reproduced luminance signal is continuously input to the A/D converter 100, and the selector 110 inputs the reproduced luminance signal to the adder 1.
08 is selected and one frame or one field of this is frozen in the image memory 116. At the same time, the same field as the reproduced luminance signal field is sent from the S port to Yo+Yl+Y! +Y3+Yt+YS+・− is read, and multiplier 104 adds coefficient K (0<K<
1) and the reproduced luminance signal multiplied by the coefficient (1-K) by the multiplier 106 are added together by the adder 108. At this time, if there is a dropout in the reproduced luminance signal, the selector 110 selects the output side of the selector 122 during that period to perform dropout compensation.

In FIG. 1B, the A/D converter 100 is successively input with reproduction line sequential color difference signals, and the selector 110 is connected to the adder 1.
08 is selected and one frame or one field of this is frozen in the image memory 162. At this time, the same field as the field of the reproduction line sequential color difference signal is simultaneously transmitted from the S port by two rusks: RYo, RYo, RYz, RY□RY4. BY4.
BY6. BY61-・-BYE, BYE, BYs, BY
z, BYs, BYs, BY7. It is read out as BYt, -. The selector 166 selects this and selects RYo,
BY, RYz, BYz, BY4. BYslRYh, BY
Output as t, -. This is multiplied by a coefficient K (0<K<1) in a multiplier 104, and the reproduced line sequential color difference signal multiplied by a coefficient (1-K) in a multiplier 106 is added in an adder 108. do. If there is a dropout in the reproduction line sequential color difference signal, the selector 11 during that period.
0 selects the output side of the selector 166 and performs dropout compensation.

By performing the above operation for several days, the magnetic sheet 21
The image data of the same still image reproduced from 5 is added several times. Random noise can be reduced by addition (S603). If the reproduced video signal is a frame, the above operation is performed frame by frame, and if the reproduced video signal is a field, the above operation is performed when the field of the reproduced video signal matches the field of the synchronization signal generation circuit 250. If not, the image memories 116 and 162 are read by performing inter-field interpolation, which will be described later.

FIG. 6B is a time chart when the reproduced video signal is a frame, and shows a time chart when no noise reduction is performed, and when the reproduced video signal is a frame.
This shows the case where noise reduction is performed over frames.

FIG. 6C is a time chart when the reproduced video signal is a field, and shows a case where noise reduction is not performed and a case where noise reduction is performed over four fields.

Next, the data stored in the image memories 228 and 230 is read out (S604). In the case of a luminance signal, the stored data is read from the S port of the image memory 116 in accordance with the address signal from the S address generation circuit 138 in FIG. 1A. read out. This read signal is applied to the D/A converter 128 via selectors 122 and 126. Image memory 116
If the stored image is a frame image, it is sufficient to alternately read one field at a time. Further, in the case of a field image, a signal read out as is is used for one field, and a signal subjected to inter-field interpolation is used for the other field.

That is, when using an image stored in an odd field of the image memory 116, when outputting it as an odd field signal, Yo+Y+ is output from the S port of the image memory 116.
+Yz+Ys+Ya+Ys+Yi+'-・Read in normal rask order, selectors 122, 126
and output via the D/A converter 128.

When outputting as an even field signal, Yt, Yt, Yt, Ys, Yt are output from the S port of the image memory 116.
, YS+Yi-, and at the same time, they are read from the P port as Y++Yz+Y, +Ya, Ys+Yi++,-. The S port output and the P port output are averaged by an adder 124, and a selector 126 selects the output of the adder 124. As a result, D/A converter 1
The output of 28 is Yo, Y,, Y, , in odd fields.
Y3+Y4+YS+Y6+ '----, and in the even field (Y0+Y+)/2. (y++yz)/2
．． (Yz+h)/2. (Y3+Y4.)/2. (Y
4. +YS)/2, -. These are inter-field interpolated values.

In addition, when using a signal stored in an even field of the image memory 116 and outputting it as an even field signal, the YO+
yl + Ytl Y31 Y41 Ys+ Y&l
When reading out in the normal rask order such as - and - and outputting it as an odd field signal, the image memory 11
6 S port to YO+Yl+YZ+Y3+Y4+YS
At the same time as reading +Y&+ '-, Yo, Yo, Yt from the P port.

YztYs+Yt+Ys+ -・-, the data l raster before is read out in normal rask order. The S port output and the P port output are averaged by an adder 124, and then
/ctor 126 selects the output of adder 124.

As a result, the output of the D/A converter 128 is (yo+yo)/2. (Yo+Y+)/2.
(Y++Yz)/2. (YZ+Yl) /21 (Y
3+Y 4. ) /2. (Yt+Ys) /2t-
This becomes the inter-field interpolated value, and Yo for even fields.

Y++Yz+Yi+Yt+Ys+Yi+・-.

The color difference signal is as follows. Image memory circuit 2
Since the input signal to 30 is a line-sequential color difference signal, it is necessary to perform line-to-line time conversion when outputting the stored data. That is, in FIG. 1B, the image input to the image memory 162 is
The line sequential color difference signals are RYO, BYI,
RYz, BY:l, RYt, BYs, RYI
,, BY? .

- When starting from the RY component, the image memory 162a contains the RY components RYo, RYz, RYn,
RYb.

-... are stored in the image memory 162b, and the BY components BYI, BY3 . BYs, BY? , "- are stored, and the launch circuit 320 of the color difference discriminating circuit 150 is in a state indicating that the first rask is the R-Y component. Then, the data stored in the image memory 162 is simultaneously transferred from the S port to the launch circuit 320 of the color difference discrimination circuit 150. Rusk by Rusk, RYo, RYoIRYt, RY□RY,, RY□RY,
, BYE, ... BYI, BYI, BY3.
BYs, BYs, BYE, BY? , BYy, -
It is read out as follows. From P port at the same time, R
-Y, B-Y rasters alternately BY,,RY,,BY
,,RY,.

It is read out as B'h, RYb, BYs, -.

Both selectors 174 and 176 switch the input signal every rask, and selectors 178 and 180 switch the input signal for the D/A converter 18.
2 and 184 are switched so that they always output R-Y and B-Y signals, respectively. As a result, the D/A converter 182 outputs RYo, (RYoIRYt)/2. RYz, (R
Yz+RY4)/2. BY41 (RYn+RYb)
/2. -, and the D/A converter 184 outputs (BYl+B
Yl)/2. BYI, (BYl+BY3)/2. BY
3°(BYz+BYs)/2. Output BYS+'-,
A line synchronized color difference signal is formed.

Further, when the line sequential color difference signal input to the image memory circuit 230 starts from the B-Y component, the image memory 162
a has BY components BYo, BYz, BYtlBY&,'
-' is stored in the image memory 162b, and the R-Y component R
Y1, BY3. RYS, BY? , . . - are stored, and the latch circuit 320 of the color difference discrimination circuit 150 stores
- It is in a state indicating that it is a Y component. and,
The data stored in the image memory 162 is transferred simultaneously from the S port.
Rusk each, BYO, BY6. BYz, BYz, BY4. BY
4. BYE, BYb, -BYI, BYI, BY3.
BY3. RYs, RYs, RYt, BY7. ---, R-Y is read from the P port at the same time.
, B-Y rasters alternately, RYI, BYI, RYI,
BY? , RYs, BYb, RYs,'---. By switching the selectors 174 to 180, the D/A converter 182 outputs (RY1+RY+)/2. B
YI, (RY++RY*)/2. BY3. (RY3
+RYs)/2. The D/A converter 184 outputs BY. , (BYO+BYri/2.BYz, (B
Yz+BY4)/2. BY4. (BY4+BY&)/
2. Output -.

If the image stored in the image memory 162 is a frame image, the above operation may be performed for each field. Further, in the case of a field image, the above operation is performed twice in succession in one field (S604).

Next, move the playback heads 216 and 217 (5605),
The device enters a standby state and repeats the above operations.

In the above reproduction mode, the latch circuit 132 indicating the blanking area is operated, and this satisfies the entire image area of the reproduced video signal.

In the playback mode, the playback image is reduced and stored in the image memory 11.
6. The operation of recording in 162 will be explained.

The flowchart is shown in FIG. 7A. The time chart at this time is the same as that shown in FIG. 6C when the reproduced video signal is a field and noise reduction is not performed.

First, the image memory 116, 162 is cleared to a predetermined value (S700). Next, field alignment is performed between the reproduced video signal of the field image and the reference synchronization signal generation circuit 250 (S701), and discrimination is performed by the color difference discrimination circuit 150 in a period of 1.5 cm (5702). The details of this part are the same as the previous explanation, so the explanation will be omitted. Next, selector 2
54 selects the synchronizing signal generating circuit 248, reduces the image of the reproduced video signal in the next 1V period, and reduces the image of the image memory 116.54.
162 (5703). That is, in FIG. 1B, the reproduction line sequential color difference signals are RYo, BY+ for each rask.
, RYz, BYs, RYn.

Assume that it starts with the RY component, such as BYs, RYb, BYt, '-. For example, convert this to 115 xi15
When reducing the field image to a field image of
The horizontal synchronization signal for generating the vertical address signal of the P address generation circuit 136 is frequency-divided by 175 in order to multiply the frequency by 75 and multiply the frequency by 175 in the vertical direction. That is, sampling is performed alternately from the RY component at a rate of 1 rask for every 5 rasks from the reproduction line sequential color difference signal, and other data is thinned out. For example, R
Yo, BY+, RYz, BYs, BY4. BYs, RY
a, BYt, RYs, BY+, BY+o, BYI+, -
From, RYo, BYs.

Sampling of RY, ,, -... or RYo,
BY+, BY+o.

A zero-thinned raster sampled BY, . In other words, in the case of R-Y, the image memory 162
In the case of a, B-Y, the data is taken into the lowest raster area of the image memory 162b. At the same time as this writing, S
The lowest raster area of the memory space of the image memory 162 is always read two rasters from the port, and the selector 166
are alternately selected and used for dropout compensation of the reproduced video signal as described above.

As described above, a 115 x 15 reduced image can be stored in the image memory 162 as a field image from the reproduced line-sequential color difference signal of the field image.

Furthermore, when reducing the frame image to a 115 x 15 frame image and storing it in the image expansion memory 162, multiplying the frame image by 175 in the horizontal direction is the same as described above. To multiply by 1 to 5 in the vertical direction, the horizontal synchronization signal for vertical address signal generation of the P address generation circuit 136 is divided by 275 or a similar frequency division ratio. In other words, the reproduction line sequential color difference signal is sampled at a rate of 2 rasks for every 5 rasks, and the RY components are sampled at a rate of 2 rasks at a time.

For example, RYo, RYz, BYs, BYt, BY+. +
RYI! +・-・or sample RYo, RY
z, BYv, BY+, BY+. Sample I RL z+'-. Then, the fields are alternately switched one rask at a time. In the former case, RYo, BYs, BY+o, '- are stored in the odd fields of the image memory 162, and BYt, BY? are stored in the even fields. , BY+2.
- is stored. As before, the thinned out raster is stored in the lowest raster area of the memory space of the image memory 162, read out from the S port, and used for dropout compensation of the reproduced video signal.

As described above, the reproduction line sequential color difference of the field image (reduced image of size 8 to 115 x 115) can be stored in the image memory 162 as a frame image.

By changing the initial value of the P address generation circuit 136, the reduced image can be placed and stored at any position in the memory space of the image memory 162, but the image memory 162 is Since it is a color difference memory, it must be read from the RY component raster of the image memory 162.

Similarly, regarding the reproduced luminance signal, the P address generation circuit 1
1 clock for generating 36 horizontal address signals
By dividing the frequency by 75, reduction is performed in the horizontal direction, and in the vertical direction, the raster of the luminance signal corresponding to the raster of the reproduced line sequential color difference signal imported into the image memory 162 can be imported into the image memory 116. Compensation can be done in the same way. Here, a new value is reset in the latch circuit 134 so as to store an area smaller than the image area of the reproduced video signal determined by the launch circuit 132, and the resulting blanking signal is used to store the reduced image. Store in image memory.

The reproduction line sequential color difference signal is BY, RY, ,B for each rask.
Yz, BY3. BY4. RYS, BYthlRYE,
Assuming that the B-Y component is input sequentially, such as BYel-, the blanking area is set by shifting it by one rask, and RY+, BYz, RYs, BYa, RYs, BY
The above operation is performed assuming that the RY components are sequentially input as E, RYE, BYI, . . . .

Next, the selector 254 selects the reference synchronization signal generation circuit 250 and reads out the image memories 116 and 162 (S7
04), at this time, it is operated by a blanking signal from the latch circuit 132. Then, by forwarding the reproduction track of the magnetic sheet 215 (S705) and similarly storing the reduced image, it is possible to obtain 25 5×5 field images or frame images as shown in FIG. 7B.

Note that similar operations can be performed for other reduction ratios.

〔Effect of the invention〕

As can be easily understood from the above explanation, according to the present invention, an image memory is used instead of a delay line or a line memory, and line-to-line time conversion of line-sequential color difference signals is realized by digital processing, so that the analog circuit can eliminate all the shortcomings of Furthermore, since it becomes possible to form a gate array, circuit scale, cost, etc. can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1A is a block diagram of the configuration of an image memory circuit for luminance signals, FIG. 1B is a block diagram of the configuration of an image memory circuit for line-sequential color difference signals, FIG. 2 is a block diagram of the system configuration of an embodiment of the present invention, and FIG. The figure shows a detailed configuration block diagram of the clamp circuit 102 and the color difference discrimination circuit 150 shown in FIGS. 1A and 1B, FIG. 3B is a time chart of the color difference discrimination circuit 150, FIG. 4A is a flowchart of the recording mode, and FIG. 4B 5A, 5B, and 5C are picture-in-picture display explanatory diagrams. FIG. 6A is a flowchart of the playback mode.
Figures B and 6C are time charts of playback mode, Figure 7A is a flowchart of multi-screen freeze, and Figure 7B is a time chart of playback mode.
The figure is an explanatory diagram of a 5×5 multi-screen, Figures 8A and 8B.
The figure is a configuration block diagram of a conventional example. 116 - Image memory 11 B, -5-ps conversion circuit 130 - Blanking signal generation circuit 132.13
4-Latch circuit 136...P address generation circuit 13
8・-S address generation circuit 15 (L-color difference discrimination circuit
162 (162a, 162b)-=image memory 21
0-.-External input terminal 215...-Magnetic sheet for reproduction 228.230-,--Image memory circuit 236--
...Output terminal 243...Magnetic sheet for recording 24
6--Synchronization separation circuit 248-Synchronization signal generation circuit 25
0- Reference synchronization signal generation circuit 252- Reset switch

Claims (1)

[Claims] An image memory having at least two output ports for which read addresses can be individually specified and into which line-sequential color difference signals are input, and an adding means for adding and averaging the signals from the output ports of the image memory at appropriate timing. An image storage device comprising: a line-synchronized color difference signal obtained from a signal of one output port of the image memory and an output of the adding means.