JPH01271839A - Data processor - Google Patents

Abstract

PURPOSE:To shorten the time interval between the execution of a conditional branch instruction and the execution of the next instruction by instructing the branch in response to the microaddress information following a specific address that is produced when the branching conditions are satisfied. CONSTITUTION:An unconditional branch microinstruction is supplied to an instruction decoding part 102 from the outside of a microprocessor 100 via an instruction reading part 101. An instruction decoder 111 outputs an unconditional branch deciding signal 122 in response to said unconditional branch microinstruction. The signal 122 is supplied to a microaddress analyzing circuit 130 via a latch circuit 116. Then the final instruction end microinstruction 126'' related to the microinstruction read out before the unconditional branch instruction is produced from a micro-ROM 113 via a latch circuit 118. Thus the circuit 130 outputs a branch instruction signal 131 in response to the instruction 126'' and the signal 122 and the part 101 starts an early reading action of the next instruction, i.e., a branching destination.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device using a microprogram control method, and relates, for example, to a microprocessor suitable for high-speed processing.

[Conventional technology]

A conventional data processing device using a microprogram control method is described in Iwahiro Lectures on Microelectronics 8rVLSI Computer I, edited by Tatsu Motooka, pp.

97-107, a control signal is created by a microinstruction read from a microblock storage memory.

[Invention or problem to be solved]

FIG. 2 shows an example of the configuration of a microprocessor that was considered in the application by the inventor of the present application based on the above-mentioned prior art. In the microprocessor of this example, the stages of pipeline processing are: instruction readout in the reading unit 101, first instruction decoding (instruction decoder) by the instruction decoder 111 of the decoding unit 102, and micro RO in the decoding unit 102.
It is divided into four parts: second instruction decoding (micro ROM) by the M113 and instruction execution by the instruction execution unit 103.

Since the processing in these four stages is performed in parallel, this microprocessor executes so-called pipeline processing. FIG. 6(a) shows the flow of the vibration line processing in the normal state of this microprocessor.

Ta. The horizontal axis shows time, and the vertical axis shows each stage of processing. The numbers shown in parentheses for each stage in Figure 6(a) are as follows:
3 shows signals at the inputs of circuits with corresponding numbers in FIG. 2; The symbols A-1'' (7) in FIG. 6(a) each represent a macro instruction.
The instruction code is read out from the main memory outside the microprocessor or the cache memory inside the microprocessor, and decoded by the instruction decoder 111 to obtain the micro address 121. For example, the instruction decoder 11
1, the microaddress MAL is obtained. This micro address indicates the start address of the subroutine A1 of the micro program stored in the micro ROM 113. Therefore, microaddress MA1. ．． Mc2. MA3°M, A4 correspond to a series of microprogram subroutines Al, A2°A3, which constitute one macroinstruction. Then, for each microA)-res MAL to MA4, microRO
The MI 13 is searched, and the execution unit ]03 is controlled based on the search result, that is, the microinstruction 136.

As can be seen from FIG. 6(a), in normal vibe line processing, instructions are executed without interruption, and the microprocessor can process instructions at high speed.

On the other hand, the flow of processing when the microprocessor executes a branch instruction and performs branch processing is shown in FIG. 6(b). -As you can see, there is idle time during instruction execution, which slows down the instruction execution speed. This is due to the fact that a branch occurred during the execution of instruction A.

A microprocessor has instructions A, B, C, D, etc.
The instructions are prefetched on the assumption that they will be executed in sequence. However, when a branch occurs, instruction A
Since instruction F is executed next, reading ahead of the instruction is wasted. This processing disturbance appears as idle time in the execution section.

For example, when the branch macro instruction A is a conditional branch instruction, the above instruction execution idle time occurs. That is, microinstruction A1 is a step to execute a conditional judgment for a conditional branch instruction, and microinstruction A2 is a step to actually execute a branch based on the result of this conditional judgment.
and microinstruction A3, which is the step of decoding the next instruction in either case of the above branch being taken or not, and microinstruction A4, which is the step of declaring the end of branch microinstruction A. As shown above, pipeline processing includes instruction reading, first instruction decoding, and second instruction reading.
This is because it consists of four steps: instruction decoding and instruction execution.

'' As mentioned above, in the microprocessor shown in FIG. 2, there is idle time between the end of execution of a conditional branch instruction and the start of execution of the next instruction.

On the other hand, an instruction reading section in a single-chip microprocessor includes a semiconductor device (for example, a MOSFET of 1.3 micron rule or less) formed on a semiconductor chip by making full use of a fine semiconductor process.

Signal processing in circuits such as an instruction decoding section and an instruction execution section is becoming faster and faster.

As the signal processing speed of circuits in microprocessors increases, there is a problem in that the idle time during instruction execution during pipeline signal processing as described above causes a decline in the overall performance of the microprocessor. This has become clear from the results of the above-mentioned study by the inventor of the present application.

Therefore, an object of the present invention is to provide a pipeline data processing device in which the time interval between execution of a conditional branch instruction and execution of the next instruction is shortened.

[Means to solve the problem]

In order to achieve the above object, a data processing device according to an embodiment of the invention disclosed in this application has the following features.

That is, the data processing device (100) of this embodiment includes: (1) an instruction reading unit (101) for reading out instructions stored in a storage means; and (2) reading by the instruction reading unit (101). (3) an instruction execution unit (103) controlled by the output of the instruction decoding unit (lO2); ) is: (1a) Branch instruction signal (131) from the instruction decoding section
The instruction decoding section (102) has a branch control circuit (114) for reading out the branch destination instruction stored in the storage means in response to: (2a) the instruction reading section (101) reads out the branch destination instruction; an instruction decoder (111) that generates a micro address in response to an instruction issued by the instruction decoder (111); (2b) an instruction execution unit (10
3) a memory for storing a microprogram (113) for generating a microinstruction for controlling the microinstruction and next microaddress information related to the microaddress of the next microinstruction to be executed after the microinstruction; and (2c) the above-mentioned. Memory for storing microprograms (113
) and a microaddress generation circuit (115) that generates the next microaddress in response to at least the next microaddress information (128) generated from the instruction execution unit (103) and information (128) related to the instruction execution result generated from the instruction execution unit (103).
), and the instruction decoder (1, 11) of the instruction decoding unit (]02) executes the instruction decoder (1, 11) for conditional branching in response to the conditional branch instruction (A) read by the instruction reading unit. The first micro-address (MAL) is generated, and the micro-program storage memory (113) of the instruction decoder (102) responds to the -th micro-address (MAL) written in - for the conditional branch. , -I Outputs the information related to the condition determination for the conditional branch and the information (126') instructing branch preparation as the first microinstruction (A1), and also outputs the information related to the condition determination for the conditional branch as the first microinstruction (A1).
) is output as the next microaddress. (MA2), outputs information instructing a branch as the second microinstruction (A2), and outputs the third microaddress (MA3) following the second microaddress (MA2) as the next microaddress. The microprogram storage memory (113) of the instruction decoder (1, 02) transmits information instructing next instruction decoding to the third microinstruction (M3) in response to the third microaddress (MA3). ), and the microaddress generation circuit (115) outputs the information related to the condition determination in the first microinstruction (A1) and the information related to the instruction execution result generated from the instruction execution unit. (128), it is determined whether or not the condition for the conditional branch is satisfied, and when the condition is satisfied, the microaddress generation circuit (115) converts the second microaddress (MA2) to the next microaddress. When this condition is not met, the microaddress generation circuit (115) generates the third microaddress (MA3).
) is generated as the next microaddress, and the instruction decoder (102) further: (2d) generates the next microaddress generated from the microaddress generation circuit (115) when the branch preparation instruction information (126') and the above conditions are met. The branch instruction signal (]3]) is supplied to the branch control circuit (114) of the instruction reading section (101,) in response to the second microaddress (M A 2 ) as a microaddress. It is characterized by having a signal analysis circuit (130) that generates a signal (see FIG. 1).

[Effect]

In the microprocessor of FIG. 2 that was considered before the application, not only is the signal analysis circuit (130) not arranged, but the instruction decoding unit (130) is not arranged in response to the first micro address (MAl, 102) The above microprogram! The first microinstruction (A1) output from the delivery memory (113) only contained information related to the condition determination for the conditional branch, and did not include any information instructing branch preparation. .

Therefore, in the microprocessor shown in FIG. 2, in response to the first microaddress (MAL), information related to condition determination for a conditional branch is stored in the microprogram storage memory (113) or in the first microinstruction (MAL). A1) and the second micro address (MA2)
is output as the next microaddress, and when the branch condition of the conditional branch instruction is met, the microaddress generation circuit (11, 5
) is generated with the second microaddress (MA2) as the next microaddress, and this second microaddress (M
A2), the microprogram storage memory (1
13) outputs the information (126) instructing the branch as the second microinstruction (A2), the actual branch by the conditional branch instruction has been executed for the first time.

As the scale of command signal processing of a data processing device such as a microprocessor increases, the scale of the microprogram storage memory (113) also increases accordingly. Therefore,
With this increase in scale, the second micro address (MA2
) in response to microprogram storage memory (11
3) outputs the information (126) instructing a branch as the second microinstruction (A2), which is also inevitably delayed.

Therefore, in the microprocessor shown in Figure 2, the read time of the branch destination instruction is also delayed, and there is a non-negligible idle time between the execution of the conditional branch instruction and the execution of the next instruction, which is the branch destination instruction. .

On the other hand, in the microprocessor according to one embodiment of the present invention, the -above-th microaddress (
The Y-th microinstruction (A1) outputted from the microprogram storage memory (113) of the instruction decoding unit (102) in response to the instruction decoder (102) contains information related to the condition determination for the conditional branch and the branch. Information instructing preparation (1
26'), and branch preparation instruction information (126').
') and the second microaddress (MA2) as the next microaddress generated from the microaddress generation circuit (115) when the branching condition of the conditional branching instruction is established, the instruction reading unit (101) branches. Control circuit (114)
A signal analysis circuit (130) is arranged to generate a branch instruction signal (131) to be supplied to the branch instruction signal (131).

Therefore, in the microprocessor of one embodiment of the present invention, in response to the first microaddress (MAL), the microprogram storage memory (113) stores information related to condition determination for conditional branching in response to the first microaddress (MAL). At the same time as the micro-instruction (A1), the second micro-address (MA2) is output as the next micro-address, and when the branch condition of the conditional branch instruction is established, the micro-address generation circuit (115) outputs the second micro-address (MA2) as the next micro-address. ) is generated as the next microaddress, the branch instruction signal (131) of the signal analysis circuit (130) instructs an actual branch by a conditional branch instruction, making it possible to read the next instruction which is the branch destination instruction early. As a result, it is possible to shorten the idle time between execution of a conditional branch instruction and execution of the next instruction, which is the branch destination instruction.

Other objects and other novel features of the invention will become apparent from the accompanying drawings and detailed description of the embodiments.

〔Example〕

FIG. 1 shows an example of the configuration of a microprocessor using the present invention.

The microprocessor 100 basically includes an instruction reading section 10.
1. Instruction decoding unit 102. It consists of an instruction execution unit 103. The macro instruction read by the instruction reading unit 101 from the main memory outside the microprocessor or the cache memory inside the microprocessor is sent to the instruction decoding unit 102.
Instruction decoder 1 ]-1 and micro ROM, A13 2
deciphered in stages. Then, the instruction execution unit 103 executes the instruction according to the microinstruction that is the result of the decoding.

The instruction decoder 111 decodes the macro instruction from the instruction reading unit 101 and outputs a 60-bit decoding result including a micro address to the latch circuit 116. The microaddress that is the decoded result from the output of the latch circuit 116 is input to the microROM 113 through the selector 117 and address decoders 1 and 2, and a 135-bit microinstruction 118 is obtained as a result of ROM access. The microinstruction 118 includes information 136 for controlling the execution unit 103 as well as next microaddress information 127 for 12bj and t. Next micro address 127 is micro address generation circuit 115° selector 1
17 to the micro ROM 113 again, and the next micro instruction is read out.

Note that the instruction decoder 111 outputs the starting microaddress of a subprogram consisting of microinstructions.

For example, in FIG. 6(,), when instruction A is decoded, the first microaddress A1 of the subprogram is output.

Micro program storage memory (micro ROM) 1
13, in response to the leading microaddress generated from the instruction decoder 111, the instruction execution unit 1o3. Microaddress generation circuit 1152 generates a microinstruction for controlling the branch control circuit 114, etc., and next microaddress information related to the microaddress of the next microinstruction to be executed after this microinstruction. Furthermore, the micro ROMI 13 responds to the j-th micro-address generated from the output of the micro-address generation circuit 115 and supplied via the selector 117 (22) to the next next micro-instruction and the subsequent next micro-address information. Output.

FIG. 4 shows the contents of micro 1ζ OP, 1!13.

The left side of FIG. 4 shows the micro-address supplied to the micro-ROM 113, and the center of FIG. The right side of FIG. 4 shows the next micro-address generated from 'U SY IO ROM]i- in response to each micro-address.

In FIG. 4, the micro address MAL.

M A 2 , M A 3 , and M A 4 constitute a conditional branch macro instruction A, and the conditional branch macro instructions are read from the main memory outside the processor or the cache memory inside the microprocessor via the instruction reading unit 101. When Δ is supplied to the instruction decoder]02, the instruction decoder]-1 generates a leading microaddress MAL for a conditional branch.

In response to the first micro-address MΔ1, the micro-ROM 113 outputs information related to condition determination for a conditional branch and information 126' instructing branch preparation as the first micro-instruction A1. The second micro address MA2 following the first micro address MAL
is output as the next microaddress.

This branch preparation instruction information indicated by the -1 bit signal 126' is supplied from the output of the micro ROM 1.13 via the latch circuit 118 to the micro address analysis circuit 130 which will be described in detail later.

When this second micro address MA2 is supplied to the input of the micro ROMI 13 via the selector 117,
The output of the micro ROM 113 is output as a second micro instruction A2 that instructs a branch, and is also output as a third micro instruction MA following the second micro address AM2.
Outputs 3 as the next microaddress.

Note that in this embodiment, the second micro address MA2
is placed at an even address, and the third microaddress M
A3 is placed at an odd address.

When this third micro-address MA3 is supplied to the input of the micro-ROM 113 via the selector 117, the output of the micro-ROM 113 outputs information instructing the decoding of the next instruction as the third micro-instruction M3. The fourth micro address MA4 following address MA3 is output as the next micro address.

When this fourth micro-address MA4 is supplied to the input of the micro-ROM 113 via the selector 117, the output of the micro-ROM 113 outputs information declaring the end of the branch instruction as the fourth micro-instruction M4. However, when declaring the end of this branch instruction, the next microaddress is not output.

As described above, when the conditional branch microinstruction A is supplied to the instruction decoding unit 102 from the main memory external to the microprocessor 100 or the cache memory inside the microprocessor via the instruction reading unit 101, the instruction decoder 111 executes the conditional branch microinstruction A. Leading micro address MA for
In response to this first microaddress MAI-, the microphone ROMI 13 outputs information related to condition determination for a conditional branch and information 126' instructing branch preparation as the first microinstruction A1. At the same time, the second microaddress MA2 following the first microaddress MAL is output as the next microaddress.

On the other hand, the microaddress generation circuit 115 generates information related to condition determination in the first microinstruction Al and the instruction execution unit 1.
In response to the flag information 128 related to the execution result of the previous instruction generated from 03, it is determined whether a condition for a conditional branch is satisfied, and when this condition is satisfied, the micro-response generation circuit 115 The second microaddress MA2 is generated as the next microaddress, and when this condition is not met, the microaddress generating circuit 15 generates the third microaddress MA3 as the next microaddress.

That is, the basis for determining the condition of a conditional branch instruction is the flag information 128 left in the instruction execution unit 103 by an already executed instruction.

In one embodiment, as shown in FIG.

In particular, the instruction decoder 102 responds to the branch preparation instruction information 126' and the second even-numbered microaddress MA2 as the next microaddress generated from the microaddress generation circuit 115 when the branch condition of the conditional branch instruction is met. a signal analysis circuit 130 that generates a branch instruction signal 131 that is supplied to the branch control circuit 114 of the instruction reading unit 101;
is located.

That is, when the branch condition of a conditional branch instruction is satisfied, an even numbered address is generated as the next microaddress from the microaddress generation circuit 115, and when the branching condition of a conditional branching instruction is not satisfied, an odd numbered address is generated as the next microaddress from the microaddress generation circuit 115. be done. Therefore, the determination of whether the branch condition of a conditional branch instruction is satisfied or not is made by using the LSB (Least 51g) of 1 bit of the address signal generated from the microaddress generation circuit 115.
This is possible by monitoring the n1ficant Bit) signal. That is, the microaddress generation circuit 11
The 1-bit signal 124 supplied from the output of IIO 5 to the microaddress analysis circuit 130 via the selector 117 is this LSB signal.
In the case of I+ level, it means that the branch condition of the conditional branch instruction is satisfied and the even address is generated as the next microaddress from the microaddress generation circuit 115. If this LSB signal 124 is in the rt I II level, the conditional branch is executed. The branch condition of the instruction is not satisfied, and the odd address is set as the next microaddress in the microaddress generation circuit 11.
This means that it was generated from 5.

Therefore, in response to the LSB signal 124 at the '0' level and the branch preparation instruction information 126', the microaddress analysis circuit 130 outputs the branch instruction signal 131.

On the other hand, increasing the speed of signal processing not only for conditional branch instructions but also for unconditional branch instructions is an important technical issue. In order to achieve this technical problem, the following measures have been further added to the present embodiment shown in FIG.

That is, when an unconditional branch macro instruction is supplied to the instruction decoder 02 from the main memory outside the microprocessor OO or the cache memory inside the microprocessor via the instruction read unit 01, the instruction decoder 1
1.1 outputs an unconditional branch instruction determination signal 122 in response to this unconditional branch macro instruction, and this unconditional branch instruction determination signal 122 is supplied to the microaddress analysis circuit ]-30 via the latch circuit 116. Ru. When the last instruction termination microinstruction 1-26 '' related to the macroinstruction read from the external main memory or internal cache memory before this unconditional branch instruction is generated from the output of the microROM 413 via the latch circuit 118, In response to this instruction end microinstruction]-26" and the unconditional branch instruction determination signal 122, the microcontroller returns analysis circuit]30
outputs the branch instruction signal 1;31, and the instruction reading section 1.01
starts early reading of the next instruction, which is the branch destination.

FIG. 7 shows an example of the circuit configuration of the microATO analysis circuit 130. When the branch condition of a conditional branch instruction is satisfied, output 00 of one AND circuit is asserted, and when an unconditional branch instruction is read and decoded, the output of the other AND circuit is asserted.
Output cuff 01 of the circuit is asserted and in either case OR
A branch instruction signal 131 is generated from the output of the circuit.

Hereinafter, the signal processing operation of the microprocessor of this embodiment shown in FIG. 1 will be explained in detail with reference to FIGS. 3 and 6.

FIG. 3(,) shows a signal processing operation related to the conditional branch instruction of the microprocessor shown in FIG. 2, which was studied before the application was filed. As described above, when the conditional branch macro instruction A is supplied to the instruction decoder 102 from the main memory outside the microprocessor or the cache memory inside the microprocessor, the instruction decoder 111 generates the first microaddress MAL for the conditional branch. .

In response to this first microaddress MAL,
In step 301 of a), the micro ROM 113 outputs information related to the condition determination for the conditional branch as the first micro instruction, and also outputs this micro address MA]
The second micro-addresses MA1 to MA2 following the micro-addresses are output as the next micro-addresses.

When the branch condition of the one-conditional branch instruction is met in step 301, the microaddress generation circuit 15 outputs the second 75-microaddress MA2 as the next microaddress. In response to this second microA1-res MA2,
A branch is first instructed at the output stage of step 3302 in FIG. 3(a), when the micro ROM 113 outputs the branch instruction information 126 as the second microinstruction A2. Therefore, as shown in FIG. 6(b), there is a vacant time between the execution of the conditional branch instruction and the execution of the next instruction.

On the other hand, when the branch condition of the conditional branch instruction is not satisfied, in step 301, the microaddress generation circuit]1
5 outputs the third microaddress MA3 as the next microaddress. This second micro address MA3
In response, in step 303 of FIG. 3(a), the micro ROM 113 (3) outputs information instructing the decoding of the next instruction as the third micro instruction A3, and outputs the fourth micro address MA4. . In response to this fourth microaddress MA4, in step 304 of FIG. 3(a), the microROM1
13 outputs information declaring the end of the branch instruction as the fourth microinstruction A4.

On the other hand, the signal processing operation of the microprocessor of this embodiment shown in FIG. 1 can process conditional branch instructions at high speed as described below.

In other words, the conditional branch macro instruction A is sent to the instruction decoding unit 102 from the main memory outside the microprocessor or the cache memory inside the microprocessor, as shown in the following sequence.
When supplied to the instruction decoder 1]-1, the instruction decoder 1]-1 generates a leading microaddress MAI for a conditional branch.

In response to this leading miter lower 1-less MAL, in step 301 of FIG. It outputs it as a microinstruction, and also outputs the second even-numbered microaddress MA2 following this microaddress MAL as the next microaddress.

When the branch condition of the conditional branch instruction is met, this step 3
05 is the micro address generation circuit] 15 is the even address second micro address MA2, and the next micro address 1-
Output as a response. -J two-way branch preparation instruction information 126
'The second microaddress M,A of any even address
2, the microaddress analysis circuit 1-30 outputs the branch instruction information 1.26' as the second microinstruction A2.A branch has already been instructed at the input stage of step 306 in FIG. 3(b). Ru. Therefore, as shown in FIG. 6(c), there is no free time between execution of the conditional branch instruction and execution of the next instruction. In contrast, this step 30
5, when the branch condition of the conditional branch instruction is not met, the microaddress generation circuit 115 outputs the third microaddress MA3, which is an odd address, as the next microaddress.

In response to the odd third micro address MA3, the micro RO is
M11.3 outputs information indicating the next instruction deconid as a third microinstruction A3, and outputs a fourth microaddress MA4. This fourth micro address MA4
In response to this, in step 308 of FIG. 3(b), the micro ROM 113 outputs information declaring the end of the branch instruction as the fourth micro instruction A4.

FIG. 5 shows a flowchart of signal processing for processing an unconditional branch instruction, in which information instructing an unconditional branch is transmitted in step 501 in response to the first microaddress at the beginning for the unconditional branch. One microinstruction is output, and the second microaddress following the first microaddress at the beginning is outputted as the next microaddress, and in response to this second microaddress, step 5
At step 02, the information instructing the decoding of the next instruction is outputted as a second microinstruction, and at the same time, a third micro-address is outputted, and in response to the micro-address of this day-, at step 503. Information declaring the end of the branch instruction is output as the third microinstruction.

Note that step 501 in FIG.
This is executed in two stages: decoding of the second instruction at step 113. In this embodiment of FIG. 1, the first
Unconditional branch decode signal 1 obtained from instruction decoding results
22 is supplied to the microaddress analysis circuit 130, and the branch instruction signal 13 of this microaddress analysis circuit 130
1 provides a high-speed branch instruction.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the above embodiments, and various modified embodiments can be adopted.

For example, the branch instruction information as the second microinstruction A2 in FIG. 4 may be of content that instructs a branch passively, since it is no longer necessary to actively instruct a branch. For example, the information content of this negative branch indication may be constituted by the information content that the branch preparation of the first microinstruction A1 is not canceled. The information content of this negative branch instruction also corresponds to information that instructs branching according to the technical idea of the present invention.

〔Effect of the invention〕

According to the present invention, the content of the next instruction to be read differs depending on whether the branch condition of the conditional branch instruction is satisfied or not, but it responds to the next microaddress information of a specific address generated from the microaddress generation circuit when the branching condition is satisfied. Since the branch instruction is issued early, the time interval between execution of the conditional branch instruction and execution of the next instruction can be shortened.

[Brief explanation of the drawing]

FIG. 1 shows a block diagram of a microprocessor according to an embodiment of the present invention, FIG. ) shows a flowchart of processing of a conditional branch instruction in the microprocessor of FIG. 2, while FIG. 3(b) shows a flowchart of processing of a conditional branching instruction in the microprocessor of FIG. Micro R in the microprocessor in Figure 1
A structural diagram of the OM113 is shown, FIG. 5 is a flowchart of the processing of an unconditional branch instruction in the microprocessor of FIG. 1, and FIG. 6(b) shows a flowchart of pipeline processing related to the conditional branch instruction of the microprocessor of FIG. 2, and FIG. 6(Q) shows the flowchart of pipeline processing related to the conditional branch instruction of the microprocessor of FIG. A flowchart of related pipeline processing is shown, and FIG. 7 shows a circuit diagram of an example of a microaddress analysis circuit in the microprocessor of FIG. 1.

Claims (1)

[Claims] 1. The data processing device includes: (1) an instruction reading unit for reading instructions stored in a storage means; (2) decoding the instructions read by the instruction reading unit; (3) an instruction execution unit controlled by the output of the instruction decoding unit; the instruction reading unit: (1a) responding to a branch instruction signal from the instruction decoding unit; and a branch control circuit for reading out a branch destination instruction stored in the storage means, and the instruction decoding section: (2a) responding to the instruction read by the instruction reading section, (2b) In response to the microaddress generated from the instruction decoder, a microinstruction for controlling the instruction execution unit and a next microinstruction to be executed after the microinstruction are generated. a memory for storing a microprogram that generates next microaddress information related to the microaddress; (2c) the next microaddress information generated from the memory for storing the microprogram and an instruction execution result generated from the instruction execution section; the instruction decoder of the instruction decoding section responds to the conditional branch instruction read by the instruction reading section. and generates a first micro-address for the conditional branch, and the microprogram storage memory of the instruction decoder section responds to the first micro-address for the conditional branch to generate a first micro-address for the conditional branch. outputs information related to condition determination and information instructing branch preparation as a first microinstruction, and outputs a second microaddress following the first microaddress as the next microaddress; The microprogram storage memory outputs information instructing a branch as a second microinstruction in response to the second microaddress, and sets the third microaddress following the second microaddress to the next microaddress. The microprogram storage memory of the instruction decoding section outputs information instructing to decode the next instruction as a third microinstruction in response to the third microaddress, and the microaddress generation circuit Determine whether or not the condition for the conditional branch is satisfied in response to the information related to the condition determination in the first microinstruction and the information related to the instruction execution result generated from the instruction execution unit. When the condition is satisfied, the microaddress generation circuit generates the second microaddress as the next microaddress, and when the condition is not satisfied, the microaddress generation circuit generates the third microaddress as the next microaddress. The instruction decoder further: (2d) reads the instruction in response to the branch preparation instruction information and the second microaddress generated from the microaddress generation circuit as the next microaddress when the condition is met; A data processing device comprising a signal analysis circuit that generates the branch instruction signal to be supplied to the branch control circuit of the section. 2. The data processing device according to claim 1, wherein the signal analysis circuit generates the branch instruction signal in response to the LSB signal of the second microaddress. 3. The microprocessor includes: (1) an instruction reading unit for reading instructions stored in the storage means; (2) an instruction decoding unit for decoding the instructions read by the instruction reading unit; (3) an instruction execution section controlled by the output of the instruction decoding section; the instruction reading section: (1a) storing in the storage means in response to a branch instruction signal from the instruction decoding section; The instruction decoder includes a branch control circuit for reading out the branch destination instruction, and the instruction decoder includes: (2a) an instruction decoder that generates a microaddress in response to the instruction read by the instruction readout unit; (2b) In response to the micro-address generated from the instruction decoder, a micro-instruction for controlling the instruction execution section and a next micro-instruction related to the micro-address of the next micro-instruction to be executed after the micro-instruction are provided. (2c) at least the next microaddress information generated from the microprogram storage memory and information related to the instruction execution result generated from the instruction execution section; and a microaddress generation circuit that generates the next microaddress in response to the instruction decoder, and the instruction decoder of the instruction decoding section generates a next microaddress in response to the conditional branch instruction read by the instruction reading section. generates a first micro-address, and in response to the first micro-address for the conditional branch, the memory for storing the microprogram of the instruction decoding section generates information related to the condition determination for the conditional branch; and information instructing branch preparation as a microinstruction, and outputs a second microaddress following the first microaddress as the next microaddress, and the memory for storing the microprogram of the instruction decoding section is In response to the second microaddress, the third microaddress following the second microaddress is output as the next microaddress, and the microprogram storage memory of the instruction decoding section responds to the third microaddress. outputs information instructing the next instruction decoding as a microinstruction, and the microaddress generation circuit outputs the information related to the condition determination in the first microinstruction and the instruction execution result generated from the instruction execution unit. In response to the above-mentioned related information, it is determined whether the condition for the conditional branch is met, and when the condition is met, the micro-address generation circuit generates the second micro-address as the next micro-address, and When the condition is not met, the microaddress generation circuit generates the third microaddress as the next microaddress, and the instruction decoder further: (2d) When the branch preparation instruction information and the condition are met, the microaddress generation circuit generates the third microaddress as the next microaddress. The method further comprises a signal analysis circuit that generates the branch instruction signal to be supplied to the branch control circuit of the instruction reading section in response to the second microaddress as the next microaddress generated from the second microaddress. Data processing equipment. 4. The microprocessor according to claim 3, wherein the signal analysis circuit generates the branch instruction signal in response to the LSB signal of the second microaddress.