JPH01271809A - Input abnormality detector for control pulse signal - Google Patents

Input abnormality detector for control pulse signal

Info

Publication number
JPH01271809A
JPH01271809A JP9986588A JP9986588A JPH01271809A JP H01271809 A JPH01271809 A JP H01271809A JP 9986588 A JP9986588 A JP 9986588A JP 9986588 A JP9986588 A JP 9986588A JP H01271809 A JPH01271809 A JP H01271809A
Authority
JP
Japan
Prior art keywords
detector
mask
signal
input
control pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9986588A
Other languages
Japanese (ja)
Inventor
Koji Watabe
渡部 耕児
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9986588A priority Critical patent/JPH01271809A/en
Publication of JPH01271809A publication Critical patent/JPH01271809A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To detect the input abnormality of a control pulse signal with high accuracy by forming a blind sector in accordance with a reference speed level and at the same time setting a delay time for detection of the abnormality in accordance with the reference speed level. CONSTITUTION:The reference speed level '1' is supplied to a blind sector arithmetic circuit 16 for calculation of a blind sector having its upper and lower limit levels. At the same time, a mask time arithmetic circuit 22 calculates a large mask time T1 against a low reference speed level and a small mask time T1 against a high reference speed level respectively in accordance with the level '1'. These mask times are applied to a mask detector 12. While a blind sector detector 18 checks the presence or absence of a difference signal 7 received from an input pulse number change component detector 6. If the difference value is included in a blind sector, the detector 18 transmits a normal detecting signal 19. The other normal detecting signal 15 is obtained when the input pulse number, i.e., the feedback value is equal to zero and at the same time the level '1' is not equal to zero. When these two conditions are satisfied, an AND circuit 20 transmits a normal detecting signal 21.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、パルス発振器から入力される制御パルス信
号によシ制御対象機器を制御する制御システムにおいて
、制御パルス信号の入力に異常があったことを検出する
制御パルス信号の入力異常検出装置に関するものである
[Detailed Description of the Invention] [Industrial Application Field] This invention is directed to a control system that controls a device to be controlled by a control pulse signal input from a pulse oscillator, in which there is an abnormality in the input of the control pulse signal. The present invention relates to a control pulse signal input abnormality detection device that detects this.

〔従来の技術〕[Conventional technology]

第3図は従来の制御パルス信号の入力異常検出装置を示
すブロック図であり、パルス発振器が取付けられた制御
対象機器に対して示されている速度基準値がゼロでない
にも拘らず、入力される制御パルス信号のパルス数が変
化しないことを検出することによシ、異常を検出するよ
うにしたものである。図において、1は制御対象機器に
出力されている速度基準値、2はその速度基準値1がゼ
ロでないことを検出する速度基準値キ0の検出器、3は
その検出信号、4は制御対象機器に今回の周期に入力さ
れた制御パルス信号のパルス数のカウント値を示す入力
パルス数カウント値の今回値、5は制御対象機器に前回
の周期に入力された制御パルス信号のパルス数のカウン
ト値を示す入力パルス数カウント値の前回値、6は今回
値4と前回値5との差の値から入力パルス数の変化分を
検出する検出器、7はその差の値を示す信号、8は差の
値を示す信号7がゼロ、即ち入力パルス数−0を検出す
る検出器、9はその検出信号、10は検出信号3,9が
加えられる論理積回路、11はその出力信号、12は所
定レベルの出力信号11が加えられてから所定のマスク
時間T1を経て出力信号110レベルを調べるマスク検
出器、13はその異常検出信号、14は異常検出信号を
反転するインバータ、15はインバータ14から得られ
る正常検出信号である。
FIG. 3 is a block diagram showing a conventional control pulse signal input abnormality detection device. The abnormality is detected by detecting that the number of pulses of the control pulse signal does not change. In the figure, 1 is the speed reference value output to the controlled device, 2 is the speed reference value key 0 detector that detects that the speed reference value 1 is not zero, 3 is its detection signal, and 4 is the controlled object The current value of the input pulse number count value that indicates the count value of the number of pulses of the control pulse signal input to the device in the current cycle, 5 is the count of the number of pulses of the control pulse signal input to the controlled device in the previous cycle 6 is a detector that detects the change in the number of input pulses from the difference between the current value 4 and the previous value 5; 7 is a signal indicating the value of the difference; 8 1 is a detector that detects that the signal 7 indicating the difference value is zero, that is, the number of input pulses minus 0; 9 is its detection signal; 10 is an AND circuit to which detection signals 3 and 9 are added; 11 is its output signal; 12 1 is a mask detector that checks the output signal 110 level after a predetermined mask time T1 after the output signal 11 of a predetermined level is applied; 13 is an abnormality detection signal; 14 is an inverter for inverting the abnormality detection signal; 15 is an inverter 14 This is the normal detection signal obtained from.

次に動作について説明する。Next, the operation will be explained.

制御対象機器に与えられている速度基準値1がゼロでな
いとき、検出器2は検出信号3を出力する。このとき検
出器6から出力される今回値4と前回値5との差の値を
示す信号7がゼロを示していると、検出器8は検出信号
9を出力する。このとき論理積回路10は、速度基準値
1がゼロでないのにも拘らず、フィードバック値である
入力パルス数がゼロであるという矛盾を示す例えばHレ
ベル(高レベル)の出力信号11を出力する。しかしな
がらこの場合、制御対象機器の応答遅れや、低速時にお
けるパルスインクリメントの巾等の原因によシ、正常時
でも入力パルス数がゼロとなることも考えられるので、
マスク検出器12において、出力信号11の立上りから
所定のマスク時間T1だけ遅延した時点での出力信号1
1のレベルを調べる。即ち、第4図に示すように所定の
マスク時間T1を経た時点で出力信号11のHレベルが
続いていれば異常と見なし、異常検出信号13を出力す
る。この異常検出信号13はインバータ14で反転され
て正常検出信号となる。
When the speed reference value 1 given to the controlled device is not zero, the detector 2 outputs a detection signal 3. At this time, if the signal 7 indicating the difference between the current value 4 and the previous value 5 output from the detector 6 indicates zero, the detector 8 outputs a detection signal 9. At this time, the AND circuit 10 outputs, for example, an H level (high level) output signal 11 indicating a contradiction that the number of input pulses, which is the feedback value, is zero even though the speed reference value 1 is not zero. . However, in this case, the number of input pulses may be zero even under normal conditions due to reasons such as response delay of the controlled device or the width of the pulse increment at low speeds.
In the mask detector 12, the output signal 1 is detected at a time point delayed by a predetermined mask time T1 from the rise of the output signal 11.
Check the level of 1. That is, as shown in FIG. 4, if the output signal 11 continues to be at the H level after a predetermined mask time T1, it is regarded as abnormal, and the abnormality detection signal 13 is output. This abnormality detection signal 13 is inverted by an inverter 14 and becomes a normal detection signal.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の制御パルス信号の入力異常検出装置は以上のよう
に構成されているので、速度基準値1がゼロでない場合
に、フィードバック値となる入力パルス数がゼロとなっ
た場合のみの異常しか検出することができず、またマス
ク検出器12に与えられるマスク時間T1も一定である
ため、種々の大きさの速度基準値1に対応することがで
きず、特に高速基準値の場合に異常検出が遅れるなどの
問題点があった。
Since the conventional control pulse signal input abnormality detection device is configured as described above, it detects an abnormality only when the number of input pulses serving as the feedback value becomes zero when the speed reference value 1 is not zero. Moreover, since the mask time T1 given to the mask detector 12 is constant, it is not possible to deal with speed reference values 1 of various sizes, and abnormality detection is delayed especially in the case of a high speed reference value. There were problems such as:

この発明は上記のような問題点を解消するためになされ
たもので、入力パルス数がゼロ以外のときでも、異常検
出が行えると共に、制御対象機器に示される種々の速度
基準値に応じて即応性のある検出を行うことのできる制
御パルス信号の入力異常検出装置を得ることを目的とす
る。
This invention was made in order to solve the above-mentioned problems, and it is possible to detect abnormalities even when the number of input pulses is other than zero, and to take prompt action according to various speed reference values indicated on the controlled equipment. The present invention aims to provide a control pulse signal input abnormality detection device that can perform accurate detection.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る制御パルス信号の入力異常検出装置は、
速度基準値に応じて制御系に不感帯を設定すると共にマ
スク時間を可変と成し、入力パルス数の変化が不感帯に
あるときは正常と見なすようにしたものである。
The control pulse signal input abnormality detection device according to the present invention includes:
A dead zone is set in the control system according to the speed reference value, and the mask time is made variable, so that when the change in the number of input pulses is within the dead zone, it is considered normal.

〔作 用〕[For production]

この発明における制御パルス信号の入力異常検出装置は
、速度基準値と入力パルス数との相関関係が常にチエツ
クされながら異常検出が行われると共に、速度基準値に
応じた即応性のある異常検出が行われる。
The control pulse signal input abnormality detection device of the present invention performs abnormality detection while constantly checking the correlation between the speed reference value and the number of input pulses, and also performs immediate abnormality detection according to the speed reference value. be exposed.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第1
図において、1〜15は第3図の同一符号部分と同一で
あるので説明を省略する。ただし、マスク検出器12に
与えられるマスク時間Tlは後述するマスク時間演算回
路22によシ可変となっている。第1図において、16
は不感帯演算回路で、与えられた速度基準値1を中心と
する不感帯が演算される。17はその不感帯を示す信号
、18は検出器6から得られる今回値4と前回値5との
差の値を示す信号7と不感帯を示す信号17とを比較し
て、差の値が不感帯に入っているか否かを調べる不感帯
検出器、19は差の値が不感帯に入っているときに出力
される正常検出信号、20は正常検出信号19と前述し
た正常検出信号15とが加えられる論理積回路、21は
論理積回路20から出力される真の正常検出信号、−2
2は与えられた速度基準値1に応じた長さのマスク時間
T1を算出するマスク時間演算回路である。
An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 to 15 are the same as the same reference numerals in FIG. 3, so their explanation will be omitted. However, the mask time Tl given to the mask detector 12 is variable by a mask time calculation circuit 22, which will be described later. In Figure 1, 16
is a dead zone calculation circuit, which calculates a dead zone centered around the given speed reference value 1. 17 is a signal indicating the dead zone, and 18 is a signal 7 indicating the difference between the current value 4 and the previous value 5 obtained from the detector 6 and the signal 17 indicating the dead zone, and the difference value is determined to be in the dead zone. 19 is a normal detection signal that is output when the difference value is within the dead band; 20 is a logical product in which the normal detection signal 19 and the above-mentioned normal detection signal 15 are added; circuit, 21 is a true normal detection signal output from the AND circuit 20, -2
Reference numeral 2 denotes a mask time calculation circuit that calculates a mask time T1 having a length corresponding to the given speed reference value 1.

次に動作について説明する。Next, the operation will be explained.

不感帯演算回路16には、パルス発振器が設けられた制
御対象機器に与えられる速度基準値1が入力される。こ
の速度基準値1は制御パルス信号のパルス数に換算され
、その換算値に正及び負の余裕量が足されることによυ
、下限値と上限値とを有する不感帯が算出される。これ
と共にマスク時間演算回路22は、速度基準値1に応じ
て、低速基準値に対しては長いマスク時間T1を算出す
ると共に、高速基準値に対しては短いマスク時間゛Pl
を算出して、マスク検出器12に加える。従って、第2
図にも示すように、マスク時間T1が速度に応じて変化
するので、制御対象機器の応答遅れや、低速時のパルス
のインクリメント巾等に起因して、正常であるにも拘ら
ず異常検出信号13が出力されてしまうことを防止する
ことができる。
A speed reference value 1 given to a controlled device provided with a pulse oscillator is input to the dead zone calculation circuit 16 . This speed reference value 1 is converted to the number of pulses of the control pulse signal, and the positive and negative margins are added to the converted value, so that υ
, a dead zone having a lower limit value and an upper limit value is calculated. At the same time, according to the speed reference value 1, the mask time calculation circuit 22 calculates a long mask time T1 for the low speed reference value, and a short mask time T1 for the high speed reference value.
is calculated and added to the mask detector 12. Therefore, the second
As shown in the figure, since the mask time T1 changes depending on the speed, an abnormality detection signal may be generated even though it is normal due to the response delay of the controlled device or the increment width of the pulse at low speeds. 13 can be prevented from being output.

一方、不感帯検出器18は、検出器6からの差の値を示
す信号7が不感帯に入っているか否かを調べ、差の値が
不感帯に入っていれば正常検出信号19を出力する。ま
た他方の正常検出信号15は、速度基準値1がゼロでな
い場合にフィードバック値である入力パルス数がゼロと
なったときに得られる。従って、論理積回路20はこれ
らの2つの条件が得られたときに真の正常検出信号21
を出力する。
On the other hand, the dead zone detector 18 checks whether the signal 7 indicating the difference value from the detector 6 is within the dead zone, and outputs a normal detection signal 19 if the difference value is within the dead zone. The other normality detection signal 15 is obtained when the number of input pulses, which is the feedback value, becomes zero when the speed reference value 1 is not zero. Therefore, the AND circuit 20 outputs the true normal detection signal 21 when these two conditions are obtained.
Output.

なお、上記実施例では、2つの正常検出信号19゜15
を論理積回路20に加えているが、正常検出信号19を
反転した信号と異常検出信号13とを論理和回路に加え
て、異常検出信号を得るようにしてもよい。また検出器
6においては今回値4と前回値5との差を求めているが
、この検出器6としては、一定周期内の制御パルス信号
をカウントできるものであればよい。
In the above embodiment, two normal detection signals 19°15
is added to the AND circuit 20, however, the abnormality detection signal may be obtained by adding a signal obtained by inverting the normality detection signal 19 and the abnormality detection signal 13 to the OR circuit. Further, the detector 6 calculates the difference between the current value 4 and the previous value 5, but this detector 6 may be of any type as long as it can count control pulse signals within a fixed period.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、速度基準値に応じた
大きさの不感帯を設けると共に、速度基準値に応じた異
常検出の遅れ時間(マスク時間)を設けるように構成し
たので、常に速度基準値と入力パルス数との相関関係が
チエツクされながら検出が行われ、壕だ入力パルス数が
ゼロ以外の場合でも異常検出を行うことができ、さらに
入力パルス数がゼロになったときは、即応性のある検出
が行われるので、精度の良い検出を行うことができる効
果がある。
As described above, according to the present invention, a dead zone of a size corresponding to the speed reference value is provided, and a delay time (mask time) for abnormality detection is provided depending on the speed reference value. Detection is performed while checking the correlation between the reference value and the number of input pulses, and abnormality detection can be performed even when the number of input pulses is other than zero. Furthermore, when the number of input pulses becomes zero, Since the detection is performed with a quick response, there is an effect that the detection can be performed with high precision.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例による制御パルス信号の入
力異常検出装置を示すブロック図、第2図は同装置にお
けるマスク検出に関するタイムチャート、第3図は従来
の制御パルス信号の入力異常検出装置を示すブロック図
、第4図は同装置のマスク検出に関するタイムチャート
である。 1は速度基準値、2は速度基準値4oの検出器、6は入
力パルス数変化分の検出器、8は入力パルス数二〇の検
出器、12はマスク検出器、16は不感帯演算回路、1
8は不感帯検出器、22はマスク時間演算回路。 なお、図中、同一符号は同一、又は相当部分を示す。 特許出願人  三菱電機株式会社
FIG. 1 is a block diagram showing a control pulse signal input abnormality detection device according to an embodiment of the present invention, FIG. 2 is a time chart regarding mask detection in the same device, and FIG. 3 is a conventional control pulse signal input abnormality detection device. A block diagram showing the apparatus, and FIG. 4 is a time chart regarding mask detection of the apparatus. 1 is a speed reference value, 2 is a detector for a speed reference value of 4o, 6 is a detector for a change in the number of input pulses, 8 is a detector for an input pulse number of 20, 12 is a mask detector, 16 is a dead zone calculation circuit, 1
8 is a dead zone detector, and 22 is a mask time calculation circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant Mitsubishi Electric Corporation

Claims (1)

【特許請求の範囲】[Claims]  制御パルス信号により制御される制御対象機器に与え
られる速度基準値に応じた大きさの不感帯を算出する不
感帯演算回路と、所定の周期における制御パルス信号の
入力パルス数の変化分を検出する検出器と、上記入力パ
ルスの変化分と上記不感帯とを比較する不感帯検出器と
、上記速度基準値が与えられ、かつ上記入力パルス数の
変化分がなかつたことを所定のマスク時間を経てから検
出するマスク検出器と、上記速度基準値に応じて上記マ
スク時間を算出するマスク時間演算回路とを備えた制御
パルス備考の入力異常検出装置。
A dead zone calculation circuit that calculates a dead zone of a size corresponding to a speed reference value given to a controlled device controlled by a control pulse signal, and a detector that detects a change in the number of input pulses of the control pulse signal in a predetermined period. and a dead zone detector that compares the change in the input pulse with the dead zone, and detects after a predetermined mask time that the speed reference value is given and there is no change in the number of input pulses. An input abnormality detection device for control pulse notes, comprising a mask detector and a mask time calculation circuit that calculates the mask time according to the speed reference value.
JP9986588A 1988-04-22 1988-04-22 Input abnormality detector for control pulse signal Pending JPH01271809A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9986588A JPH01271809A (en) 1988-04-22 1988-04-22 Input abnormality detector for control pulse signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9986588A JPH01271809A (en) 1988-04-22 1988-04-22 Input abnormality detector for control pulse signal

Publications (1)

Publication Number Publication Date
JPH01271809A true JPH01271809A (en) 1989-10-30

Family

ID=14258700

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9986588A Pending JPH01271809A (en) 1988-04-22 1988-04-22 Input abnormality detector for control pulse signal

Country Status (1)

Country Link
JP (1) JPH01271809A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009015539A (en) * 2007-07-04 2009-01-22 Toyota Industries Corp Information transmission method in automated guided vehicle

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009015539A (en) * 2007-07-04 2009-01-22 Toyota Industries Corp Information transmission method in automated guided vehicle

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