JPH01268329A - Code converter - Google Patents

Abstract

PURPOSE:To convert a signal having a jitter to other code without an error and surely, and simultaneously, to generate a receiving clock by providing an edge interval deciding circuit for deciding an edge interval of a pulse edge. CONSTITUTION:An edge of rise and fall of a pulse signal 1e of a prescribed code which has been transmitted is detected and decided by a pulse edge rise/fall detecting and deciding circuit 1a, and from a pulse edge which has been detected and decided, its edge interval is decided by an edge interval deciding circuit 1b. Subsequently, from the edge interval which has been decided, a data sampling timing is generated by a data sampling timing generating circuit 1c, receiving data is brought to sampling by a sampling circuit 1d, and a signal which has converted the pulse signal to other code, and a receiving clock are obtained. In such a way, for instance, a Manchester code signal containing a jitter is converted to other code signal such as an NRZ(Non Return to Zero) code signal, etc., and also, the receiving clock can be made simultaneously.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a code conversion device that converts a digital signal code in which the edge of a signal pulse fluctuates over time due to jitter into a signal code of another system. .

[Conventional technology]

For example, "Fundamentals and Practice of Microcomputer Data Transmission J" (Published by CQ Publishing Co., Ltd., Publication date: January 1980)
(October 30), pages 187 to 189 discuss the problem of transmission errors and loss of synchronization caused by jitter (phase fluctuation) due to waveform distortion when transmitting digital data (binary information).

FIG. 2 is a waveform diagram for explaining such a problem. In the diagram, 2a is a certain data stream, 2b is this data stream 2a expressed in Manchester code,
2a is NRZ (N
on Return to Zero) code.

Manchester code 2b is an interface code for transferring binary information between transmitting and receiving devices, and is a signal containing synchronization timing information. To convert this Manchester code into an NRZ code, it is sufficient to make the rising and falling edges of the synchronization timing (center part of the bit signal) correspond to "1" and 901 of the NRZ code.

Next, to explain the operation when converting a signal based on Manchester code 2b into a signal based on NRZ code 2c, a signal pattern @1010...10@ (preamplifier The synchronization timing is recognized on the receiving side by adding Here, the pulse repetition period at this time is defined as T. Also, in Manchester code 2b in Figure 2, 110
The pulse when it becomes 1 or 1011 is Long Pis%
5hort pulse when '11 or 101 is continuous
Define Pis. At this synchronization timing, data sent thereafter can be sampled and converted into an NRZ code.

[Problem to be solved by the invention]

However, the transmitted good signal contains jitter due to the influence of the transmission path, noise, code amount interference, and the performance of the transmitter/receiver. When the jitter becomes large, there is a problem in that the synchronization timing created by the preamplifier section makes it impossible to reproduce the transmitted good signal on the receiving side.

This invention was made to solve the above-mentioned problems, and it is possible to erroneously convert a transmitted signal expressed by a predetermined code with jitter of up to T/4 (T is synchronization) into another code. It is an object of the present invention to provide a code converting device that can reliably convert data and generate a reception clock at the same time.

[Means to solve the problem]

The code conversion device according to the present invention includes a pulse edge rising/falling edge detection/judgment circuit for detecting and judging the rising edge υ and falling edge of a transmitted pulse signal, and a pulse edge edge detecting/judgment circuit for detecting and judging the rising edge υ and falling edge of a transmitted pulse signal. The pulse signal is generated by an edge interval determination circuit that determines the interval, a data sampling timing generation circuit that generates data sampling timing from the edge interval determined by this circuit, and a sampling circuit that samples data based on the data sampling timing of this circuit. This is to obtain a signal converted into another code and a reception clock.

[Effect]

The rising edge of the transmitted pulse signal of a predetermined code.

A falling edge is detected and determined by a pulse edge rising/falling edge detection and determination circuit, and an edge interval determination circuit then determines the edge interval from the detected and determined pulse edge. Data sampling timing is then generated from the determined edge interval, data is sampled using this data sampling timing, and a signal obtained by converting the pulse signal into another code and a reception clock are obtained.

〔Example〕

An embodiment of the present invention will be described with reference to the drawings. In FIG. 1, la is a pulse edge rising/falling detection/determination circuit based on an input signal 1e expressed by Manchester code, and 1b is a pulse edge detection/determination circuit whose edge interval is Long Pls.
1c is a data sampling timing generation circuit that generates data sampling timing to obtain the NRZ code; 1d is a data sampling timing generation circuit that generates the received data using six timings. This is a sampling circuit that performs sampling. And 1f is an NRZ code signal.

FIG. 3 shows the pulse edge rising and falling edge detection judgment circuit 1.
This figure shows a specific circuit of &, in which 3a is a clock signal and its clock period is T/16. Ma7'
j 3b e3c, aci +3e is D type flip 7
0 Tsubu, 3f, 3g are AND gates, 3h is an AND gate 3f, an OR gate that inputs the output signal of 3g, 31 is an output signal of ant game) 3f, 3j is an output signal of OR game) 3h, 3 is an AND gate 3g output signal of 31.
3m s 3 n e 3Q are each flip flop o
These are the Q output signal, the Q output signal, the Q output signal, and the Q output signal of y-p 3b, 3e=3d-3e.

FIG. 4 is a time chart of signals at various parts of the circuit shown in FIG.

FIG. 5 shows a specific circuit of the edge interval determination circuit 1b. In the figure, 5a is a programmable counter section, 5b-5f
, 5 to 5m + 5Q, 5z is a D-type 7 rig flop,
5g to 5j, 51.5p to 5te5w, 5x are AND gates, 5n, 5u*5v are OR gates, and 5y is an SR type flip 70 tube. Further, 5al-5a5 are output signals of the programmable counter section 5a, which are respectively input to the D input terminals of the seven lip-flops 5b to 5f. Also 5bl, 5c1.5f1.5kl.

5m1. *5Q1 *5zl are each flip-flop sb.

5c+5f*5, each Q output signal of 5m*5Q, 5z,
5al.

shx, stl, sjx, 511 are output signals of AND gates 5g, 5h, 5i, sj, si, respectively, 5nl, 5ul *5vl are OR game)
This is an output signal of 5n+5u, 5v.

FIG. 6 is a time chart of signals from various parts of the edge interval determination circuit 1b shown in FIG.

FIG. 7 shows a specific circuit of the data sampling timing generation circuit 1c. In the figure, 7a is a LongPig signal,
7b is a 1/2 clock delay element, IC is an l clock delay element, 7d, 7e, and 7f are D-type flip-flops,
7g is an AND gate, 7h is an OR gate, 7i is an or game) 7h's output signal, 7k.

7 m s 7 n are flip-flops 7 d
+7e.

7f Q output signal, Q output signal, and Q output signal. 7
1 is also the output signal of the AND gate 7g.

FIG. 8 is a time chart of signals from various parts of the friend data sampling timing generation circuit 1c shown in FIG. 7.

FIG. 9 shows a specific circuit of the sampling circuit 1d. In the figure, 9a is a counter, 9a1 is its count up signal, 9b*9cs9d are D-type flip-flops, 9e is an AND gate, and 9f is a data sampling timing signal.

Next, the operation of the above embodiment will be explained. First, the operation of the pulse edge rising/falling edge detection/determination circuit 1a will be explained with reference to the time chart of FIG.
When the Manchester code signal 1e is input to the D input terminals of the flip-flops 3b and 3d driven by the third
The signals of each section 31 etc. shown in the specific circuit shown in the figure are as shown in FIG. 4, and as a result, the signal 31. A signal 3k that detects the falling edge is obtained as a pulse signal as shown in FIG. Note that the signal 3j is a composite signal (synthetic pulse) of the signals 3i and 3, and these are sent to the edge interval determination circuit 1b specifically shown in FIG.

However, in this edge interval determination circuit 1b, the sixth
The figure shows a time chart of each part, and this circuit 1b
By adding the signal 3j as a trigger to the programmable counter section 5a of the 5hort Pig and calculating the edge distance using the clock 3a, the 5hort
Pla signal 5 j 1 , L if Long Pl s
The ohg Pls signal 511 is output as shown in the time chart of FIG. In addition, when the edge distance is around 0.75T, the discrimination circuit 5z selects 5hort Pig(0
,75T) signal 5ul and Long Pig (0,75
T) Outputs a signal of 5vl. Also, 5al is 5hor
The signal Shor indicates that it is the t section, and the signal 5hl is a Long signal that indicates that it is the Long section. Also, if it is neither Short nor Long, Err
(Error) Outputs signal 5nl. Output signal 5al e 5a2 of programmable counter section 5a.

5a355a4.5a5 are r4J and r12J, respectively
, rlOJ, r16J.

This is a "20" count up signal.

Next, a data sampling timing generation circuit 1c specifically shown in FIG. 7 generates data sampling timing. In the figure, 7a is the LongP1m signal, when the signal 5i1 is 111, it is the signal 5vl, when it is part 01, the signal 5kl is the 5hort signal, when the signal 511 is 111, it is the signal 5u2, and when it is '0'', it is the signal 5kl. It represents the signal 5kl.Then, the 1/2 clock delay element 7b, the 1 clock delay element Tc5D type flip 7
The circuit of 7d, 7e, 7f, 7g, 7h, or 7h outputs the clock signal 71 for data sampling at that timing if it is a Long Plg, as shown in Figure 8, and the 5hort Plg is When continuing, a data sampling clock reset signal (CLK R8T) is output for every even numbered bit. However, this is limited to the case where the clock was not reset at 5hort Pla last time as well. FIG. 8 shows the relationship between these signals for a certain data stream.

Next, in the sampling circuit 1d shown in FIG.
Using the R8T signal, data is sampled from the Manchester code signal and an NRZ code signal is output. When the counter 9a counts up a certain set value, it outputs a count-up signal 9al. This signal 9
Use the data sampling timing signal 9f using al, sample the data at this timing, and
At the same time as obtaining the RZ code signal, the data sampling timing signal 9f is used as a reception clock.

In the above embodiment, the case of Manchester code is explained, but the same effect can be achieved with other codes by the same method.

〔Effect of the invention〕

As described above, according to the present invention, a code converter converts a jitter-containing, for example, Manchester code signal into, for example, N
Since the configuration is configured such that a reception clock can be generated at the same time as converting into another code signal such as an RZ code signal, a highly reliable code conversion device can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a code converter according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing the relationship between Manchester code and NRZ code, and FIG. 3 is a pulse edge rising/falling edge detection/determination circuit. Circuit diagram, Figure 4 is the operating waveform diagram of Figure 3,
5 is a circuit diagram of the edge interval determination circuit, FIG. 6 is an operating waveform diagram of FIG. 5, FIG. 7 is a circuit diagram of the data sampling timing generation circuit, and FIG. 8 is an operating waveform diagram of FIG. 9
The figure is a circuit diagram of a sampling circuit. 1a is a pulse edge rising/falling detection determination circuit, 1b is an edge interval determination circuit, lc is a data sampling timing generation circuit, and 1d is a sampling circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Patent applicant: Mitsubishi Electric Corporation, (2 others) Figure 1 Figure 2 Figure 3 a Figure 4 Figure 3

Claims (1)

[Claims] A pulse edge rising/falling detection/determination circuit that detects and determines the rising edge and falling edge of a pulse signal, and whether or not the edge interval of the pulse edges detected and determined by this pulse edge rising/falling detection/judgment circuit is within a predetermined range. an edge interval determination circuit that determines the edge interval, a data sampling timing generation circuit that generates data sampling timing based on the edge interval determined by the edge interval determination circuit, and a data sampling timing generation circuit that generates the data sampling timing based on the data sampling timing generation circuit. A code conversion device comprising a sampling circuit that samples data.