JPH01267694A - Active matrix type display device, its scanning circuit, and driving circuit for scanning circuit - Google Patents

Abstract

PURPOSE:To put a matrix switch in normal operation even when the switch is composed of a-silicon transistors (TR) which rise slowly by driving scanning electrodes correctly even when selection periods of respective blocks overlap one another and making the selection period of one scanning electrode line long. CONSTITUTION:Terminals A1, A2...An, and An+1 are supplied with a selective scanning signal which is repeated in order; and a H level is supplied to a terminal B2 and a L level is supplied to a terminal C2 while or a little bit before the terminal An+1 rises to the H level for the 1st time. Then (n) scanning MOS TRs M(n+1), M(n+2)...M(2n) of a 2nd block are turned on and (n) MOS TRs N(n+1), N(n+2)...N(2n) are turned off. This state is continued until the select signal applied to the terminal An-1 falls to select scanning electrodes S(n+1), S(n+2)...S(2n) of the 2nd block in order. Consequently, even when the a-Si TRs which rise slowly are used, a scanning circuit which drives scanning electrode lines is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in the scanning circuit of an active matrix display device having switching display and display elements arranged in a matrix.

[Conventional technology]

A method for reducing the number of connection lines between an active matrix board and an external drive circuit and for reducing the size of the board is described in Japanese Patent Laid-Open No. 58-1.
It is described in No. 27991. In this system, the scanning electrode driving section is constructed from an IJ switch and is built into an active matrix substrate. The scanning circuit described here is divided into m blocks each having b scanning electrode lines, and the drain of a MOS transistor is connected to each scanning electrode line. Then, the selection and selection of mxs scanning electrodes is performed using a signal input to each of m drive terminals connecting the gate of the transistor and a signal input to each of one drive terminal connecting the source of the transistor. The structure was such that it was possible to decide whether or not to choose.

[Problem to be solved by the invention]

The above-mentioned conventional technology does not consider lengthening the scan electrode selection period when driving the scan electrode using a transistor such as α-5i which has a slow rise. For this reason, in the above-mentioned prior art, the 1
If you lengthen the period of two selection signals, the first selection signal and the second selection signal will overlap, so in the overlapping area of the block, the first and second scanning electrode lines of the block will be at the beginning of one scanning period of the block. Finally, they are selected simultaneously, making it impossible to lengthen the scanning electrode selection period. For this reason, there is a problem in that a transistor with a slow rise cannot drive the scan electrode.

SUMMARY OF THE INVENTION An object of the present invention is to provide a scanning circuit that has a circuit configuration that can lengthen the scanning electrode selection period and can drive scanning electrode lines even when using an α-5i l transistor with a slow rise. .

[Means to solve the problem]

The above purpose is to increase the number of drive terminals to which scan electrode selection signals are applied than the number of scan electrode lines belonging to one block, and to This is achieved by not using the drive terminal for applying the scan electrode selection signal in the other block, but by using another drive terminal.

[Effect]

The period of the scanning electrode selection signal input to each of the +1 or more drive terminals can be made longer than the period of the selection signal input to the nine drive terminals.

In other words, even if the scan electrode selection period is lengthened, the overlapping portion of the fourth scan electrode line selection signal in the same block and the next selection signal of the drive terminal to which the first scan electrode selection signal is applied is , can be eliminated. Therefore, even if adjacent block selection periods overlap, the wrong scanning electrode will not be selected.

〔Example〕

Hereinafter, one embodiment of the present invention will be explained with reference to FIG.
kl, N(kl (A = 1.2.-・nan
) is an N-type MOS transistor, and 5(k) is a scan electrode of an active matrix substrate, which is divided into m blocks each having one scan electrode. In addition, terminal Ai*E
)' + C) rVzoff (i = 1+lL
'=''' n, a+1, j=1+2+"""J is the application terminal of the drive signal of this scanning circuit.

The operation of the embodiment shown in FIG. 1 will be explained using a second example of operation waveforms.

The signal levels "H" and =L' shown in FIG. 2 are relative for each terminal, and some terminals may have different voltage amplitudes. Regarding the waveform of terminal Al,
Scan electrode selection voltage is at °H” level, non-selection voltage is at “L” level.
It is shown as a level. Terminal Bi.

Regarding the waveform of C1, the scanning MO5) transistor M(k) and the non-select potential fixing MO5 transistor N(
The gate voltage at which Al is turned on is shown as "H" level, and the gate voltage at which Al is turned off is shown at °L level.

In the initial state, terminal Bl r B, l, song, 1
3pc is supplied with °L° level, for all scans, w
os transistor J/fll, M f21,
...=-, M (mn) is in the off state. Terminal C1
+ C2, .
#(21, −・−, N (mn) is in the on state,
The scanning electrode non-selection potential (indicated as "L" level in Fig. 2) applied to terminal 1"gaff is applied to scanning electrode gas (1).
, S f21 ,...

S (na). Next, the “H° level” is applied to terminal B1.

When the "L" level is input to the terminal C1, the nine scanning MOS transistors Mfl+, 31 of the first block
(21.

..., M(rc) is turned on, and one non-selected potential fixing MO5) transistor N(ll, #(2+)
, ..., #(31 are turned off. As a result, the scan electrode selection signals applied to the terminals A1, A2, . . . An are applied to the scan electrode lines S (1), S of the first block.
(21, -, S (il) 6 Scanning electrodes other than the first block 1! S (n + 1).

S(+2), . . . , 5caF&> continues to output the scanning electrode non-selection potential (°L level) in its initial state.

At this time, terminal A1. A2. . . . When a sequential selection scanning signal as shown in the waveform example of FIG. 2 is given to An,
Nine scanning MO5) Rungis II M in on state
(11,M (21,-,M

Next, by giving terminals B, K'L level and terminals C, K'H° level, nine scanning MO5) transistors M[1
1, M (21, ..., M (+sl is turned off,
Nine unselected potential fixing transistors N (1),
N (21, -, N (When rLl is turned on, the "H° level" is applied to terminal B again.

Until a signal of "L° level" is applied to the terminal C1, the scanning electrode lines 5 (11, 5 (
21, . . . , s is kept at a non-selection potential.

Here, the terminal j 1 + A 2 * ・” + An,
A sequentially repeated selection scanning signal is applied to A3+t, and when terminal A1+1 first becomes "H" level, almost simultaneously or slightly earlier, terminal E becomes "H° level".
Apply the "L° level to terminal C1, and connect the nine scanning MO5) transistors y(+1) 1M(rL+2) of the second block.
), .
2) +・=...+# (2rb) is turned off. By continuing this state until the selection signal applied to the terminal An-1 falls, the terminal A3++.

The scanning electrodes S(n+1), 5(n+
2).

5 (2s) are selected sequentially, and in the third block, the terminals An, A++, A1 . ..., scanning electrode 5C2n+1> by sequential selection signals applied to A2
.

5(2+s+2), . . . , 5(Sn) are selected in sequence, and the terminals At, A2, . . .
・The period in which the selection signal is applied repeatedly to + A z + 1 and the selection signal is applied to nine terminals among them is defined as the selection period for one block, and the MO5) transistor for scanning is turned on during that period. The signals to set the state are sequentially sent to the terminals E1. By applying voltage to E2...B, the total number of times nine scanning electrodes S (11.

5(21,-, S CyLrb) is driven. At this time, terminal c1.

C2, . . . -, Crs have respective terminals E1 . B2. ..., a signal of a different level from the signal input to Er1L is applied. Here, terminal A1. A2. ....

A, +1 for a period longer than the time difference between the selection signals applied to adjacent terminals Aj, A2 . ... + J n + K selection signal is applied, the selection signals are overlapped, and
That period.

A driving method is used in which two blocks are selected at the same time.

FIG. 3 is an example of a circuit for forming the signals that drive the embodiment of FIG. 1 is a shift register with a +1 output, 2 is an external frequency divider, 3 is a shift register with a -1 output, 4 is a latch, R is a reset terminal or a data terminal, and CX is a clock terminal. Note that the terminals ('1, C2, -) necessary for driving the embodiment shown in FIG.

Although the signal formation of CS is omitted in the operational circuit example of FIG. 3, the signal formation of terminals B1. B2. . . . can be easily obtained by inverting the signal for Era using an inverter or the like.

FIG. 4 shows an example of the operating waveforms of the example pivot circuit shown in FIG. 3, and the operation of this circuit will be briefly described. The vertical synchronizing signal Vzync is used as a scanning start signal for the shift register 1.3, and the horizontal synchronizing signal Hzync is set at a period of 1°/1 minute of the shift register 2.3. It is used as a clock for latch 4. Terminal A1. A2.・
...The waveform of I A'3 is obtained from shift register 1. The clock of shift register /3 has a period of b minutes, 2
The output P1 of is used. Terminal B1. B2. ..., Eyx
The waveform is the output P2 of the latch whose data is the output D1 of the 3-minute cycle and the output of the shift register 6; , Q;, .
Formed from Q2.

In the embodiment of FIG. 1, the number of scanning electrodes in one block is one, whereas the number of scanning electrodes in one block is +1 terminals AI, j2.
... Since the driving method is to repeatedly apply selection signals to IA and S+1, two shift registers and one
The external division period is required.

Taking this point into consideration, FIG. 5 shows a scanning circuit that does not require a one-minute cycle of four in the drive circuit.

Another embodiment of the invention is shown in FIG. Elements and terminals equivalent to those in FIG. 1 are given the same reference numerals.

The difference from Fig. 1 is that except for the terminals Ar and +1, the terminals AI
' and terminal 4, connect the source of the first scanning transistor of the odd-numbered block to A1, the source of the second scanning transistor to AU, and connect the first scanning transistor of the even-numbered block to A1. The drain of the moon scanning transistor is connected to the terminal , l, the drain of the fourth scanning transistor is connected to the terminal Ar:, and the drains of the second to first scanning transistors are always connected to the terminals, (
(21, AI3+.

...This is the point connected to A (9-1).

The operation of the embodiment shown in FIG. 5 will be explained using the example of operation waveforms shown in FIG. First, next to the initial state [%n+2 terminals, 41
, A'1. A2. ...+ Ar, , A'n, nine terminals A1 . . . excluding terminals A'1 and A'2. A2
．． . . . sequentially apply selection signals to A-U.

Next, instead of terminal Aj, A, terminal A'1,
A', using terminal A'1 + A2 + "' +
A selection signal is sequentially applied to 'n-+, A'B.

The above operations are repeated in sequence. Here, during the period when the "H" level is applied to the terminal B1 of the first block, the terminal A1.
A2. ...+A3, and the period when the "H" level is applied to the terminal B2 of the second block is the period in which the selection signals are sequentially applied to the terminals A"1, A'1, ...+A.
1>-1*A' This is the period in which selection signals are sequentially applied to 2B. Thereafter, the scanning electrodes 5 (11) are sequentially operated in the same manner as in the first block in the odd-numbered blocks and in the first block in the even-numbered blocks.

5 (21, . . . , 5Cmn) are sequentially driven. Fifth
In the embodiment shown in FIG. 1, two adjacent terminals B) and 13)' + I are simultaneously selected as °B level, and the period is equal to the adjacent terminals 41 and 4L+t.
is longer than the time difference between which the selection signals of terminals A1 and A2 . The width of the selection signal applied to each of the selection signals is within twice the time difference between the selection signals, and the scan electrodes 5(11, 5(21, . . . , 5(nl) are driven.

The operations of #(11, #(21, . . . , N(-) in FIG. 5 are the same as those in the embodiment shown in FIG. 1, so a description thereof will be omitted.

FIG. 7 is an example of a circuit for forming the signals that drive the embodiment of FIG. 3.5 is a shift register similar to that shown in FIG. 3, and 4 is a latch. Moreover, FIG. 8 shows its operating waveform.

Although it is very similar to the drive circuit in Figure 5, the external output shift registers also function as a B frequency divider, so the L divider 4 used in Figure 3 is not necessary. The feature is that the even block is determined by the output QB of the ratte 4. Terminal A1. A'1゜A2.・・・＋Ark
*The waveform of A'n is the shift register 2 and latte 4.
is formed by the output QE of terminal B1. The waveforms of A2...B1 are the output Qt' of shift register 3, Qt'...Q
'rn-1 and the output Q of the shift register 2.

The waveforms of terminals CI, C2-C, and terminals f11,
B2-Br& is omitted because it can be easily obtained by inverting the paper using an inverter or the like.

The embodiment shown in FIG. 5 requires one more terminal than the embodiment shown in FIG. 1, but the drive circuit is simpler.

FIG. 9 is a circuit diagram of a scanning circuit showing another embodiment of the present invention. The difference from the embodiment shown in FIG. 1 is that a terminal A1+2 is added and a scanning transistor M(II, M(2)
The sources of M(,,F&) are sequentially connected to terminals A1. A2...A
, +□. FIG. 10K shows an example of the operation waveforms in FIG. 9. Terminal E1. B2. ... Scanning transistor M(1) connected to B, j/(2),...
・The number of 1M (11&ru) is 4 each, which is the same as the embodiment shown in FIG. 1. However, the number of terminals A1. A2. ...An+
A selection signal is repeatedly applied to +, A, and +2 in sequence. From this, in the embodiment of FIG. 9, adjacent terminals Bj and B, +1
The period in which adjacent terminals A! and A! can be set to "H" level simultaneously is defined as Since the time difference between the selection signals applied to terminals A1 and Ai++ can be doubled, the time difference between the selection signals applied to terminals A1. A2...An+2
The selection signal period applied to each of the scanning electrodes 5(1), 5(21,
...The selection period of each S (mF&) can be tripled, and even if the transistor has a slower rise than the scan transistor that can be driven in the embodiment shown in FIG.
+5(2), . . . S (yen) driving is possible.

#(11, #(21,...N) in the embodiment of FIG.
(The operation of - is the same as the embodiment shown in FIG. 1, so the explanation will be omitted.

Further, the circuit for forming the signal for driving the embodiment of FIG. 9 is as follows:
Since it is sufficient to simply replace the shift register 1 in FIG. 3 with a shift register with 1+2 outputs, the explanation will be omitted.

FIG. 11 shows scanning electrodes 5 (1), S (21, -, SC
A circuit diagram of a scanning circuit that drives the .nm) is shown.

In FIG. 11, the source of the first scanning transistor belonging to the odd-numbered block and the source of the second scanning transistor belonging to the even-numbered block KJi are connected to the terminal A1, and the source of the fourth scanning transistor belonging to the odd-numbered block is connected to the terminal A1. and the source of the first scanning transistor belonging to even-numbered block 2 are connected to terminal A. The other details are the same as in Figure 5.

A driving method according to an embodiment of the present invention using the circuit shown in FIG. 11 will be explained using an example of operating waveforms shown in FIG. 12. Terminal A1. A
2. ..., A, the selection signal applied to terminal AI,
Among the selection signals repeatedly and sequentially applied to A21..., A, the odd-numbered selection signal of terminal A and the terminal A1
and the even-numbered selection signals are collectively connected to terminal A.

The even-numbered selection signals of terminal A and the odd-numbered signals of terminal A1 are applied together as the selection signal of terminal A1, and the selection signals of terminal A1 and terminal A are applied together. I'll try not to. Here, the terminal B1 is given the °H" level from the same time or a little before the first selection signal is applied to the terminal A1 until the operating waveform of the scanning electrode S (+sl falls. , scanning electrode 5
The °H level is applied from the time when the operating waveform of (rL+1) starts to rise until the time when the scanning electrode 5 (2a) starts to fall. Thereafter, similar operations are performed in sequence. Terminal C (11, C
(2) , . . . , C(rpr) has terminals 1°B2 . ...
,B, and give different levels to each one. By driving the circuit of FIG. 11 using the operating waveform example shown in FIG. 12, the adjacent terminals nO) and B()+1)K are given as in the embodiment of FIG. ”
Even if the timings of the levels overlap, if the overlap is shorter than the time difference between the selection signals applied to the terminals At and A,+1, then the respective scanning electrodes 5 (11, 5+21
, . . , 5 (section 1) can be driven using a scanning transistor that is twice as necessary as the time difference, and the number of terminals can be reduced by one compared to the embodiment shown in FIG. Here, the fall of the scanning electrode in the part where the blocks overlap is the unselected potential fixing transistor #(11, N(21, . . . )
Do it with NC41.

FIG. 15 shows an example of a circuit for forming signals for driving the embodiment shown in FIG. 11, and FIG. 14 shows its operating waveforms.

Since the circuit example shown in FIG. 13 is almost the same as the circuit example shown in FIG. 7, a description of the operation will be omitted.

FIG. 15 shows nine unselected potential fixing transistors N(1), #(21, . . . , N(n
) instead of five resistors Rfil, R(21,...
・, R(+sl) is connected to one end of the 6IS resistors showing another embodiment of the present invention, to the scanning electrode lines 5(1), 5
+21, . . . , 5(n), and the other ends are connected together to one terminal VzofI.

The embodiment shown in FIG. 15 consumes more power due to the resistive load than the embodiment shown in FIG. ! In addition to the embodiment shown in Fig. 1, which requires only a small number of lines, the embodiment shown in Fig. 5, Fig. 9,
The nine unselected potential fixing transistors /N(1), N(21, . . . , #(a) in the embodiment shown in FIG.
As in the example shown in the figure, the resistance R(11, R(2), ・
..., 7? (It is also possible to replace it with at.

FIG. 16 shows a display panel incorporating the scanning circuit of the present invention. 12 is a display panel, 6 is one of the embodiments of the present invention shown in FIGS. 1, 5, 9, 11, and 15, and 7 is an active matrix display unit. It is.

FIG. 17 shows a display device using the display panel 12 shown in FIG. 16. 8 is a horizontal scanning circuit; 9 is a scanning circuit 6;
This is a drive circuit that forms a signal to be applied to the scanning circuit 6.
are the embodiments shown in FIGS. 1, 5, and 11, the drive circuit 9 is shown in FIG. 5, respectively.

The embodiments are shown in FIGS. 7 and 15. Note that it is also possible to use other drive circuits as the drive circuit 9.

FIG. 18 shows an embodiment of a display device constructed using a transistor with high mobility such as P-Si, which is a scanning circuit of the present invention, and built into a display panel.

2S is a display panel such as P-S i, 21 is a shift register that drives vertical scanning lines, 6 is a scanning circuit of the present invention, 9 is a signal that controls the shift register 21 and the scanning circuit 6, and a signal that is converted to AC. This is a control circuit that forms primary color signals. 10 is the scanning electrode line 5 (11, 5+21).

. . , a holding capacity of 5 (nrc). P-S i
For substrates with high mobility such as, the vertical scanning circuit has a fast operation speed, so it constitutes a shift register 1121 and drives the vertical scanning electrode lines G(1), G(21,..., G(gl). Furthermore, since faster operation, that is, higher mobility is required to configure the horizontal scanning circuit with a shift register, the operation speed may be slower than that of the shift register. Using the scanning circuit 6, the primary color signals R, G, and E are displayed on the screen in a dot sequential manner.

Note that the storage capacitor 10 can be replaced by the capacitance of a wiring or a transistor.

19, 20, and 21 are application examples using a display device 22 including the scanning circuit 6 of the present invention.

FIG. 19 shows a television, with an antenna 13. tuner 11
．． Circuit 14. Audio processing circuit 15. Primary color decoder 16° synchronous separation circuit 17. Gamma correction circuit 18 and display device 22
It consists of The explanation of its operation is omitted as it is the same as that of a normal television.

FIG. 20 shows an application example in which the display device 12 is used as a display of a device having a playback function. The difference from FIG. 19 is that the TV signal received by the antenna 13 is not used;
The point is that a video signal from a device with a playback function is used.

FIG. 22 shows an application example in which the display device 22 is used as a viewfinder of a video camera. 20 is a camera control circuit, 21 is an image pickup device, and 22 is a signal processing circuit, and a switch 23 switches the input video signal. A description of the operation of the embodiment shown in FIG. 22 will be omitted since it is similar to that of a well-known video camera.

〔Effect of the invention〕

According to the present invention, in a method in which a scanning circuit is built into an active matrix substrate by a method of driving a matrix switch for each block in order to reduce the number of connection lines between an active matrix substrate and an external drive circuit, each block is selected. The scan electrodes can be driven correctly even if the periods overlap, and the selection period for one scan electrode line can be made longer, so the matrix switch can operate normally even if it is configured with transistors such as α-silicon, which has a slow rise. It has the effect of working.

[Brief explanation of the drawing]

An example driving circuit diagram, FIG. 4 is an operating waveform diagram of the circuit shown in FIG. 3, FIG. 5 is a circuit diagram showing another embodiment of the present invention, and FIG. 6 is a diagram of the circuit shown in FIG. Operation waveform diagram of the circuit, No. 7
The figure is a circuit diagram driving the circuit shown in FIG. 5, FIG. 8 is an operation waveform diagram of the circuit shown in FIG. 7, FIG. 9 is a circuit diagram of another embodiment of the present invention, and FIG. The figures are an operation waveform diagram of the embodiment shown in Figure 9, Figure 11 is a circuit diagram of the scanning circuit, and Figure 12 is a circuit diagram of the scanning circuit.
11 is an operating waveform diagram of the circuit shown in FIG. 11, FIG. 13 is a signal forming circuit diagram of the circuit shown in FIG. 12, and FIG. 14 is an operating waveform diagram of the circuit shown in FIG. 13. FIG. 15 is a circuit diagram showing another embodiment of the present invention, FIG. 16 is a display panel diagram of the present invention, FIG. 17 is a diagram of a display device of the present invention, and FIG.
19 is a diagram showing a television set according to the present invention, FIG. 20 is a diagram showing a playback apparatus according to the present invention, and FIG.
The figure is a diagram of a video camera of the present invention. J/(11* Jf121 + ...1M (r&n
n), A'(11*A'(21,...,A'
(1111%)...MOS) Transistor 5(1), 5(21,...+SCmn)...Song/scanning electrode Rfll, RI2+,..., R(mle)...Resistance agent Patent attorney Masaru Ogawa Male No. j Figure Male 2 Figure 3 Figure 4 B3・H□... Hatake 5 Figure 6 5 (2^)・→←・→Me1・÷... Figure 7 8th B3-1 11→←−1←←su−−Ichi paper 9 figure Isamu 10 figure S gusi] 1,11n2 ″′・□□U No. 11 Figure 12 Figure 5 (2n+1)・→・→Twist 1・・B1 Snake 2 BB・’・・Jim man 1
5th episode 18th

Claims (1)

[Claims] 1. In a scanning circuit of an active matrix display device having a pixel consisting of a switch element and a display element at each intersection of a matrix constituted by a plurality of scanning electrodes and a plurality of signal electrodes, the scanning electrode At least one or more transistors each having a drain connected to the scan electrode are arranged, and the scan electrodes are divided into m blocks each having n scan electrodes, and a first set of m drive terminals, and n+1 the gates of the transistors in each block are commonly connected for each block and connected to one drive terminal group of the first set for each block. , the sources of the transistors in each block are connected to different drive terminal groups of the second set, and in each block, the sources of the n transistors are different from each other in at least one adjacent block. A scanning circuit for an active matrix display device, characterized in that the scanning circuit is connected to a second set of drive terminals. 2. The scanning circuit according to claim 1, further comprising a second set of n+1 drive terminals, and a second drive terminal group that is not connected in each block is sequentially changed. 3. Furthermore, it has a second set of n+2 drive terminals, and the sources of the second to (n-1)th transistors in each block are connected to the second to (n-1)th transistors of the second set of drive terminals. n-1)
The source of the first transistor that is connected to the first transistor and belongs to the odd-numbered block is connected to the first of the drive terminals of the second set, and the source of the first transistor is connected to the first of the drive terminals of the second set. The source of the first transistor connected to the second set and belonging to the even-numbered block is connected to the (n+1)th drive terminal of the second set, and the source of the first transistor is connected to the (n+2)th drive terminal. 2. The scanning circuit according to claim 1, further comprising: 4. The transistor is a first transistor, and the first
A plurality of second transistors are provided separately from the plurality of transistors, and the drains of the plurality of second transistors are connected to the drains of the plurality of first transistors and the scan electrode, respectively, and the sources of the plurality of second transistors are connected to the drains of the plurality of second transistors. are commonly connected to one fifth drive terminal, and the gate of one second transistor connected to the scanning electrode of each block is connected to a fourth set of drive terminals for each block. The scanning circuit according to claim 1, 2, or 5, characterized in that: 5. An active matrix method in which the drain of a switching transistor is connected to each of a plurality of scanning electrode lines, the plurality of transistors are grouped into a plurality of blocks, and each block is connected to a single common drive terminal. In the method for driving a scanning circuit of a display device, a signal is applied to the sources of the plurality of transistors to maintain an “H” level for a period longer than a time difference in which signals applied to the drains of adjacent transistors are at an “H” level; An active matrix type display device characterized in that a signal is applied to the gates of the plurality of transistors to keep the signal applied to the gates of the transistors of adjacent blocks at the "H" level for a period longer than the time difference between the signals being applied to the "H" level. How to drive a scanning circuit. 6. The display panel according to claim 1, wherein the transistor is formed in the same process as a transistor forming a pixel portion. 7. In an active matrix display device having a pixel consisting of a switch element and a display element at each intersection of a matrix constituted by a plurality of scanning electrodes and a plurality of signal electrodes, at least a transistor whose drain is connected to the signal electrode is provided. One or more drive terminals are provided, the signal electrodes are divided into one block each, and the first set of m drive terminals n+
Each signal electrode includes at least one first transistor having one or more second set of drive terminals, the drain of which is connected to the gate of the third transistor; The gates of the transistors are commonly connected for each block and connected to one drive terminal of the first set, and the sources of the first transistors in each block are respectively connected to different drive terminals of the second set. An active matrix display device characterized in that the source of one of the first transistors in each block is connected to at least one different drive terminal of a second set in an adjacent block.