JPH01267657A - Formation of mask for exposure - Google Patents

Abstract

PURPOSE:To shorten the time of data processing at the time of mask formation by performing logical processing and shift processing as to a pattern formed in the stage of the design of a basic type gate circuit, and exposing patterns of the basic type gate circuits in gate circuit units according to the arrangement addresses of the gate circuits. CONSTITUTION:Pattern data on (n) type impurity diffusion masks regarding plural kinds of basic type gate circuits 21-2n are read out respectively and the logical processing and shift processing of the data are carried out to correct an increase or decrease in thickness, etc., in a semiconductor circuit forming process. Then one of the basic type gate circuits 21-2n is read out and address data for arranging the gate circuit 2 on a mask substrate 5 is read out of arrangement design data. Then an electron beam is projected on the exposure start position of the address to expose the patterns for (n) type impurity diffusion, etc., on the substrate in gate circuit units, one by one. This operation is performed as to all of the remaining gate circuits 22-2n and thus the exposure scan of the pattern masks for (n) type impurity diffusion is completed. Then processes for development, etching, and resist removal are carried out to complete the mask.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for creating an exposure mask, the mask is created based on design data of a semiconductor circuit designed in multiple layers, with the aim of shortening the mask creation time. In the method for creating an exposure mask, data modification means performs logical processing and/or shift processing on a basic gate circuit pattern designed in one design layer of circuit pattern design, and a gate circuit pattern subjected to the data modification means. is configured to include a gate circuit exposure means for exposing the mask substrate in units of gate circuits based on the data of the basic type gate circuit layout address designed in another design hierarchy.

[Industrial application field]

The present invention relates to a method for creating an exposure mask, and more particularly, to a method for creating a mask that can simplify data processing when creating a mask used for manufacturing a semiconductor circuit or the like.

[Conventional technology]

When designing patterns for semiconductor integrated circuits such as gate array circuits, rather than patterning the entire integrated circuit at once, a basic circuit is extracted from the many gate circuits that make up the integrated circuit. After designing these patterns, the layout of the basic circuit is designed, thus increasing the efficiency of the design by dividing the integrated circuit into multiple layers.

These multiple PJIl! When creating a mask based on design data divided into 1 parts, a solid expansion is performed in which pattern design data and layout design data are combined.

The data obtained by this solid development is then used as pattern data for the entire integrated circuit, and the mask substrate is exposed all at once based on this data. It is necessary to take these phenomena into account and correct the data in advance.

For this reason, after completing the data processing using the solid pattern, shift processing is performed to predict the thickening or thinning of the pattern and correct the pattern data.

Also, when this shift process is performed, the patterns may be separated or
Since patterns that are not originally conductive may come into contact, logical processing is performed to correct the data in anticipation of this.

As mentioned above, when making a mask, solid development,
The resist on the substrate is exposed to light based on the semiconductor circuit pattern data that has been subjected to logic processing and shift processing, and is then developed, etched, and removed to form a mask (FIG. 8).

[Problem to be solved by the invention]

However, logic processing and shift processing are performed at once for all patterns of the semiconductor circuit that have been solidly developed.
There is a problem that as the number of gate circuits included in a semiconductor integrated circuit increases, it takes more time to create a mask, which reduces production efficiency.

The present invention has been made in view of these problems, and an object of the present invention is to provide a method for creating an exposure mask that can shorten the mask creation time.

[Means to solve the problem]

The above problem is solved by the basic gate circuits 21 to 2n designed in one design layer of circuit pattern design in an exposure mask creation method in which a mask is created based on design data of a semiconductor circuit designed in multiple layers. data modification means for logically processing and/or shifting the pattern, and patterns of gate circuits 21 to 2n subjected to the data modification means, based on addresses of gate circuit layout design data designed in another design hierarchy, The problem is solved by a method for creating an exposure mask characterized by comprising a gate circuit exposure means for exposing the mask substrate 5 in units of gate circuits.

[For production]

When designing a pattern for a semiconductor circuit, the overall image of the chip is not made concrete at the same time, but patterns for gate circuits 21 to 2n that form multiple basic types are designed, and then the gate circuit layout is designed. A semiconductor circuit is designed by dividing it into multiple layers, such as

Next, the case of creating a mask for a semiconductor exposure apparatus will be explained using a mask for n-type impurity diffusion as an example.

First, the pattern data of the n-type impurity diffusion mask for the gate circuits 21 to 2n of several basic types is read out, and this data is subjected to logic processing and shift processing to correct thickening or thinning during the semiconductor circuit formation process. do.

Next, one of the basic gate circuits 21 to 2n is called, address data for arranging this gate circuit 2 on the mask substrate 5 is called from the layout design data, and an electron beam is placed at the exposure start position of the address. guess,
A pattern for n-type impurity diffusion is exposed onto the substrate one gate circuit at a time.

This operation is performed for all remaining gate circuits 22 to 2n, and the exposure scanning of the pattern mask for n-type impurity diffusion is completed.

Thereafter, the mask is completed by performing development, etching, and resist removal according to the usual process.

The above process is applied to other patterns as well.

〔Example〕

FIG. 2 shows an example of an integrated circuit, and reference numeral l in the figure is a semiconductor integrated circuit constituted by a gate array in which a large number of gate circuits 2 are arranged.

When designing the pattern of this semiconductor integrated circuit l,
First, from the gate circuit 2, the logic circuit, RAM, RO
Gate circuits 21 to 21, which are basic types like M and I10 circuits
2n is extracted, and then a pattern design diagram 3 of each layer is designed for each basic type gate circuit 21 to 2n, and a pattern 3P of each layer such as an n-type impurity diffusion layer, a gate layer, a bulk wiring, etc.
~3P, is created (Figure 3).

Thereafter, a layout diagram 4 necessary for arranging the basic gate circuits 21 to 2n is designed (FIG. 4).

In this way, when designing the pattern of the semiconductor integrated circuit 1, the pattern is divided into a plurality of layers using the CAD method, and the data is stored in a storage device (not shown).

Next, an embodiment of the present invention will be described based on the flowchart shown in FIG. 1, taking as an example a mask for an n-type impurity diffusion pattern constituting the semiconductor integrated circuit 1.

N-type impurity diffusion patterns 3 P +t to 3P1. used in the plurality of basic gate circuits 21 to 2n shown in FIG. 4.
By reading the design data and performing shift processing on this data, thickening or thinning of etching in the semiconductor circuit manufacturing process is corrected. Furthermore, logic processing is performed before this shift processing to prevent pattern deformation or the like due to the shift processing.

The data obtained through these logical processes and shift processes is stored in a storage device.

Next, the n-type impurity diffusion pattern 3P11 of the first gate circuit 21 of the basic type is called, and the layout diagram 4
After calling the address for arranging the gate circuit 21 from the data, an electron beam is applied to the exposure start position of the mask substrate 5 corresponding to this address, and exposure is performed according to the data of the pattern 3P for n-type impurity diffusion of the gate circuit m21. Perform scanning (Figure 5.6).

In this case, if there are a plurality of blocks in which the gate circuits 21 are arranged, exposure scanning is performed in units of blocks according to the arrangement Wf[.

Pattern 3P1 as above. After completing the exposure scan, the data of the n-type impurity diffusion patterns 3P+t to 3P11+ in the other basic gate circuits 22 to 2n are subjected to similar processing on the same substrate 5 for each basic gate circuit. By doing this, mask exposure for n-type impurity diffusion is completed.

In addition, the symbol 3Pz (3Pz+~3P0)~3P in the figure
, (3Pa+ to 3P, ,) show pattern diagrams of gate layers, bulk wiring layers, etc. other than patterns for n-type impurity diffusion in the basic gate circuits 21 to 2n.

Resist 6 on mask substrate 5 after the above-mentioned exposure process
, a pattern for diffusing n-type impurities of the semiconductor circuit 1 which has been made into a latent image is formed, and when development, etching, and resist removal are performed in this order, a pattern is formed between the mask substrate 5 and the resist 6. The chromium ff7 thus formed becomes a pattern for n-type impurity diffusion.

The above process can be used when directly forming a mask, but can also be used when producing a reticle. When using a reticle, reduction projection exposure is performed using a photorepeater to produce a master mask.

In the above embodiment, the design data is divided into two layers: the pattern design of the gate circuit 2 and the layout design of the gate circuit 1232. However, as shown in FIG. When there is a necessary fixed circuit area 10 and a variable circuit area 11 whose circuit is changed according to the user's request, a gate circuit layout diagram is designed for each area and the fixed circuit area 10 is exposed and scanned. Later, the mask substrate can be exposed region by region, such as by exposing the variable circuit region 11.

Furthermore, in the embodiment described above, the pattern of the gate circuit 2 is exposed on the substrate in gate circuit units,
Hundreds of patterns for multiple gate circuits, for example gate circuit 2
The present invention cannot be applied when creating a mask for interconnecting t-horizontal wiring, and it is necessary to go through the conventional steps of solid development, logic processing, shift processing, and exposure (FIG. 8).

〔Effect of the invention〕

As described above, according to the present invention, when designing a semiconductor circuit divided into multiple hierarchies, logic processing and shift processing are performed on the pattern formed at the design stage of the basic gate circuit, and then the gate Since the pattern of the basic gate circuit is exposed sequentially in gate circuit units according to the order of the circuit layout address, it is possible to omit the need for solid development when creating masks used for bulk wiring, impurity diffusion, etc. At the same time, only the gate circuit forming the basic type is subjected to logic processing and shift processing, so that the data processing time during mask production can be significantly reduced, and the semiconductor circuit production time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing an embodiment of the present invention, FIG. 2 is a plan view showing an example of a semiconductor circuit, and FIG.
FIG. 4 is a plan view showing a pattern diagram of a gate circuit formed by designing a semiconductor circuit; FIG. 4 is a plan view showing a layout diagram of a gate circuit formed by designing a semiconductor circuit; FIG. FIG. 6 is a cross-sectional view of the mask substrate after mask exposure according to the present invention; FIG. 7 is a plan view of a mask prepared according to another embodiment of the present invention; FIG. 8 is a perspective view of a mask substrate shown in FIG. FIG. 2 is a flowchart diagram illustrating a conventional method. (Explanation of symbols) 1...Semiconductor integrated circuit, 2...Gate circuit, 21-2n...Gate circuit, 3...Layer pattern design diagram, 3P,...N-type impurity diffusion pattern, 4... Layout diagram, 5... Mask substrate, 6... Resist, 7... Chrome film. FIG. 1 is a flowchart diagram showing one embodiment of the present invention. FIG. 4 is a plan view showing a gate circuit layout area formed by designing a semiconductor circuit. FIG. 7 is a plan view of the master to be modified according to the embodiment of FIG. Figure 6

Claims (1)

[Claims] In a method for creating an exposure mask in which a mask is created based on design data of a semiconductor circuit designed in a plurality of hierarchies, a basic gate circuit ( A basic gate circuit arrangement in which a data modification means for performing logical processing and/or shift processing on the patterns 21 to 2n) and a pattern of the gate circuit (21 to 2n) to which the data modification means is applied are designed in another design hierarchy. A method for creating an exposure mask, comprising: gate circuit exposure means for exposing a mask substrate (5) in units of gate circuits based on address data.